Analog Devices AD5934 Manual page 5

Parameter
RECEIVE STAGE
Input Leakage Current
5
Input Capacitance
Feedback Capacitance, C
FB
ANALOG-TO-DIGITAL CONVERTER
Resolution
Sampling Rate
LOGIC INPUTS
Input High Voltage, V
IH
Input Low Voltage, V
IL
6
Input Current
Input Capacitance
POWER REQUIREMENTS
VDD
I , Normal Mode
DD
I , Standby Mode
DD
I , Power-Down Mode
DD
1
Temperature range for Y version = −40°C to +125°C, typical at +25°C.
2 The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5934.
3
The peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage.
Output Excitation Voltage (V p-p) = [2/3.3] × VDD
4 The dc bias value of the output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage.
Output Excitation Voltage (V p-p) = [2/3.3] × VDD
5
Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of current-
to-voltage amplifier.
6
The accumulation of the currents into Pin 8, Pin 15, and Pin 16.
Y Version
Min Typ
1
0.01
3
5
12
250
0.7 × VDD
2.7
10
17
7
9
0.7
1
Rev. A | Page 5 of 40
1
Max Unit Test Conditions/Comments
nA To VIN pin
pF Pin capacitance between VOUT and GND
pF Feedback capacitance around current-to-
voltage amplifier; appears in parallel with
feedback resistor
Bits
kSPS ADC throughput rate
0.3 × VDD
1 μA T = 25°
A
7 pF T = 25°C
A
5.5 V
15 mA VDD = 3.3 V
25 mA VDD = 5.5 V
mA VDD = 3.3 V; see the Control Register section
mA VDD = 5.5 V
5 μA VDD = 3.3 V
8 μA VDD = 5.5 V
AD5934