System Description - Analog Devices AD5934 Manual

AD5934

SYSTEM DESCRIPTION

SCL
MICROCONTROLLER
SDA
The AD5934 is a high precision, impedance converter system
solution that combines an on-board frequency generator with a
12-bit, 250 kSPS ADC. The frequency generator allows an external
complex impedance to be excited with a known frequency. The
response signal from the impedance is sampled by the on-board
ADC and DFT processed by an on-board DSP engine. The DFT
algorithm returns both a real (R) and imaginary (I) data-word at
each frequency point along the sweep. The impedance magnitude
and phase is easily calculated using the following equations:
R +
2 2
Magnitude = I
−1
Phase = tan (I/R)
To characterize an impedance profile Z(ω), generally a frequency
sweep is required such as that shown in Figure 15.
FREQUENCY (Hz)
Figure 15. Impedance vs. Frequency Profile
MCLK
COS
2
I C
INTERFACE
REAL IMAGINARY
REGISTER REGISTER
MAC CORE
(1024 DFT)
MCLK
WINDOWING
OF DATA
ADC
(12 BITS)
Figure 14. Block Overview
Rev. A | Page 12 of 40
DDS
CORE
DAC
(27 BITS)
SIN
V
AD5934
PROGRAMMABLE
GAIN AMPLIFIER
×5
×1
LPF
The AD5934 permits the user to perform a frequency sweep with
a user-defined start frequency, frequency resolution, and number
of points in the sweep. In addition, the device allows the user to
program the peak-to-peak value of the output sinusoidal signal as
an excitation to the external unknown impedance connected
between the VOUT and VIN pins.
Table 5 gives the four possible output peak-to-peak voltages and
the corresponding dc bias levels for each range for 3.3 V. These
values are ratiometric with VDD. So for a 5 V supply:
Output Excitation Voltage
Output DC Bias Voltage
Table 5. Voltage Levels Respective Bias Levels for 3.3 V
Range Output Excitation
No. Voltage Amplitude
1 1.98 V p-p
2 0.99 V p-p
3 383 mV p-p
4 198 mV p-p
The excitation signal for the transmit stage is provided on-chip
using DDS techniques that permit subhertz resolution. The receive
stage receives the input signal current from the unknown impedance,
performs signal processing, and digitizes the result. The clock for
the DDS is generated from an external reference clock that is
provided by the user at MCLK.
R VOUT
OUT
BIAS
RFB
VIN
VDD/2
= ×
for Range 1 . 1 98
5 0 .
= ×
for Range 1 . 1 48
3 3 .
Output DC Bias Level
1.48 V
0.74 V
0.31 V
0.179 V
Z(ω)
5 0 .
= −
3 V p p
3 3 .
= −
. 2 24 V p p