Ic Data - Marantz SR-19EX Service Manual

6. IC DATA

QD01 : AK4536
DZFL1
Audio AK4356
LOUT1+
I/F
SCF DAC DATT
LOUT1-
DZFR1
ROUT1+
SCF DAC DATT
ROUT1-
DZFL2
LOUT2+
SCF DAC
DATT
LOUT2-
Register
DZFR2
ROUT2+
SCF DAC
DATT
ROUT2-
DZFL3
LOUT3+
SCF DAC DATT
LOUT3-
DZFR3
ROUT3+
SCF DAC DATT
ROUT3-
LOUT1- 1
LOUT1+ 2
DZFL2 3
DZFR1 4
AK4356VQ
DZFL1 5
CAD0 6
CAD1 7
Top View
PDN 8
BICK 9
MCLK 10
DVDD 11
QU02:NJU3711
8 12 P1
DATA
13
CLK 9 1
2
V
SS 4 3
5
6
V DD 14
7
10
STB
CONTROL CIRCUIT
NJU3711
CLR 11
No. Pin Name
1 LOUT1-
2 LOUT1+
3 DZFL2
4
DZFR1
5 DZFL1
6 CAD0
7 CAD1
MCLK
8 PDN
LRCK
BI CK
9 BICK
10 MCLK
11 DVDD
CS
12 DVSS
Control
CCLK
13 SDTI1
CDTI 14 SDTI2
15 SDTI3
16 LRCK
17 SMUTE
18 CCLK
19 CDTI
SDTI1
20 CSN
SDTI2
SDTI3
No. Pin Name
21 DFS0
22 CKS0
23 CKS1
24 CKS2
25 DIF0
26 DIF1
27 DIF2
28 DZFE
29 DZFR3
30 DZFL3
33 AVDD
31 DZFR2
32 VREFH
32 VREFH
33 AVDD
31 DZFR2
34 AVSS
35 ROUT3-
30 DZFL3
36 ROUT3+
29 DZFR3 37 LOUT3-
38 LOUT3+
28 DZFE
39 ROUT2-
40 ROUT2+
27 DIF2
41 LOUT2-
26 DIF1
42 LOUT2+
43 ROUT1-
25 DIF0
44 ROUT1+
24 CKS2
Note: SMUTE, DFS0, CKS0, CKS1, CKS2, DIF0, DIF1, DIF2, DZFE pins are ORed w ith serial control reg ister.
23 CKS1
QM17:NJU3713D
DATA 10
11
CLK
P2
P3
V SS 5
P4
P5
V 18
DD
P6
P7
P8
12
STB
CONTROL CIRCUIT NJU3713
CLR 13
47
I/O Function
O DAC1 Lch Negative Analog Output Pin
O DAC1 Lch Positive Analog Outp ut Pin
O DAC2 Lch Zero Input Detect Pin
O DAC1 Rch Zero Input Detect Pin
O DAC1 Lch Zero Input Detect Pin
I Chip Address 0 Pin
I Chip Address 1 Pin
I Power-Down & Reset Pin
When "L", the AK4356 is powered-down and the control reg isters are reset to
default state. If the state of CAD0-1 change s, then the AK4356 must be reset by PDN.
I Audio Serial Data Clock Pin
I Master Clock Input Pin
- Digital Power Supply Pi n, +4.75 ~ +5.25V
- Digital Ground Pin
I DAC1 Audio Serial Data In p ut Pin
I DAC2 Audio Serial Data In p ut Pin
I DAC3 Audio Serial Data In p ut Pin
I Aud io Input Channel Clock Pin
I Soft Mute Pin (Note)
When this pin goes to "H", soft mute cycle is initialized .
When returning to "L ", the output mute releases.
I Control Data Clock Pin
I Control Data Input Pin
I Chip Select Pin
This pin should be held to "H" except for access.
I/O Function
I Double Speed Sampling Mode 0 Pin (Note)
"L": Normal Speed, "H ": Double Speed at DFS1 bit ="0".
I Input Clock Select 0 Pin (Note)
I Input Clock Select 1 Pin (Note)
I Input Clock Select 2 Pin (Note)
I Audio Data Interface Format 0 Pin (Note)
I Audio Data Interface Format 1 Pin (Note)
I Audio Data Interface Format 2 Pin (Note)
I Zero Input Detect Enable Pin (Note)
O DAC3 Rch Zero Input Detect Pin
O DAC3 Lch Zero Input Detect Pin
O DAC2 Rch Zero Input Detect Pin
I Positive Voltage Reference Input Pin, AVDD
- Analog Power Supply Pin
- Analog Ground Pin , +4.75 ~+5.25V
O DAC3 Rch Negative Analog Output Pin
O DAC3 Rch Positive Analog Output Pin
O DAC3 Lch Negative Analog Output Pin
O DAC3 Lch Positive Analog Output Pin
O DAC2 Rch Negative Analog Output Pin
O DAC2 Rch Positive Analog Output Pin
O DAC2 Lch Negative Analog Output Pin
O DAC2 Lch Positive A nalog Output Pin
O DAC1 Rch Negative A n alog Output Pin
O DAC1 Rch Positive Analo g Output Pin
QL07:NJU3718L
15
DATA
16
CLK
14 P1
15 P2
16 P3
P4
17
1 P5
2 P6
3
P7
4 P8
6 P9 V
SS 21
7 P10
V DD 28
8 P11
9 P12
17
STB
CONTROL CIRCUIT
CLR 18
Q351 : LC72722
V REF
+5V FLOUT CIN
Vdda
+
REFERENCE
–
VOLTAGE
Vssa
V REF
57 kHz
BPF
MPXIN
ANTIALIASING SMOOTHING
(SCF)
FILTER FILTER
DO
RAM ERROR CORRECTION
CL
CCB
(24 BLOCK DATA) (SOFT DECISION)
DI
CE
CLK(4.332 MHz)
T1
MEMORY CONTROL
T2 TEST
T3 to T7
OSC/DIVIDER
X IN
V REF 1
MPXIN 2
Vdda 3
Vssa 4
FLOUT 5
LC72722
CIN 6
T1 7
T2 8
T3(RDCL) 9
T4(RDDA) 10
T5(RSFT) 11
X OUT 12
Top view
19 P1
20 P2
22 P3
23 P4
24 P5
P6
25
26 P7
27 P8
1 P9
2 P10
3 P11
4 P12
5 P13
6 P14
8 P15
9 P16
10 P17
11 P18
12
P19
13 P20
14 SO
NJU3718
48
+5V
Vddd
CLOCK
PLL
RECOVERY
(57 kHz)
(1187.5 Hz)
Vssd
DATA
RDS-ID
DECODER
SYNC
SYNC/EC CONTROLLER
SYR
SYNC SYNC
DETECT-1 DETECT-2
X OUT
24 SYR
23 CE
22 DI
21 CL
20 DO
19 RDS-ID
18 SYNC
17 T7(CORREC/ARI-ID/TA/BEO)
16 T6(ERROR/57K/TP/BE1)
15 Vssd
14 Vddd
13 X IN