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Description of major ICs
LC32V4265T-25 (IC911) : DRAM
1. Pin layout
Vcc
1
I/O1
2
I/O2
3
I/O3
4
I/O4
5
Vcc
6
I/O5
7
I/O6
8
I/O7
9
I/O8
10
N.C.
13
N.C.
14
WE
15
RAS
16
N.C.
17
A0
18
A1
19
A2
20
A3
21
Vcc
22
3. Block diagram
Clock generator No.1
RAS
UCAS
LCAS
A0
A8
Vss
44
43
I/O16
42
I/O15
41
I/O14
40
I/O13
Vss
39
38
I/O12
I/O11
37
I/O10
36
I/O9
35
32
N.C.
31
LCAS
30
UCAS
29
OE
A8
28
A7
27
A6
26
25
A5
24
A4
Vss
23
Clock generator No.2
Mode control
Refresh counter
262144 memory cells
512
Low address
buffer
Sense amplifier I / O gate
Column
address buffer
2. Pin function
Symbol
Function
A0 to A8
Address input
Low address strobe
RAS
Column address strobe
UCAS
(Upper byte control)
Column address strobe
LCAS
(L+K81ower byte control)
Write enable
WE
Output enable
OE
Data I/O
I/O1 to I /O16
Vcc
Power supply
Ground
Vss
No connection
N.C.
Clock generator No.3
Lower byte
Data input buffer
I/O1 to I/O8
X16 bits
Data output buffer
I/O1 to I/O8
512X16
512
Column decoder
Substrate bias generator
Pre-decoder
NX-HD10
Vcc
Vss
WE
Upper byte
I/O1
I/O9 to I/O16
I/O9 to I/O16
I/O16
OE
1-23
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