Marantz NR1506 /U1B Service Manual page 131

W9864G6KH-6 (HDMI : U1020)
W9864G6KH-6 Pin description
5. PIN DESCRIPTION
PIN NUMBER
23 ~ 26, 22,
29 ~35
20, 21
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
51, 53
19
18
17
16
39, 15
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
PIN NAME FUNCTION
Address
A0 A11
BS0, BS1 Bank Select
Data
DQ0 DQ15
Input/ Output
Chip Select
CS
Row Address
Strobe
Column
CAS
Address Strobe Referred to
Write Enable
WE
UDQM
Input/output
mask
LDQM
CLK Clock Inputs
CKE Clock Enable
V Power
DD
V Ground
SS
Power for I/O
V
DDQ
buffer
Ground for I/O
V
SSQ
buffer
NC No Connection No connection.
W9864G6KH
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 A11. Column address: A0 A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock , CAS and WE define the
operation to be executed.
Referred to
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside
DRAM.
Separated power from V , to improve DQ noise
DD
immunity.
Separated ground from V , to improve DQ noise
SS
immunity.
Publication Release Date: Nov. 12, 2013
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131
Revision A02