Geehy SEMICONDUCTOR APM32F405/415 G Series User Manual

Arm cortex-m4 based 32-bit mcu

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User Manual

APM32F405/415xG

APM32F407/417xExG

Arm

Cortex

-M4 based 32-bit MCU

Version: V1.4

www.geehy.com

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Page 1 User Manual APM32F405/415xG APM32F407/417xExG ® ® Cortex -M4 based 32-bit MCU Version: V1.4 www.geehy.com Page 0...
Page 2: Table Of Contents
Contents Introduction and document description rules ........8 Introduction........................ 8 Document description rules ..................8 System architecture ................12 Full name and abbreviation description of terms ............ 12 System architecture block diagram ................. 12 Memory mapping ....................15 Startup configuration ....................15 FLASH memory ...................
Page 3 Reset and clock (RCM) ............... 60 Full name and abbreviation description of terms ............ 60 Reset management unit (RMU) ................60 Clock management unit (CMU)................63 Register address mapping ..................70 Register functional description ................71 Power management unit (PMU) ............101 Full name and abbreviation description of terms ..........
Page 4 General-Purpose Input/Output Pin (GPIO) ........149 Full name and abbreviation description of terms ..........149 Main characteristics ....................149 Structure block diagram ..................150 Functional description ................... 150 Register address mapping ..................154 Register functional description ................154 Timer overview .................. 159 Full name and abbreviation description of terms ..........
Page 5 Main characteristics ....................258 Structure block diagram ..................258 Functional description ................... 258 Register address mapping ..................260 Register functional description ................261 Watchdog timer (WDT) ..............265 Introduction......................265 Independent watchdog timer (IWDT) ..............265 Window watchdog timer (WWDT) ................. 267 IWDT register address mappin ................
Page 6 Introduction......................314 Main characteristics ....................314 Functional description ................... 316 Register address mapping ..................330 Register functional description ................330 Internal integrated circuit interface (I2C) ........338 Full name and abbreviation description of terms ..........338 Introduction......................338 Main characteristics ....................338 Structure block diagram ..................
Page 7 OTG_FS global register address mapping ............453 OTG_FS global register functional description ............. 454 OTG_FS host mode register address mapping ............ 468 OTG_FS host mode register functional description..........469 OTG_FS device mode register address mapping ..........475 OTG_FS device mode register functional description .......... 476 Full-speed OTG power and clock gating control register (OTG_FS_PCGCTRL) 491 OTG_HS1 global register address mapping ............
Page 8 Introduction......................635 Structure block diagram ..................635 Functional description ................... 635 Register address mapping ..................639 Register functional description ................639 Random number generator (RNG) ..........645 Introduction......................645 Main characteristics ....................645 Functional description ................... 645 Register address mapping ..................646 Register functional description ................
Page 9: Introduction And Document Description Rules
Introduction and document description rules Introduction This user manual provides application developers with all the information about how to use MCU (micro-controller) system architecture, memory and peripherals. ® ® ® ® For information about Arm Cortex -M4 core, please refer to Arm Cortex Technical Reference Manual;...
Page 10 R/W mode Description Abbreviation The software can read and set this bit, and writing 0 has no read/set effect on this bit. The software can read this bit and writing 0 or 1 can trigger an read-only write trigger RT_W event but has no effect on the value of this bit.
Page 11 Full name in English English abbreviation Output Interrupt Data DATA Size SIZE Divider Prescaler Multiplier Period Table 3 Full Name and Abbreviation of Modules Full name in English English abbreviation External Memory Controller EMMC Static Memory Controller Dynamic memory Controller Reset and Clock Management Unit Power Management Unit Backup Register...
Page 12 Full name in English English abbreviation Controller Area Network Secure Digital Input and Output SDIO Universal Serial Bus Full-Speed Device USBD Analog-to-Digital Converter Digital-to-Analog Converter Cyclic Redundancy Check Calculation Unit Float Point Unit www.geehy.com Page 11...
Page 13: System Architecture
System architecture Full name and abbreviation description of terms Table 4 Full name and abbreviation description of terms Full name in English English abbreviation Advanced High-Performance Bus Advanced Peripheral Bus Core Couple Memory System architecture block diagram ® Cortex ® -M4 core in the product has FPU, while the FPU of other series of products (unless otherwise specified) is beyond the core.
Page 14 Name Description Connect the main interface of DMA peripherals and the bus matrix. DMA peripheral bus It can not only realize access of DMA to the peripherals on AHB, but also realize transmission among memories. Connect the main interface of Ethernet DMA and the bus matrix. Ethernet DMA bus The data are loaded/stored in the memory through Ethernet DMA.
Page 15 Figure 1 APM32F405/415xG、APM32F407/417xExG System Architecture Block Diagram NVIC M4 with FPU JTAG/SWD CCM Data RAM D-bus I Code Ethernet MAC D Code Fast USB OTG Main SRAM1 Annex SRAM2 DMA1 AHB bus matrix DMA2 SRAM/External EMMC memory AHB1 Fast USB OTG GPIO A-I Camera interface CRYP...
Page 16: Memory Mapping
resources. Only one of two USB OTG_HS can be used at the same time. Their difference is: one has on-chip UTMI USB PHY (there is internal PLL with 60MHz output), while the other does not have. Memory mapping The assigned addresses of memory mapping include the core (including core peripherals), on-chip Flash (including main memory area, system memory area and option bytes), on-chip SRAM, and bus peripherals (including AHB and APB peripherals).
Page 17 startup mode. Table 6 Startup Mode Configuration and Access Mode Startup mode configuration Startup mode Access mode BOOT1 pin BOOT0 pin The main flash memory is mapped to the boot Main flash space, but it can still be accessed at its original memory address, that is, the contents of the flash memory （Flash）...
Page 18: Flash Memory
FLASH memory Full name and abbreviation description of terms Table 7 Full name and abbreviation description of terms Full name in English English abbreviation Flash Memory Controller One-time Programmable Adaptive Real-time Introduction This chapter mainly introduces the storage structure, read, erase, write, read/write protection, unlock/lock characteristics of Flash, and the involved register functional description.
Page 19: Flash Memory Structure
Flash memory structure Table 8 Flash Memory Structure Block Name Address range Size (byte) Sector 0x0800 0000–0x0800 3FFF Sector 0 0x0800 4000–0x0800 7FFF Sector 1 0x0800 8000–0x0800 BFFF Sector 2 0x0800 C000–0x0800 FFFF Sector 3 Main memory block 0x0801 0000 – 0x0801 FFFF Sector 4 0x0802 0000 –...
Page 20 When PMU_CTRL register VOSSEL=0, the maximum value of HCLK is 144MHz; when VOSSEL=1, the maximum value of HCLK is 168MHz. CPU frequency can be adjusted by selecting different wait cycles, so as to adjust the reading speed of Flash. Adaptive real-time memory accelerator (ART) ART accelerator can improve the execution speed of Flash, so that the Flash can execute programs with fewer wait cycles at high CPU frequency.
Page 21 Erase main memory block Flash can support sector erase and mass erase (erase all). Mass erase does not affect OTP sector or configuration sector. Main memory page erase Page erase is an independent erase according to the main memory area page selected by the program, which will not have any impact on the page not selected for erasure.
Page 22 the write operation will be suspended, a programming parallelism error will be generated, and the PGPRLERR bit will be set to 1. Programming sequence error The correct programming sequence is: Confirm the operation currently not performed to the Flash through FMC_STS[BUSY] Set FMC_CTRL[PG] to 1 Conduct write operation...
Page 23 Address Bit field Option byte Functional description RSTSTOP Reset occurs when entering the stop mode Reset occurs when entering the standby RSTSTDB mode 15:8 RPROT Read protection 11:0 NWPROT No write protection 0x1FFF C008 15:12 Erase/write option byte The option byte must be unlocked before erasing/writing. The programming sequence of option byte is: Confirm the operation currently not performed to the Flash through FMC_STS[BUSY]...
Page 24 Write protection In order to prevent accidental rewriting of Flash due to program disorder, in default state, the Flash supports write protection function of up to 12 user sectors; when the corresponding bit of the FMC_OPTCTRL[NWPROT] bit field is at low level, the corresponding sector will be write-protected, and the sector cannot be erased/written.
Page 25 Level 0 When FMC_OPTCTRL[RPROT]=0xAA, the read protection function is not used for Flash. Level 1 When FMC_OPTCTRL[RPROT]=any value (except 0xAA and 0xCC), the read protection level is 1. At this time, if the level is adjusted to Level 0, mass erase operation will be performed to erase all data of Flash and backup SRAM.
Page 26: Register Address Mapping
can be programmed only when the value of the lock block is 0x00. The value of the lock block can only be 0x00 or 0xFF; otherwise, the OTP byte cannot be used normally. Note that neither data block nor lock block of OTP can be erased. Register address mapping Table 14 FMC Register Address Mapping Register name...
Page 27 Field Name Description Instruction Cache Reset ICACHERST 0: Invalid 1: Reset Data Cache Reset DCACHERST 0: Invalid 1: Reset 31:13 Reserved Flash key register (FMC_KEY) Offset address: 0x04 Reset value: 0x0000 0000 Field Name Description 31:0 When unlocking, this key needs to be written into this register. FMC_OPTKEY Offset address: 0x08 Reset value: 0x0000 0000...
Page 28 Field Name Description Programming Sequence Error PGSEQERR RC_W1 This bit will be set to 1 when a programming sequence error occurs. 15:8 Reserved Busy BUSY This bit will be set to 1 when operation is performed for Flash. 31:17 Reserved Flash control register (FMC_CTRL) Offset address: 0x10 Reset value: 0x8000 0000...
Page 29 Field Name Description Error interrupt Enable ERRINTE 0: Disable 1: Enable 30:26 Reserved Lock When this bit is set to 1, it means that this register is locked; when LOCK the unlocking sequence is detected, it will be cleared to zero by the hardware.
Page 30 Field Name Description Not Write Protect 27:16 NWPROT 0: Write protection isenabled 1: Write protection is disabled 31:28 Reserved www.geehy.com Page 29...
Page 31: External Memory Controller (Emmc)
External Memory Controller (EMMC) Full name and abbreviation description of terms Table 15 Full name and abbreviation description of terms English Full name in English abbreviation Static Random Access Memory SRAM Read Only Memory Pseudo Static Random Access Memory PSRAM Random Access Memory Synchronous Dynamic Random Access Memory SDRAM...
Page 32: Smc Structure Block Diagram
memory and is distinguished by chip selection signal; only one external device can be accessed at any moment; each memory block can be configured separately, and the timing can be programmed for external devices. SMC Structure Block Diagram SMC consists of five parts: AHB bus interface, configuration register, NORFlash controller, NANDFlash/PC card controller and external device interface, specifically as shown in the figure below: Figure 2 SMC Block Diagram...
Page 33 When the width of AHB accessing external data is larger than that of memory data, the access operation will be automatically cut to be consistent with the width of external data for transmission. When the width of AHB accessing external data is less than that of memory data, if the external memory has the function of byte selection, it can transmit data normally through byte channel;...
Page 34 rules:  When the width of external memory data is 8 bits, HADDR[25:0] is connected to SMC_ A [25:0], while SMC_A[25:0] is connected to the external memory address line.  When the width of external memory data is 16 bits, HADDR[25:1] is connected to SMC_ A [24:0], while SMC_A[24:0] is connected to the external memory address line.
Page 35 SMC signal name Signal direction Function NL（=NADV） Output Effective address signal NBL[1] Output High byte enable NBL[0] Output Low byte enable Note: The output signal of the controller changes at the rising edge of the internal clock; in the synchronous write mode, the output data changes at the falling edge of the memory clock. NOR Flash/PSRAM controller provides programmable timing parameters for external memory, including the parameters in the following table: Table 20 Programmable NOR/PSRAM Timing Parameters...
Page 36 SMC memory block Storage space Start address End address General 0x80000000 0x83FFFFFF Memory block 3-NAND flash memory Attributes 0x88000000 0x8BFFFFFF General 0x90000000 0x93FFFFFF Memory block 4-PC Attributes 0x98000000 0x9BFFFFFF card 0x9C000000 0x9FFFFFFF NAND flash memory block is divided into three blocks in part of the low-byte area, and different blocks can be accessed through HADDR [17:16].
Page 37 SMC signal name Signal direction Function Output Write enable signal NWAIT/INT[3:2] Input NAND Flash ready/busy input signal A[17] Output NAND Flash address latch signal (ALE) NAND Flash command latch signal A[16] Output (CLE) 8-bit multiplexing: D[7:0] bidirectional Input/Output address/data bus D[15:0] 16-bit multiplexing: D[15:0] bidirectional Input/Output...
Page 38: Smc Register Address Mapping
Table 25 Programmable NAND/PC Card Timing Parameters Operation Parameter Function Unit Minimum Maximum mode Memory data The time of holding the data bus high- bus in high-impedance state Write impedance after starting write operation time The number of clocks holding the address after Memory hold AHB clock transmitting the command,...
Page 39: Smc Register Functional Description
SMC register functional description NOR flash memory and PSRAM control register SRAM/NOR flash memory chip selection control register 1…4 (SMC_CSCTRL1…4) Offset address: 0x8*(x-1), x=1…4 Reset value: 0x0000 30DX Field Name Description Enable the Corresponding Memory Bank MBKEN 0: Disable 1: Enable Address/Data Multiplexing Enable This bit is effective only for NORFlash and PSRAM.
Page 40 Field Name Description 0: NWAIT signal is effective in the data period before waiting 1: NWAIT signal is effective in the waiting period Write Memory Enable This bit is used to enable write operation of SMC for the memory. WREN 0: Disable write;...
Page 41 Field Name Description …… 1111: 16 HCLK clock cycles Note: In synchronous operation, this parameter is meaningless and is always 1 memory clock cycle Address-Hold Time Configure Only apply to NOR flash memory operation in SRAM, ROM and asynchronous bus multiplexing mode. 0000: Reserved ADDRHLDCFG 0001: 2 HCLK clock cycles...
Page 42 Field Name Description Note: When accessing asynchronous NOR flash memory, SRAM or ROM, this parameter is invalid. When operating CRAM, this parameter is 0. Asynchronous Access Mode Configure Valid only when EXTMODEEN bit of SMC_CSCTRLX register is 1. 00: Access mode A 29:28 ASYNCACCCFG 01: Access mode B...
Page 43 Field Name Description …… 1111: 16 HCLK clock cycles Clock divide ratio (for CLK signal Configure) Cycle of CLK clock output signal, expressed by the number of HCLK cycles. 0000: Reserved 23:20 CLKDIVCFG 0001: CLK cycle=2×HCLK cycle 0010: CLK cycle =3×HCLK cycle 1111: CLK cycle=16×HCLK cycle (default value after reset) This bit is invalid in asynchronous NOR Flash, SRAM or ROM access mode.
Page 44 Field Name Description Memory Type Configure MTYPECFG 0: PC card, CF card, CF+ card or PCMCIA 1: NAND flash memory Databus Width Configure 16 bits must be used for PC Card. DBWIDCFG 00: 8 bits 01: 16 bits Others reserved ECC Computation Logic Enable ECCEN 0: Disable and reset ECC...
Page 45 Field Name Description Interrupt High-Level Generate Flag This bit is set to 1 by hardware and cleared by software. IHLFLG 0: Not generate 1: Generate Interrupt Falling Edge Generate Flag This bit is set to 1 by hardware and cleared by software. IFEFLG 0: Not generate 1: Generate...
Page 46 Field Name Description Common Memory x Wait Time Configure This bit takes HCLK as the clock cycle and defines the minimum hold time of the command. After the defined time, if the waiting signal is effective low, the hold time of the command will become longer.
Page 47 Field Name Description Attribute Memory x Wait Time Configure This bit takes HCLK as the clock cycle and defines the minimum hold time of the command. After the defined time, if the waiting signal is effective low, the hold time of the command will become longer.
Page 48: Dmc Introduction
Field Name Description I/O x Wait Time Configure This bit takes HCLK as the clock cycle and defines the minimum hold time of the command. After the defined time, if the waiting signal is effective low, the hold time of the command will become longer. 0000 0000: Reserved 15:8 WAIT...
Page 49: Dmc Structure Block Diagram
DMC structure block diagram Figure 3 DMC structure block diagram Memory controller Host interface unit Memory interface unit Address decoder Host interface controller Control register Off-chip SDR-SDRAM Data FIFO SDR-SDRAM controller Address FIFO Refresh unit DMC functional description DMC external memory interface The signal with the prefix "N"...
Page 50 Signal Name Input/Output Function Input/Output Bidirectional data Input/Output Bidirectional data Input/Output Bidirectional data Input/Output Bidirectional data Input/Output Bidirectional data Input/Output PH13 Bidirectional data Input/Output PH15 Bidirectional data Input/Output Bidirectional data Input/Output Bidirectional data Input/Output PH10 Bidirectional data Input/Output PD10 Bidirectional data Input/Output PD12 Bidirectional data...
Page 51: Dmc Register Address Mapping
 Corresponding pin of row address: A0-A9, totally 11 bits  Corresponding pin of column address: A0-A8, totally 8 bits  Corresponding pin of Bank: BA0, 1 bit The row address width bit of the configuration register DMC _CFG is set to 1010;...
Page 52 Field Name Description Column Address Width Configure 0000-0110: Reserved 0111: The column address is 8 bits 12:9 CAWCFG 1000: The column address is 9 bits …… 1110: The column address is 15 bits 1111: Reserved Data Width Configure 14:13 DWCFG 00: SDRAM data bit width is 16 bits Others reserved 31:15...
Page 53 Field Name Description Auto-Refresh Period Select These bits are used to define the minimum time interval between two auto-refresh commands. 0000: 1 clock cycle 17:14 ARPSEL 0001: 2 clock cycles …… 1111: 16 clock cycles Minimum interval time from exiting self-refresh switch to activation command or auto-refresh read command 21:18 XSR0...
Page 54 Field Name Description Put SDRM in Self-Refresh Mode Enable SRMEN 0: Invalid 1: Enable Put SDRM in Power-Down Mode Enable PDMEN 0: Disable 1: Enable Precharge Algorithm Configure 0: Precharge the row immediately after read operation. PCACFG 1: Precharge the row after a period of delay upon completion of read operation.
Page 55 Switch register (DMC_SW) Offset address: 0x0400 Reset value: 0x0000 0000 Field Name Description Memory Controller Function Switch MCSW 0: Select SMC 1: Select DMC 31:1 Reserved Control register 2 (DMC_CTRL2) Offset address: 0x0404 Reset value: 0x0000 002E Field Name Description Clock Phase Configure CPHACFG 0: The system clock is not reverse...
Page 56: System Configuration Controller (Syscfg)
System configuration controller (SYSCFG) Main characteristics Remapping of configuration memory Select MAC PHY interface Configure external interrupt of GPIO Control I/O compensation cell I/O compensation cell When the I/O output buffer speed is configured as 50MHz or 100MHz, the I/O port noise will affect the power supply voltage.
Page 57 Field Name Description Memory Mapping Select Control the memory mapping address 0x0000 0000. After reset, the parameters of these bits are determined by actual BOOT. 00: Main flash mapping address: 0x0000 0000 MMSEL 01: System flash mapping address: 0x0000 0000 10: SMC Bank1 (NOR/PSRAM1 and 2) mapping address: 0x0000 0000 11: Embedded SRAM1 mapping address: 0x0000 0000 31:2...
Page 58 Reset value: 0x0000 0000 These bits are controlled by software to be rewritten to select the external interrupt source of EINTx(x=0…3). Field Name Description EINT0 Configure EINT0 These bits are controlled by software to be rewritten to select the external interrupt source of EINT0.
Page 59 Field Name Description EINT8 Configure EINT8 These bits are controlled by software to be rewritten to select the external interrupt source of EINT8. EINT9 Configure EINT9 These bits are controlled by software to be rewritten to select the external interrupt source of EINT9. EINT10 Configure 11:8 EINT10...
Page 60 Field Name Description Compensation Cell Ready Flag RDYFLG 0: Not ready 1: Ready 31:9 Reserved www.geehy.com Page 59...
Page 61: Reset And Clock (Rcm)
Reset and clock (RCM) Full name and abbreviation description of terms Table 31 Full name and abbreviation description of terms Full name in English English abbreviation Reset and Clock Management Reset Power-On Reset Power-Down Reset High Speed External Clock HSECLK Low Speed External Clock LSECLK High Speed Internal Clock...
Page 62 A system reset will occur in case of any of the above events. Besides, the reset event source can be identified by viewing the reset flag bit in RCM_CSTS (control/state register). When the system is reset, all registers except the registers in RCM_CSTS (control/state register) reset flag bit and backup domain will be reset to the reset state.
Page 63 Figure 4 "System Reset" Reset Circuit External System Filter reset reset NRST WWDT reset IWDT reset Pulse Power reset generator （20μs） Software reset Low-power management reset Power reset "Power reset" reset source "Power reset" reset source is as follows:  Power-on reset (POR) ...
Page 64: Clock Management Unit (Cmu)
Clock management unit (CMU) The clock sources of the whole system are: HSECLK, LSECLK, HSICLK, LSICLK, PLL1 and PLL2. For the characteristics of the clock source, please refer to the relevant chapter of "Electrical Characteristics" in the data manual. External clock source The external clock signal includes HSECLK (high-speed external clock signal) and LSECLK (low-speed external clock signal).
Page 65 Table 32 Clock Source Generating HSECLK Name Description Provide clock to MCU through OSC_IN pin. The signal can be generated by ordinary function signal transmitter (in debugging), crystal oscillator and other signal generators; the waveform can be square wave, sine wave or triangle wave with 50% duty cycle, External clock source and the maximum frequency is up to 26MHz.
Page 66 Name Description The clock is provided to MCU by the resonator, and the resonator includes crystal resonator and ceramic resonator. The frequency is 32.768kHz. OSC32_IN and OSC32_OUT need to be connected to the oscillator External crystal/ceramic which can be enabled and disabled through LSEEN bit in resonator RCM_BDCTRL (clock backup domain control register).
Page 67 LSICLK can be enabled or disabled by LSIEN bit in RCM_CST register. LSIRDYFLG bit in RCM_CTRL indicates whether the low-speed internal oscillator is stable. At startup stage, the clock is not released until this bit is set to "1" by hardware. If allowed in RCM_INT register, LSICLK ready interrupt request signal will be generated.
Page 68 Clock tree Figure 6 APM32F405/415xG、APM32F407/417xExG Clock Tree MACTXCLK PHY ETH /2,20 SYSCFG_PMCFG[ETHSEL] 25-50MHz MACRXCLK MACRMIICLK USB2.0 OTG_HS ULPI 24-60MHz Cortex System Clock LSICLK IWDTCLK 40KHz FCLK RTCSEL[1:0] SMCCLK LSECLK /2,4 DMCCLK OSC32_OUT 32.768 OSC32_IN /2...31 OSC_OUT 4-16MHz HSECLK 168MHz MAX OSC_IN HCLK SYSCLK...
Page 69 PLCK1 and PLCK2 are clock signal connected to APB1 and APB2 respectively. ® ® FCLK is free running clock of Arm Cortex -M4 with FPU. The frequency of AHB, APB2 (high-speed APB) and APB1 (low-speed APB) domains can be configured through multiple prescalers. Besides, the maximum frequency of AHB domain is 168MHz, the maximum frequency of APB2 domain is 84MHz, and the maximum allowable frequency of APB1 is 42MHz.
Page 70 Table 34 Working Condition of RTC When Different Clock Sources are Selected Clock source Working condition As long as V maintains power supply, RTC will continue to LSECLK is selected as RTC clock work even if V is powered off LSICLK is selected as automatic If V is powered off, the automatic wake-up unit state cannot...
Page 71: Register Address Mapping
Note: When CSS is activated by software and HSECLK fails, CSS interrupt and NMI (non-maskable interrupt) will be generated. Since NMI is executed continuously before CSS interrupt is cleared, CSSCLR bit in RCM_INT register shall be set to clear the interrupt. TMR5-based internal/external clock measurement Through the input capture function of TMR5 Channel 4, the frequency of certain clock source generators can be indirectly measured.
Page 72: Register Functional Description
Register name Description Offset address RCM_PLL1CFG PLL1 configuration register 0x04 RCM_CFG Clock configuration register 0x08 RCM_INT Clock interrupt register 0x0C RCM_AHB1RST AHB1 peripheral reset register 0x10 RCM_AHB2RST AHB2 peripheral reset register 0x14 RCM_AHB3RST AHB3 peripheral reset register 0x18 RCM_APB1RST APB1 peripheral reset register 0x20 RCM_APB2RST APB2 peripheral reset register...
Page 73 Field Name Description High Speed Internal Clock Enable Set to 1 or cleared by software. HSICLK is an RC oscillator. When one of the following conditions occurs, it will be set to 1 by the hardware: power-on start, software reset, wake-up from standby mode, wake-up from stop mode, failure of HSIEN external high-speed clock source (as system clock or providing system clock through PLL).
Page 74 Field Name Description PLL1 Enable When entering the standby and stop mode, this bit is cleared to 0 by the hardware; when PLL1CLK has been configured as the clock source of the system clock (or in the process of configuration), this bit cannot PLL1EN be set to 0;...
Page 75 Field Name Description PLL Multiplication Factor A It is used to calculate VCO frequency. The calculation formula is f output)= f VCO input)×PLL1A, and the formula is established only when PLL1A is 50~432. 000000000: PLLA=0 (error) 000000001: PLLA=1 (error) …… 14:6 PLL1A 000110010：PLLA=50...
Page 76 Field Name Description System Clock Source Select When returning from stop or standby mode or the HSECLK directly or indirectly used as system clock fails, the hardware selects HSICLK as system clock by force (if the clock security system has been started) SCLKSEL 00: HSICLK is used as system clock...
Page 77 Field Name Description APB2 Clock Prescaler Factor Configure Prescaler factor used to control low-speed APB2 clock (PCLK2). 0xx: No frequency division for HCLK 100: HCLK 2-divided frequency 15:13 APB2PSC 101: HCLK 4-divided frequency 110: HCLK 8-divided frequency 111: HCLK 16-divided frequency Note: PCLK2 shall not be greater than 84MHz.
Page 78 Field Name Description Main Clock Output2 Select 00: SYSCLK is output as a clock 31:30 MCO2SEL 01: PLL2CLK is output as a clock 10: HSECLK is output as a clock 11: PLL1CLK is output as a clock Clock interrupt register (RCM_INT) Offset address: 0x0C Reset value: 0x0000 0000 Access: Access in the form of word, half word and byte, without wai cycle.
Page 79 Field Name Description Reserved Clock Security System Interrupt Flag When the external high-speed oscillator clock fails, it is set to 1 by hardware. CSSFLG When CSSCLR is set to 1 by software, this bit will be cleared. 0: No security system interrupt caused by HSE clock failure 1: Clock security system interrupt is caused by HSE clock failure LSICLK Ready Interrupt Enable Enable or disable internal 28kHz RC oscillator ready interrupt.
Page 80 Field Name Description HSECLK Ready Interrupt Clear Clear HSE ready interrupt flag bit HSERDYFLG. HSERDYCLR 0: No effect 1: Clear PLL1 Ready Interrupt Clear Clear PLL1 ready interrupt flag bit PLL1RDYFLG. PLL1RDYCLR 0: No effect 1: Clear PLL2 Ready Interrupt Clear Clear PLL2 ready interrupt flag bit PLL2RDYFLG.
Page 81 Field Name Description GPIOG Reset PGRST 0: No effect 1: Reset GPIOH Reset PHRST 0: No effect 1: Reset GPIOI Reset PIRST 0: No effect 1: Reset 11:9 Reserved CRC Reset CRCRST 0: No effect 1: Reset 20:13 Reserved DMA1 Reset DMA1RST 0: No effect 1: Reset...
Page 82 Field Name Description BN Reset BNRST 0: No effect 1: Reset SM Reset SMRST 0: No effect 1: Reset CRYP Reset CRYPRST 0: No effect 1: Reset HASH Processor Reset HASHPRST 0: No effect 1: Reset RNG Reset RNGRST 0: No effect 1: Reset OTG_FS Reset OTGFSRST...
Page 83 Field Name Description TMR4 Reset TMR4RST 0: No effect 1: Reset TMR5 Reset TMR5RST 0: No effect 1: Reset TMR6 Reset TMR6RST 0: No effect 1: Reset TMR7 Reset TMR7RST 0: No effect 1: Reset TMR12 Reset TMR12RST 0: No effect 1: Reset TMR13 Reset TMR13RST...
Page 84 Field Name Description UART5 Reset UART5RST 0: No effect 1: Reset I2C1 Reset I2C1RST 0: No effect 1: Reset I2C2 Reset I2C2RST 0: No effect 1: Reset I2C3 Reset I2C3RST 0: No effect 1: Reset Reserved CAN1 Reset CAN1RST 0: No effect 1: Reset CAN2 Reset CAN2RST...
Page 85 Field Name Description USART1 Reset USART1RST 0: No effect 1: Reset USART6 Reset USART6RST 0: No effect 1: Reset Reserved ADC Interface Reset 0: No effect ADCRST 1: Reset Note: It takes effect for all ADCs 10:9 Reserved SDIO Reset SDIORST 0: No effect 1: Reset...
Page 86 Field Name Description GPIOB Clock Enable PBEN 0: Disable 1: Enable GPIOC Clock Enable PCEN 0: Disable 1: Enable GPIOD Clock Enable PDEN 0: Disable 1: Enable GPIOE Clock Enable PEEN 0: Disable 1: Enable GPIOF Clock Enable PFEN 0: Disable 1: Enable GPIOG Clock Enable PGEN...
Page 87 Field Name Description ETH Clock Enable ETHEN 0: Disable 1: Enable ETH Transmission Clock Enable ETHTXEN 0: Disable 1: Enable ETH Reception Clock Enable ETHRXEN 0: Disable 1: Enable ETH PTP Clock Enable ETHPTPEN 0: Disable 1: Enable 28:26 Reserved OTG_HS1 Clock Enable OTGHS1EN 0: Disable...
Page 88 Field Name Description RNG Clock Enable RNGEN 0: Disable 1: Enable OTG_FS Clock Enable OTGFSEN 0: Disable 1: Enable 31:8 Reserved AHB3 peripheral clock enable register (RCM_AHB3CLKEN) Offset address: 0x18 Reset value: 0x0000 0000 Access: Access in the form of word, half word and byte, without wait cycle. Field Name Description...
Page 89 Field Name Description TMR12 Clock Enable TMR12EN 0: Disable 1: Enable TMR13 Clock Enable TMR13EN 0: Disable 1: Enable TMR14 Clock Enable TMR14EN 0: Disable 1: Enable 10:9 Reserved WWDT Clock Enable WWDTEN 0: Disable 1: Enable 13:12 Reserved SPI2 Clock Enable SPI2EN 0: Disable 1: Enable...
Page 90 Field Name Description CAN1 Clock Enable CAN1EN 0: Disable 1: Enable CAN2 Clock Enable CAN2EN 0: Disable 1: Enable Reserved PMU Clock Enable PMUEN 0: Disable 1: Enable DAC Interface Clock Enable DACEN 0: Disable 1: Enable 31:30 Reserved APB2 peripheral clock enable register (RCM_APB2CLKEN) Offset address: 0x44 Reset value: 0x0000 0000 Access: Access in the form of word, half word and byte, without wait cycle.
Page 91 Field Name Description ADC3 Interface Clock Enable ADC3EN 0: Disable 1: Enable SDIO Clock Enable SDIOEN 0: Disable 1: Enable SPI1 Clock Enable SPI1EN 0: Disable 1: Enable Reserved SYSCFG Module Clock Enable SYSCFGEN 0: Disable 1: Enable Reserved TMR9 Clock Enable TMR9EN 0: Disable 1: Enable...
Page 92 Field Name Description GPIOD Clock Enable 0: Disable PDEN 1: Enable GPIOE Clock Enable 0: Disable PEEN 1: Enable GPIOF Clock Enable 0: Disable PFEN 1: Enable GPIOG Clock Enable 0: Disable PGEN 1: Enable GPIOH Clock Enable 0: Disable PHEN 1: Enable GPIOI Clock Enable...
Page 93 Field Name Description Reserved 24:23 ETH Clock Enable 0: Disable ETHEN 1: Enable ETH Transmission Clock Enable 0: Disable ETHTXEN 1: Enable ETH Reception Clock Enable 0: Disable ETHRXEN 1: Enable ETH PTP Clock Enable 0: Disable ETHPTPEN 1: Enable Reserved 28:26 OTG_HS1 Clock Enable...
Page 94 Field Name Description CRYP Clock Enable CRYPEN 0: Disable 1: Enable HASH Processor Clock Enable HASHPEN 0: Disable 1: Enable RNG Clock Enable RNGEN 0: Disable 1: Enable OTG_FS Clock Enable OTGFSEN 0: Disable 1: Enable 31:8 Reserved AHB3 peripheral clock enable register in low-power mode (RCM_LPAHB3CLKEN) Offset address: 0x58 Reset value: 0x0000 0001...
Page 95 Field Name Description TMR4 Clock Enable TMR4EN 0: Disable 1: Enable TMR5 Clock Enable TMR5EN 0: Disable 1: Enable TMR6 Clock Enable TMR6EN 0: Disable 1: Enable TMR7 Clock Enable TMR7EN 0: Disable 1: Enable TMR12 Clock Enable TMR12EN 0: Disable 1: Enable TMR13 Clock Enable TMR13EN...
Page 96 Field Name Description UART5 Clock Enable UART5EN 0: Disable 1: Enable I2C1 Clock Enable I2C1EN 0: Disable 1: Enable I2C2 Clock Enable I2C2EN 0: Disable 1: Enable I2C3 Clock Enable I2C3EN 0: Disable 1: Enable Reserved CAN1 Clock Enable CAN1EN 0: Disable 1: Enable CAN2 Clock Enable...
Page 97 Field Name Description Reserved USART1 Clock Enable USART1EN 0: Disable 1: Enable USART6 Clock Enable USART6EN 0: Disable 1: Enable Reserved ADC1 Interface Clock Enable ADC1EN 0: Disable 1: Enable ADC2 Interface Clock Enable ADC2EN 0: Disable 1: Enable ADC3 Interface Clock Enable ADC3EN 0: Disable 1: Enable...
Page 98 When the register is accessed continuously, the waiting state will be inserted. Note: Only when BPWEN bit in PMU_CTRL is set to 1, can LSEEN, LSEBCFG, RTCSRCSEL and RTCCLKEN be changed. Field Name Description Low-Speed External Oscillator Enable LSEEN 0: Disable 1: Enable Low-Speed External Clock Ready Flag When LSECLK is stable, this bit is set to 1 by hardware, and...
Page 99 Field Name Description Low-Speed Internal Oscillator Enable Set to 1 or cleared by software. LSIEN 0: Disable 1: Enable Low-Speed Internal Oscillator Ready Flag When LSICLK is stable, this bit is set to 1 by hardware, and when it is unstable, it is cleared by hardware. LSIRDYFLG 0: Not ready 1.
Page 100 Field Name Description Low Power Reset Flag When low-power management is reset, it is set to 1 by hardware and cleared by software by writing RSTFLGCLR bit. LPWRRSTFLG 0: Reset does did not occur 1: Reset occurred Spread spectrum clock configuration register (RCM_SSCCFG) Offset address: 0x80 Reset value: 0x0000 0000 Access: Access in the form of word, half word and byte, with 0 to 3 wait cycles.
Page 101 Field Name Description 000000001: PLL2A=1 (error) …… 000110010：PLL2A=50 …… 001100011：PLL2A=99 001100100：PLL2A=100 …… 110110000：PLL2A=432 110110001: PLL2A=433 (error) …… 111111111: PLL2A=511 (error) 27:15 Reserved Division Factor This bit can be set or cleared by software, and this variable can be controlled to change the clock frequency provided to I2S. This bit can be set only when PLL2 is disabled.
Page 102: Power Management Unit (Pmu)
Power management unit (PMU) Full name and abbreviation description of terms Table 36 Full name and abbreviation description of terms Full name in English English abbreviation Power Management Unit Power On Reset Power Down Reset Brown-out Reset Power Voltage Detector Introduction The power supply is the basis for stable operation of a system.
Page 103: Structure Block Diagram
Structure block diagram Figure 37 Power Supply Structure Block Diagram Backup power domain LSECLK (crystal resonator) Backup register Low-voltage detector Wake-up Backup SRAM logic power domain I/O circuit GPIO 1.3V power domain CAP_1 Core CAP_2 BYPASS_REG Flash SRAM Voltage regulator AHB digital peripheral APB digital...
Page 104  Normal mode: In this mode, 1.3V power supply area operates at full power, and the level of the output voltage can be selected through VOSSEL bit of the register PMU_CTRL.  Stop mode: In this mode, 1.3V power supply area works in low-power state, all clocks are off, peripherals stop working and the set voltage output level remains unchanged.
Page 105 Figure 9 Power-on Reset and Power-down Reset Oscillogram Hysteresis voltage Hysteresis time Reset Brownout reset (BOR) When it is detected that V is lower than the threshold voltage V , the chip will automatically remain in reset state, and V can be configured through option byte.
Page 106 Figure 10 BOR Threshold Oscillogram BOR threshold Hysteresis voltage Reset Power voltage detector (PVD) A threshold can be set for PVD to monitor whether V is higher or lower than the threshold. If interrupt is enabled, the interrupt can be triggered to process V exceeding the threshold in advance.
Page 107 Figure 11 PVD Threshold Oscillogram PVD threshold Hysteresis voltage PVD output Power consumption control Reduce the power consumption in low-power mode There are three low-power modes: sleep mode, stop mode and standby mode. The power consumption is reduced by closing the core and clock source and setting the voltage regulator.
Page 108 Effect on Effect on Voltage Mode Description Entry mode Wake-up mode 1.3V area area regulator clock clock and all is turned peripherals off and it including the has no core peripheral Call WFE effect on Wake-up event Open None are still instruction other working...
Page 109 Characteristics Description If the system is woken up by interrupt, it will first enter the interrupt, then exit the After wake-up interrupt, and then execute the program after WFI instruction. If the system is woken up by event, it will directly execute the program after WFE instruction. Stop mode The characteristics of stop mode are shown in the table below: Table 40 Characteristics of Stop Mode...
Page 110: Register Address Mapping
RTC multiplexing function is waken up from low-power mode RTC multiplexing functions include RTC alarm, RTC wake-up event, RTC tamper event and RTC timestamp event. These functions can wake up MCU from stop mode or standby mode, and RTC provides programmable time base to wake up the devices regularly from stop or standby mode.
Page 111 Field Name Description 101：2.7V 110：2.8V 111：2.9V Note: See "Datasheet" for detailed instructions Backup Domain Write Access Enable Backup area refers to RTC and backup register; write access is disabled after reset, and is allowed after writing 1. BPWEN 0: Write is disabed 1: Write is enabled Flash power-down in Stop mode FPDSM...
Page 112 Field Name Description Backup regulator ready Flag This bit is set to 1 by hardware, indicating whether the backup regulator is ready. BKPRFLG 0: Not ready 1. Ready Reserved WKUP Pin Configure When WKUP is used as a normal I/O, the event on WKUP pin cannot wake up the CPU in standby mode;...
Page 113: Nested Vector Interrupt Controller (Nvic)
Nested vector interrupt controller (NVIC) Full name and abbreviation description of terms Table 43 Full name and abbreviation description of terms Full name in English English abbreviation Non Maskable Interrupt Introduction The Cortex-M4 core in the product integrates nested vectored interrupt controller (NVIC), which is closely coupled with the core, and can handle exceptions and interrupts and power management control efficiently and with low delay.
Page 114 Exception type Vector No. Priority Vector address Description System service called by SWI SVCall Can be set 0x0000_002C instruction Debug Monitor Can be set 0x0000_0030 Debug monitor 0x0000_0034 Reserved PendSV Can be set 0x0000_0038 Pending system service request SysTick Can be set 0x0000_003C System tick timer WWDT...
Page 115 Exception type Vector No. Priority Vector address Description CAN1_RX1 Can be set 0x0000_0094 CAN1 receiving 1 interrupt CAN1_SCE Can be set 0x0000_0098 CAN1 SCE interrupt EINT9_5 Can be set 0x0000_009C EINT line [9:5] interrupt TMR1 braking interrupt/TMR9 TMR1_BRK_TMR9 Can be set 0x0000_00A0 global interrupt TMR1 update interrupt/TMR10...
Page 116 Exception type Vector No. Priority Vector address Description SDIO Can be set 0x0000_0104 SDIO interrupt TMR5 Can be set 0x0000_0108 TMR5 interrupt SPI3 Can be set 0x0000_010C SPI3 interrupt UART4 Can be set 0x0000_0110 UART4 interrupt UART5 Can be set 0x0000_0114 UART5 interrupt TMR6 interrupt/DAC1 and DAC2...
Page 117 Exception type Vector No. Priority Vector address Description 0x0000_017C Reserved Can be set 0x0000_0180 RNG global interrupt Can be set 0x0000_0184 FPU global interrupt Table 45 APM32F417xExG Interrupt and Exception Vector Table Exception type Vector No. Priority Vector address Description 0x0000_0000 Reserved Reset...
Page 118 Exception type Vector No. Priority Vector address Description DMA1 data stream 0 global DMA1_STR0 Can be set 0x0000_006C interrupt DMA1 data stream 1 global DMA1_STR1 Can be set 0x0000_0070 interrupt DMA1 data stream 2 global DMA1_STR2 Can be set 0x0000_0074 interrupt DMA1 data stream 3 global DMA1_STR3...
Page 119 Exception type Vector No. Priority Vector address Description USART2 Can be set 0x0000_00D8 USART2 interrupt USART3 Can be set 0x0000_00DC USART3 interrupt EINT15_10 Can be set 0x0000_00E0 EINT line [15:10] interrupt RTC_Alarm Can be set 0x0000_00E4 RTC alarm interrupt OTG_FS wake-up interrupt OTG_FS WKUP Can be set 0x0000_00E8...
Page 120 Exception type Vector No. Priority Vector address Description OTG_FS Can be set 0x0000_014C OTG_FS global interrupt DMA2_STR5 Can be set 0x0000_0150 DMA2 data stream 5 interrupt DMA2_STR6 Can be set 0x0000_0154 DMA2 data stream 6 interrupt DMA2_STR7 Can be set 0x0000_0158 DMA2 data stream 7 interrupt USART6...
Page 121: External Interrupt/Event Controller (Eint)
External Interrupt/Event Controller (EINT) Introduction The interrupts/events contain internal interrupt/event and external interrupt/event. In this manual, external interrupt refers to the interrupt/event caused by I/O pin input signal, which is EINTx in interrupt vector table; other interrupts are internal interrupts/events. The events can be divided into hardware events and software events.
Page 122 Table 46 "External Interrupt and Event" Classification and Difference Points Name Trigger source Configuration and execution process (1) Set the trigger mode, allow the interrupt request, and enable corresponding peripheral interrupt line (enable in NVIC); External (2) When an edge consistent with the configuration is generated hardware External signal on the external interrupt line, an interrupt request will be generated,...
Page 123  Generate an interrupt to wake up the core; when the core recovers from WFE, it is required to clear the pending bit of corresponding peripheral interrupt and the pending bit of peripheral NVIC interrupt channel (clear the pending register in the NVIC interrupt) Wake up through EINT line events (external hardware event) ...
Page 124: Register Address Mapping
External Interrupt and Event Channel Name External Interrupt and Event Line No. OTG_FS wake-up event EINT 18 Ethernet wake-up event EINT 19 OTG_HS1 wake-up event EINT 20 RTC tamper and timestamp event EINT 21 RTC wake-up event EINT 22 Reserved EINT 23 Reserved EINT 24...
Page 125 Event mask register (EINT_EMASK) Offset address: 0x04 Reset value: 0x0000 0000 Field Name Description Event Request Mask on Line x (x=0~22) 22:0 EMASKx 0: Mask 1: Open 31:23 Reserved Enable the rising edge trigger register (EINT_RTEN) Offset address: 0x08 Reset value: 0x0000 0000 Field Name Description...
Page 126 Field Name Description Software Interrupt Event on Line x (x=0~22) This bit can be set to 1 by software, and be cleared by writing 1 to the corresponding bit of EINT_IPEND. When this bit is 0, the pending bit of EINT_IPEND can be set by writing 22:0 SWINTEx 1.
Page 127: Direct Memory Access (Dma)
Direct memory access (DMA) Introduction DMA (Direct Memory Access) can realize high-speed data transmission between peripheral devices and memory or between memory and memory without CPU intervention, thus saving CPU resources for other operations. The product has two DMA controllers, with 16 data streams. Each data stream corresponds to 8 channels, but each data stream can only use 1 channel at the same time.
Page 128 Two DMA have 16 data streams in total. Each data stream is connected with different peripheral channels, and each data stream has five event flags (DMA half transmission, DMA transmission completion, DMA transmission error, DMA FIFO error, and direct mode error). The logic of the five event flags may become a separate interrupt request, and they all support software trigger.
Page 129 Table 49 DMA1 Request Mapping Table Peripheral Data stream 0 Data stream 1 Data stream 2 Data stream 3 Data stream 4 Data stream 5 Data stream 6 Data stream 7 request Channel 0 SPI3_RX SPI3_RX SPI2_RX SPI2_TX SPI3_TX SPI3_TX Channel 1 I2C1_RX TMR7_UP...
Page 130 Table 50 DMA2 Request Mapping Table Peripheral Data stream 0 Data stream 1 Data stream 2 Data stream 3 Data stream 4 Data stream 5 Data stream 6 Data stream 7 request TMR8_CH1 TMR1_CH1 Channel 0 ADC1 TMR8_CH2 ADC1 TMR1_CH2 TMR8_CH3 TMR1_CH3 Channel 1...
Page 131 Arbitrator When multiple DMA channel requests occur, an arbiter is needed to manage the response sequence. Management is divided into two stages: the first stage is software stage, which is divided into the highest, high, medium and low priority; the second stage is hardware stage, and under the condition of the same software priority, the lower the data stream number is, the higher the priority is.
Page 132 Increment mode The increment mode of peripheral and memory is controlled through PERIM and MEMIM bits of DMA_SCFG register. When both bits are set to 1, it is configured as the increment mode and the increment is the value of PERSIZECFG and MENSIZECFG bits of DMA_SCFG register.
Page 133 FIFO MENSIZECFG MBCFG=01 MBCFG=10 MBCFG=11 threshold One-time burst of 4 Full ticks Circular mode The circular mode is used to process the circular buffer area and continuous data stream. The circular mode will automatically configure the number of data items as the initial value after the transmission ends, and continue the data transmission.
Page 134: Dma Register Address Mapping
Interrupt Each data stream has five types of interrupt events: half transmission, transmission completion, transmission error, FIFO error and direct mode error. Table 52 DMA Interrupt Request Interrupt event Event flag bit Enable interrupt bit Half transmission HTXIFLGx HTXIEN Transmission completed TXCIFLGx TXCIEN Transmission error...
Page 135 Field Name Description Stream x FIFO Error Interrupt Flag (x=0…3) These bits are set to 1 by hardware; write 1 and set to 0 by software on the corresponding bit of DMA_LIFCLR register. 22、16、6、0 FEIFLGx 0: No FIFO error event 1: FIFO error event occurs 23、17、7、1 Reserved...
Page 136 Field Name Description Stream x Transfer Error Interrupt Flag (x=4…7) These bits are set to 1 by hardware; write 1 and set to 0 by software on the corresponding bit of DMA_HIFCLR register. 25、19、9、3 TXEIFLGx 0: No transmission error 1: Transmission error is generated Stream x Half Transfer Interrupt Flag (x=4…7) These bits are set to 1 by hardware;...
Page 137 Reset value: 0x0000 0000 Field Name Description Stream x Clear FIFO Error Interrupt Flag (x=4…7) 0: Invalid 22、16、6、0 CFEIFLGx 1: The corresponding FEIFLGx flag in DMA_HINTSTS register is cleared to 0 23、17、7、1 Reserved Stream x Clear Direct Mode Error Interrupt Flag (x=4…7) 0: Invalid 24、18、8、2 CDMEIFLGx...
Page 138 Field Name Description 1: Enable Transfer Complete Interrupt Enable TXCIEN 0: Disable 1: Enable Peripheral Flow Controller 0: DMA is stream controller 1: The peripheral is stream controller PERFC This bit can be written only when the EN bit is 0; when the memory-to-memory mode selected, this...
Page 139 Field Name Description 10: Word (32 bits) 11: Reserved These bits can be written only when EN bit is 0. In direct mode, when EN bit is 1, MEMSIZECFG bit will be forced to be of the same value as that of PERSIZECFG bit. Peripheral increment offset size 0: The offset used to calculate the peripheral address is related to PERSIZECFG...
Page 140 Field Name Description 001: Select Channel 1 010: Select Channel 2 011: Select Channel 3 100: Select Channel 4 101: Select Channel 5 110: Select Channel 6 111: Select Channel 7 31:28 Reserved DMA data stream x data item number register (DMA_NDATA) (x=0…7) Offset address: 0x14+0x18×...
Page 141 Field Name Description  Enable the data stream and set CTARG bit of DMA_SCFG register to 1 DMA data stream x memory 1 address register (DMA_M1ADDR) (x=0…7) Offset address: 0x20+0x18× (data stream number) Reset value: 0x0000 0000 Field Name Description Memory 1 Address Base address of memory 1 of read/write data.
Page 142 Field Name Description FIFO Error Interrupt Enable FEIEN 0: Disable 1: Enable 31:8 Reserved www.geehy.com Page 141...
Page 143: Debug Mcu (Dbgmcu)
Debug MCU (DBGMCU) Full name and abbreviation description of terms Table 54 Full name and abbreviation description of terms Full name in English English abbreviation Frame Clock FCLK Serial Wire/JTAG Debug Port SWJ-DP Introduction APM32F407 MCU series uses Arm ® Cortex ®...
Page 144: Functional Description
® ® Figure 12 APM32F4xx Level and Arm Cortex -M4 Level Debugging Block Diagram ® ® Cortex -M4 chip ® ® Cortex core system AHB-AP Debug SW-DR or SWJ-DP Address host Control ® DAP on Arm AHB bus matrix ® Cortex Data Memory system...
Page 145: Register Address Mapping
ID code MCU device ID code APM32F MCU series incudes a MCU ID code. It can be accessed with JTAG or SW debug interface or user code. Boundary scan TAP JTAG ID code The boundary scan TAP of APM32F MCU series integrates JTAG ID code. For APM32F405/415xG、APM32F407/417xExG series products, its JTAG ID code is 0x06413B47 ®...
Page 146 Field Name Description Wafer Version Recognition 31:16 This domain identifies wafer information Debug MCU configuration register (DBGMCU_CFG) This register can configure MCU in debug mode. It includes the counter supporting timer and watchdog, low-power mode, CAN communication and assignment tracking pin. Address: 0xE004 2004 Only support 32-bit access Reset value: 0x0000 0000 (not affected by system reset, only power-on reset)
Page 147 Address: 0xE004 2008 Reset value: 0x0000 (unaffected by system reset) Field Name Description Configure TMR2 Work Status When Core is in Halted Whether TMR2 timer continues to work when the core stops work TMR2_STS 0: Continue to work 1: Stop working Configure Timer3 Work Status When Core is in Halted Whether TMR3 counter continues to work when the core stops work...
Page 148 Field Name Description Reserved Configure RTC Work Status When Core Is in Halted Whether RTC counter continues to work when the core stops work RTC_STS 0: Continue to work 1: Stop working Configure Window Watchdog Work Status When Core Is in Halted Whether WWDT counter continues to work when the core stops work WWDT_STS...
Page 149 Debug MCU APB2 freeze register (DBGMCU_APB2F) This register is used to configure MCU during debugging. Involve some APB peripherals:  Freeze the timer counter This register is reset asynchronously by POR (instead of system reset) and can be written by the debugger through system reset. Only support 32-bit access Address: 0xE004 200C Reset value: 0x0000 (unaffected by system reset)
Page 150: General-Purpose Input/Output Pin (Gpio)
General-Purpose Input/Output Pin (GPIO) Full name and abbreviation description of terms Table 57 Full name and abbreviation description of terms Full name in English English abbreviation P-channel Metal Oxide Semiconductor P-MOS N-channel Metal Oxide Semiconductor N-MOS Main characteristics GPIO port can configure the following functions through 32-bit configuration register (GPIOx_CFGLOW/GPIOx_CFGHIG) and two 32-bit data registers GPIOx_IDATA/GPIOx_ODATA): Input mode...
Page 151: Structure Block Diagram
Structure block diagram Figure 13 5V GPIO-compatible Structure Block Diagram Push-pull, open- Write Bit set/clear drain, disable Output data register P-MOS Read-write register Output From on-chip control Multiplexing function output peripheral DD_FT N-MOS Analog input To on-chip I/O pin peripheral Multiplexing function input Read Input data...
Page 152 In (pull-up, pull-down, floating) input mode  Schmitt trigger is opened  Disable output buffer  Connect weak pull-up and pull-down resistors according to different input configurations  The input data register GPIOx_IDATA captures the data on I/O pin in each AHB1 clock cycle ...
Page 153  Push-pull mode: Double MOS transistor works by turns and the output data register can control the high and low level of I/O output Read the finally written value through the output data register GPIOx_ODATA  Open-drain mode: Only N-MOS works, and the output data register can control I/O output high resistance state or low level Read the actual I/O state through the input data register GPIOx_IDATA...
Page 154 Figure 16 I/O Structure in Multiplexing Mode Push-pull, open- drain, disable P-MOS Multiplexing function output Output control N-MOS I/O pin Multiplexing function input TTL Schottky trigger External interrupt/wake-up line All GPIO ports have external interrupt function. If you want to use external interrupt line, the port must be configured as input mode.
Page 155: Register Address Mapping
Register address mapping Table 58 GPIO Register Address Mapping Register name Description Offset address GPIOx_MODE Port mode register 0x00 GPIOx_OMODE Port output mode register 0x04 GPIOx_OSSEL Port output speed register 0x08 GPIOx_PUPD Port pull-up/pull-down register 0x0C GPIOx_IDATA Port bit input data register 0x10 GPIOx_ODATA Port bit output clear register...
Page 156 Port output speed register (GPIOx_OSSEL) (x=A…I) Offset address: 0x08 Reset value: 0x0C00 0000 (Port A) 0x0000 00C0 (Port B) 0x0000 000 (other ports) Field Name Description PortxPin y Output Speed Select (y=0…15) x0: Low speed 2y+1:2y OSSELy[1:0] 01: Medium speed 11: High speed The speed of configuration I/O port is written by software GPIO port pull-up/pull-down register (GPIOx_PUPD) (x=A…I)
Page 157 GPIO port set/reset register (GPIOx_BSC) (x=A…I) Offset address: 0x18 Reset value: 0x0000 0000 Field Name Description PortxPin y Set bit (y=0…15) These bits can only perform write operation, and the value of 0x0000 is returned when reading these bits. 15:0 These bits are used to affect the corresponding ODATAy bits 0: No effect 1: Set the corresponding ODATAy bit...
Page 158 Field Name Description The value of LOCKy cannot be changed during the write sequence of the operation lock key. Any error in the write sequence of operation lock key will abort the lock. After the first lock sequence on any bit of the port, any read access on the LOCKKEY bit will return "1"...
Page 159 Field Name Description 0011：AF3 0100：AF4 0101：AF5 0110：AF6 0111：AF7 1000: Reserved 1001: Reserved 1010: Reserved 1011: Reserved 1100: Reserved 1101: Reserved 1111: Reserved 1110: Reserved www.geehy.com Page 158...
Page 160: Timer Overview
Timer overview Full name and abbreviation description of terms Table 59 Full name and abbreviation description of terms Full name in English English abbreviation Timer Update Request Event Capture Compare Length Timer category and main difference In this series of products, there are three types of timers: advanced timer, general-purpose timer and basic timer (watchdog timer is described in other chapters).
Page 161 Specific Advanced General-purpose Basic Item General-purpose timer content/Category timer timer timer Down Down Down Count mode Down Center Center Center Center alignment alignment alignment alignment Input channel Capture/Compare channel Channel Output channel Complementary output channel General DMA request PWM mode None Single-pulse None...
Page 162 Name Description TIF_ED Timer input filter edge detection CK_PSC Prescaler clock CK_CNT Counter clock Prescaler Counter AUTORLD Autoload register TIx，TI1 Timer input TIxF，TI1F， Timer input filter TI1_ED Timer input edge detection TIxFPx，TI1FP1 Timer input filter polarity ICx，IC1 Input capture ICxPS，IC1PS Input capture prescaler Trigger capture Braking signal...
Page 163: Advanced Timers (Tmr1/8)
Advanced Timers (TMR1/8) Introduction The advanced timer takes the time base unit as the core, and has the functions of input capture, output compare and braking input, including a 16-bit automatic loading counter. Compared with other timers, the advanced timer supports complementary output, repeat count and programmable dead-time insertion function, and is more suitable for motor control.
Page 164: Structure Block Diagram
 Trigger event (counter start, stop, internal/external trigger)  Capture/Compare event  Braking signal input event Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes Structure block diagram Figure 17 Advanced Timer Structure Block Diagram Clock failure event TMRx_BKIN Polarity selection TMRx_CH4 TIxFP3...
Page 165 External clock mode 1 The trigger signal generated from the input channel TI1/2/3/4 of the timer after polarity selection and filtering is connected to the slave mode controller to control the work of the counter. Besides, the pulse signal generated by the input of Channel 1 after double-edge detection of the rising edge and the falling edge is logically equal or the future signal is TI1F_ED signal, namely double-edge signal of TIF_ED.
Page 166 (TMRx_AUTORLD) is written in advance. If a repeat counter is used, an update event will be generated when the number of count-up repetitions reaches the number in the repeat counter register plus one time (TMRx_REPCNT+1). Otherwise, an update event will be generated every time the counter overruns. At this time, the repeat count shadow register, the auto reload shadow register and the prescaler buffer will be updated.
Page 167 (TMRx_AUTORLD) is written in advance. If a repeat counter is used, an update event will be generated when the number of count-down repetitions reaches the number in the repeat counter register plus one time (TMRx_REPCNT+1). Otherwise, an update event will be generated every time the counter underruns. At this time, the repeat count shadow register, the auto reload shadow register and the prescaler buffer will be updated.
Page 168 Figure 20 Timing Diagram when Division Factor is 1 or 2 in Center-aligned Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter underrun Counter overrun Update event PSC=2 CK_CNT 0000 0002 0003 0003 0002 0001 0001 Counter register Counter overrun Update event Repeat counter REPCNT There is no repeat counter REPCNT in the basic/general-purpose timer, which means that when the overrun event or underrun event occurs in the...
Page 169 Figure 21 Timing Diagram when Setting REPCNT=2 in Count-up Mode CK_CNT Counter overrun Update event Prescaler PSC The prescaler is 16 bits and programmable, and it can divide the clock frequency of the counter to any value between 1 and 65536 (controlled by TMRx_PSC register), and after frequency division, the clock will drive the counter CNT to count.
Page 170 In capture mode, the timing, frequency, period and duty cycle of a waveform can be measured. In the input capture mode, the edge selection is set to rising edge detection. When the rising edge appears on the capture channel, the first capture occurs, at this time, the value of the counter CNT will be latched in the capture register CCx;...
Page 171 Figure 22 PWM1 Count-up Mode Timing Diagram AUTORLD OCXREF Figure 23 PWM1 Count-down Mode Timing Diagram AUTORLD OCXREF Figure 24 PWM1 Center-aligned Mode Timing Diagram AUTORLD OCXREF In PWM mode 2, if the value of the counter CNT is less than that of the compare register CCx, the output level will be invalid;...
Page 172 Figure 25 PWM2 Count-up Mode Timing Diagram AUTORLD OCxREF Figure 26 PWM2 Count-down Mode Timing Diagram AUTORLD OCxREF Figure 27 PWM2 Center-aligned Mode Timing Diagram AUTORLD OCxREF PWM input mode PWM input mode is a particular case of input capture. In PWM input mode, as only TI1FP1 and TI1FP2 are connected to the slave mode controller, input can be performed only through the channels TMRx_CH1 and TMRx_CH2, which need to occupy the capure registers of CH1 and CH2.
Page 173 signal will be divided into two channels, one can measure the cycle and the other can measure the duty cycle. In the configuration, it is only required to set the polarity of one channel, and the other will be automatically configured with the opposite polarity.
Page 174 Figure 29 Single-pulse Mode Timing Diagram AUTORLD DELAY PULSE OCxREF Impact of the register on output waveform The following registers will affect the level of the timer output waveform. For details, please refer to "Register Functional Description". CCxEN and CCxNEN bits in TMRx_CCEN register ...
Page 175  CCxPOL=0 and CCxNPOL=0: Output polarity, high level is valid CCxPOL=1 and CCxNPOL=1: Output polarity, the low level is valid The following figure lists the register structure relationships that affect the output waveform Figure 30 Register Structural Relationship Affecting Output Waveform CCxEN/CCxNEN=1 Normal output RMOS=1...
Page 176 Figure 31 Braking Event Timing Diagram Brake OCxREF CCxPOL=0,OCxOIS=0 CCxPOL=0,OCxOIS=1 CCxPOL=1,OCxOIS=0 CCxPOL=1,OCxOIS=1 Complementary output and dead-time insertion Complementary output is particular output of advanced timer, and the advanced timer has three groups of complementary output channels. The insertion dead time is used to generate complementary output signals to ensure that the two- way complementary signals of channels will not be valid at the same time.
Page 177 Forced output mode In the forced output mode, the comparison result is ignored, and the corresponding level is directly output according to the configuration instruction.  CCxSEL=00 for TMRx_CCMx register, set CCx channel as output  OCxMOD=100/101 for TMRx_CCMx register, set to force OCxREF signal to invalid/valid state In this mode, the corresponding interrupt and DMA request will still be generated.
Page 178 Count in both TI1 Effective edge Count only in TI1 Count only in TI2 and TI2 Falling Count Count Count up Count up edge down down The external incremental encoder can be directly connected with MCU, not needing external interface logic, so the comparator is used to convert the differential output of the encoder to digital signal to increase the immunity from noise interference.
Page 179 Figure 34 Example of Encoder Interface Mode of IC1FP1 Reversed Phase Counter For example, when TI1 is at low level, and the rising edge of TI2 jumps, the counter will count down. Slave mode TMRx timer can synchronize external trigger ...
Page 180 source for the counter of the slave mode timer. Figure 35 Timer 1 Master/Slave Mode Example Master Slave timer timer TRGO TMR5 ITR0 TS=000 Master mode controller TRGO TMR2 ITR1 TS=001 Master mode controller TMR1 Slave mode controller TRGO ITR2 TMR3 TS=010 Master mode controller...
Page 181: Register Address Mapping
Figure 36 OCxREF Timing Diagram ETRF OCxREF OCxCEN=0 Set TMRx to PWM mode, close the external trigger prescaler, and disable the external trigger mode 2; when ETRF input is high, set OCxCEN=1, and the output OCxREF signal is shown in the figure below. Figure 37 OCxREF Timing Diagram ETRF OCxREF...
Page 182: Register Functional Description
Register name Description Offset address TMRx_CNT Counter register 0x24 TMRx_PSC Prescaler register 0x28 TMRx_AUTORLD Auto reload register 0x2C TMRx_REPCNT Repeat count register 0x30 TMRx_CC1 Channel 1 capture/compare register 0x34 TMRx_CC2 Channel 2 capture/compare register 0x38 TMRx_CC3 Channel 3 capure/compare register 0x3C TMRx_CC4 Channel 4 capture/compare register...
Page 183 Field Name Description Single Pulse Mode Enable When an update event is generated, the output level of the channel can be changed; in this mode, the CNTEN bit will be cleared, the counter will SPMEN be stopped, and the output level of the channel will not be changed. 0: Disable 1: Enable Counter Direction...
Page 184 Field Name Description affect the timer setting; When preloading is enabled, it is only updated after COMG is set, so as to affect the setting of timer; this bit only works on channels with complementary output. 0: Disable 1: Enable Reserved Capture/compare Control Update Select Only when the capture/compare preload is enabled (CCPEN=1), it...
Page 185 Field Name Description OC2NOIS Configure OC2N output idle state. Refer to OC1NOIS bit OC3OIS Configure OC3 output idle state. Refer to OC1OIS bit OC3NOIS Configure OC3N output idle state. Refer to OC1NOIS bit OC4OIS Configure OC4 output idle state. Refer to OC1OIS bit Reserved Slave mode control register (TMRx_SMCTRL) Offset address: 0x08...
Page 186 Field Name Description Master/slave Mode Enable MSMEN 0: Invalid 1: Enable the master/slave mode External Trigger Filter Configure 0000: Filter disabled, sampling by f 0001: DIV=1，N=2 0010: DIV=1，N=4 0011: DIV=1，N=8 0100: DIV=2，N=6 0101: DIV=2，N=8 0110: DIV=4，N=6 0111: DIV=4，N=8 11:8 ETFCFG 1000: DIV=8，N=6 1001:...
Page 187 Table 65 TMRx Internal Trigger Connection ITR1（TS=000） ITR1（TS=001） ITR2（TS=010） ITR3（TS=011） Slave timer TMR1 TMR5 TMR2 TMR3 TMR4 TMR8 TMR1 TMR2 TMR4 TMR5 DMA/Interrupt enable register (TMRx_DIEN) Offset address: 0x0C Reset value: 0x0000 Field Name Description Update interrupt Enable UIEN 0: Disable 1: Enable Capture/Compare Channel1 Interrupt Enable CC1IEN...
Page 188 Field Name Description Capture/Compare Channel3 DMA Request Enable CC3DEN 0: Disable 1: Enable Capture/Compare Channel4 DMA Request Enable CC4DEN 0: Disable 1: Enable COM DMA Request Enable COMDEN 0: Disable 1: Enable Trigger DMA Request Enable TRGDEN 0: Disable 1: Enable Reserved State register (TMRx_STS) Offset address: 0x10...
Page 189 Field Name Description Capture/Compare Channel3 Interrupt Flag CC3IFLG RC_W0 Refer to STS_CC1IFLG Captuer/Compare Channel4 Interrupt Flag CC4IFLG RC_W0 Refer to STS_CC1IFLG COM Event Interrupt Generate Flag 0: COM event does not occur COMIFLG RC_W0 1: COM interrupt waits for response After COM event is generated, this bit is set to 1 by hardware and cleared by software.
Page 190 Field Name Description Capture/Compare Channel1 Event Generation 0: Invalid 1: Capture/Compare event is generated This bit is set to 1 by software and cleared automatically by hardware. If Channel 1 is in output mode: When CC1IFLG=1, if CC1IEN and CC1DEN bits are set, the CC1EG corresponding interrupt and DMA request will be generated.
Page 191 Field Name Description Capture/Compare Channel 1 Selection This bit defines the input/output direction and the selected input pin. 00: CC1 channel is output 01: CC1 channel is input, and IC1 is mapped on TI1 CC1SEL 10: CC1 channel is input, and IC1 is mapped on TI2 11: CC1 channel is input, and IC1 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is closed...
Page 192 Field Name Description Capture/Compare Channel2 Select This bit defines the input/output direction and the selected input pin. 00: CC2 channel is output 01: CC2 channel is input, and IC2 is mapped on TI2 CC2SEL 10: CC2 channel is input, and IC2 is mapped on TI1 11: CC2 channel is input, and IC2 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is closed...
Page 193 Field Name Description 1111: DIV=32，N=8 Sampling frequency=timer clock frequency/DIV; the filter length=N, indicating that a jump is generated by every N events. Capture/Compare Channel 2 Select 00: CC2 channel is output 01: CC2 channel is input, and IC2 is mapped on TI1 10: CC2 channel is input, and IC2 is mapped on TI2 CC2SEL 11: CC2 channel is input, and IC2 is mapped on TRC, and only works in...
Page 194 Field Name Description 11: CC4 channel is input, and IC4 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is closed (TMRx_CCEN register CC4EN=0). OC4FEN Output Compare Channel4 Preload Enable OC4PEN Output Compare Channel4 Buffer Enable 14:12...
Page 195 Field Name Description When the capture/compare channel 1 is configured as input: This bit determines whether the value CNT of the counter can be captured and enter TMRx_CC1 register 0: Capture is disabled 1: Capture is enabled Capture/Compare Channel1 Output Polarity Configure When CC1 channel is configured as output: 0: OC1 high level is valid 1: OC1 low level is valid...
Page 196 Counter register (TMRx_CNT) Offset address: 0x24 Reset value: 0x0000 Field Name Description 15:0 Counter Value Prescaler register (TMRx_PSC) Offset address: 0x28 Reset value: 0x0000 Field Name Description Prescaler Value 15:0 Clock frequency of counter (CK_CNT)＝f /(PSC+1) CK_PSC Auto reload register (TMRx_AUTORLD) Offset address: 0x2C Reset value: 0xFFFF Field...
Page 197 Field Name Description If the output compare preload is enabled (OC1PEN=1 for TMRx_CCM1 register), the written value will affect the output compare result when an update event is generated. Channel 2 capture/compare register (TMRx_CC2) Offset address: 0x38 Reset value: 0x0000 Field Name Description...
Page 198 Field Name Description Note: Once LOCK level (LOCKCFG bit in TMRx_BDT register) is set to 1, 2 or 3, these bits cannot be modified. Lock Write Protection Mode Configuration 00: Without Lock write protection level; the register can be written directly 01: Lock write protection level 1 It cannot be written to DTS, BRKEN, BRKPOL and AOEN bits of TMRx_BDT, and OCxOIS and OCxNOIS bits of TMRx_CTRL2 register.
Page 199 Field Name Description 1: When CCxEN and CCxNEN bits of the TMRx_CCEN register are set, turn on OCx and OCxN output When the brake input is valid, it is cleared by hardware asynchronously. Note: Setting to 1 by software or setting to 1 automatically depends on AOEN bit of the TMRx_BDT register.
Page 200 DMA address register of continuous mode (TMRx_DMADDR) Offset address: 0x4C Reset value: 0x0000 Field Name Description DMA Register for Burst Transfer Read or write operation access of TMRx_DMADDR register may lead to access operation of the register in the following address: TMRx_CTRL1 address + (DBADDR+DMA index) ×4 Wherein: 15:0...
Page 201: General-Purpose Timer (Tmr2/3/4/5)
General-purpose timer (TMR2/3/4/5) Introduction The general-purpose timer takes the time base unit as the core, and has the functions of input capture and output compare, and can be used to measure the pulse width, frequency and duty cycle, and generate the output waveform. It includes a 16-bit or 32-bit auto reload counter (realize count-up, count-down and center-aligned count).
Page 202: Structure Block Diagram
Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes Structure block diagram Figure 38 General-purpose Timer Structure Block Diagram TIxFP3 TMRx_CH4 Channel x Output ICxPS OCxREF Prescaler Filter TMRx_CHx capture/compare TIxFP4 control edge register detector TMRx_CH3 TMRx_CH2 TIxFP1 Channel x Filter ICxPS OCxREF...
Page 203 is logically equal or the future signal is TI1F_ED signal, namely double-edge signal of TIF_ED. Specially the PWM input can only be input by TI1/2. External clock mode 2 After polarity selection, frequency division and filtering, the signal from external trigger interface (ETR) is connected to slave mode controller through trigger input selector to control the work of counter.
Page 204 Figure 39 Timing Diagram when Division Factor is 1 or 2 in Count-up Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter overrun Update event PSC=2 CK_CNT 0025 0000 0002 0003 0024 0001 0026 Counter register Counter overrun Update event Count-down mode Set to the count-down mode by CNTDIR bit of configuration control register (TMRx_CTRL1).
Page 205 Figure 40 Timing Diagram when Division Factor is 1 or 2 in Count-down Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter overrun Update event PSC=2 CK_CNT 0024 0023 0002 0001 0026 0025 0000 Counter register Counter overrun Update event Center-aligned mode Set to the center-aligned mode by CNTDIR bit of configuration control register (TMRx_CTRL1).
Page 206 Figure 41 Timing Diagram when Division Factor is 1 or 2 in Center-aligned Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter underrun Counter overrun Update event PSC=2 CK_CNT 0003 0003 0002 0000 0001 0002 0001 Counter register Counter overrun Update event Prescaler PSC The prescaler is 16 bits and programmable, and it can divide the clock frequency of the counter to any value between 1 and 65536 (controlled by...
Page 207 signal will pass through the prescaler, which is used to set how many events to capture at a time. Input capture application Input capture is used to capture external events, and can give the time flag to indicate the occurrence time of the event and measure the pulse jump edge events (measure the frequency or pulse width), for example, if the selected edge appears on the input pin, the TMRx_CCx register will capture the current value of the counter and the CCxIFLG bit of the state register TMRx_STS will be...
Page 208 is determined by the value of the auto reload AUTORLD. PWM output mode contains PWM mode 1 and PWM mode 2; PWM mode 1 and PWM mode 2 are divided into count-up, count-down and edge alignment counting; in PWM mode 1, if the value of the counter CNT is less than the value of the compare register CCx, the output level will be valid;...
Page 209 In PWM mode 2, if the value of the counter CNT is less than that of the compare register CCx, the output level will be invalid; otherwise, it will be valid. Set the timing diagram in PWM mode 2 when CCx=5, AUTORLD=7 Figure 45 PWM2 Count-up Mode Timing Diagram AUTORLD OCxREF...
Page 210 mode controller, input can be performed only through the channels TMRx_CH1 and TMRx_CH2, which need to occupy the capure registers of CH1 and CH2. In PWM input mode, the PWM signal enters from TMRx_CH1, and the signal will be divided into two channels, one can measure the period, and the other can measure the duty cycle.
Page 211 Figure 49 Timing Diagram in Single-pulse Mode AUTORLD DELAY PULSE OCxREF Forced output mode In the forced output mode, the comparison result is ignored, and the corresponding level is directly output according to the configuration instruction.  CCxSEL=00 for TMRx_CCMx register, set CCx channel as output ...
Page 212  Set CNTDIR of control register TMRx_CTRL1 to be read-only (CNTDIR will be re-calculated due to jumping of any input end) The change mechanism of counter count direction is shown in the figure below: Table 66 Relationship between Count Direction and Encoder Count in both TI1 Effective edge Count only in TI1...
Page 213 counter will count up. Figure 51 Example of Encoder Interface Mode of IC1FP1 Reversed Phase Counter For example, when TI1 is at low level, and the rising edge of TI2 jumps, the counter will count down. Slave mode TMRx timer can synchronize external trigger ...
Page 214 Interrupt and DMA request The timer can generate an interrupt when an event occurs during operation  Update event (counter overrun/underrun, counter initialization)  Trigger event (counter start, stop, internal/external trigger)  Capture/Compare event Some internal interrupt events can generate DMA requests, and special interfaces can enable or disable DMA requests.
Page 215: Register Address Mapping
Register address mapping In the following table, all registers of the general-purpose timer are mapped to a 16-bit addressable (address) space. Table 67 General-purpose Timer Register Address Mapping Register name Description Offset address TMRx_CTRL1 Control register 1 0x00 TMRx_CTRL2 Control register 2 0x04 TMRx_SMCTRL Slave mode control register...
Page 216 Field Name Description When the timer is configured as external clock, gated mode and encoder mode, it is required to write 1 to the bit by software to start regular work; when it is configured as the trigger mode, it can be written to 1 by hardware.
Page 217 Field Name Description 0: Disable 1: Enable Clock Divide Factor For the configuration of dead time and digital filter, CK_INT provides the clock, and the dead time and the clock of the digital filter can be adjusted by setting this bit. CLKDIV 00：t CK_INT...
Page 218 Field Name Description 000: Disable the slave mode, the timer can be used as master mode timer to affect the work of slave mode timer; if CTRL1_CNTEN=1, the prescaler is directly driven by the internal clock. 001: Encoder mode 1; according to the level of TI1FP1, the counter counts at the edge of TI2FP2.
Page 219 Field Name Description 1011: DIV=16，N=6 1100: DIV=16，N=8 1101: DIV=32，N=5 1110: DIV=32，N=6 1111: DIV=32，N=8 Sampling frequency=timer clock frequency/DIV; the filter length=N, and a jump is generated by every N events. External Trigger Prescaler Configure The ETR (external trigger input) signal becomes ETRP after frequency division.
Page 220 Field Name Description Capture/Compare Channel1 Interrupt Enable CC1IEN 0: Disable 1: Enable Capture/Compare Channel2 Interrupt Enable CC2IEN 0: Disable 1: Enable Capture/Compare Channel3 Interrupt Enable CC3IEN 0: Disable 1: Enable Capture/Compare Channel4 Interrupt Enable CC4IEN 0: Disable 1: Enable Reserved Trigger interrupt Enable TRGIEN 0: Disable...
Page 221 Field Name Description Update Event Interrupt Generate Flag 0: Update event interrupt does not occur 1: Update event interrupt occurs When the counter value is reloaded or reinitialized, an update event will be generated. The bit is set to 1 by hardware and cleared by software;...
Page 222: Refer To Sts_Cc1Rcflg
Field Name Description Capture/compare Channel3 Repetition Capture Flag CC3RCFLG RC_W0 Refer to STS_CC1RCFLG Capture/compare Channel4 Repetition Capture Flag CC4RCFLG RC_W0 Refer to STS_CC1RCFLG 15:13 Reserved Control event generation register (TMRx_CEG) Offset address: 0x14 Reset value: 0x0000 Field Name Description Update Event Generate 0: Invalid 1: Initialize the counter and generate the update event This bit is set to 1 by software, and cleared by hardware.
Page 223 The timer can be configured as input (capture mode) or output (compare mode) by CCxSEL bit. The functions of other bits of the register are different in input and output modes, and the functions of the same bit are different in output mode and input mode.
Page 224 Field Name Description level changes when the comparison result changes or when the output compare mode changes from freeze mode to PWM mode. Output Compare Channel1 Clear Enable OC1CEN 0: OC1REF is unaffected by ETRF input. 1: When high level of ETRF input is detected, OC1REF=0 Capture/Compare Channel2 Select This bit defines the input/output direction and the selected input pin.
Page 225 Field Name Description 1010: DIV=16，N=5 1011: DIV=16，N=6 1100: DIV=16，N=8 1101: DIV=32，N=5 1110: DIV=32，N=6 1111: DIV=32，N=8 Sampling frequency=timer clock frequency/DIV; the filter length=N, indicating that a jump is generated by every N events. Capture/Compare Channel 2 Select 00: CC2 channel is output 01: CC2 channel is input, and IC2 is mapped on TI1 10: CC2 channel is input, and IC2 is mapped on TI2 CC2SEL...
Page 226 Field Name Description Capture/Compare Channel 4 Selection This bit defines the input/output direction and the selected input pin. 00: CC4 channel is output 01: CC4 channel is input, and IC4 is mapped on TI4 CC4SEL 10: CC4 channel is input, and IC4 is mapped on TI3 11: CC4 channel is input, and IC4 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is closed...
Page 227 Field Name Description Capture/Compare Channel1 Output Enable When the capture/compare channel 1 is configured as output: 0: Output is disabled 1: Output is enabled CC1EN When the capture/compare channel 1 is configured as input: This bit determines whether the value CNT of the counter can be captured and enter TMRx_CC1 register 0: Capture is disabled 1: Capture is enabled...
Page 228 Counter register (TMRx_CNT) Offset address: 0x24 Reset value: 0x0000 Field Name Description 15:0 Counter Value 31:16 Counter Value (only TMR2/TMR5) Prescaler register (TMRx_PSC) Offset address: 0x28 Reset value: 0x0000 Field Name Description Prescaler Value 15:0 Clock frequency of counter (CK_CNT)＝f /(PSC+1) CK_PSC Auto reload register (TMRx_AUTORLD)
Page 229 Field Name Description Capture/Compare Channel 2 Value 15:0 Refer to TMRx_CC1 Capture/Compare Channel 2 Value (only TMR2/TMR5) 31:16 Refer to TMRx_CC1 Channel 3 capture/compare register (TMRx_CC3) Offset address: 0x3C Reset value: 0x0000 Field Name Description Capture/Compare Channel 3 Value 15:0 Refer to TMRx_CC1 Capture/Compare Channel 3 Value (only TMR2/TMR5)
Page 230 Field Name Description 10001: Transmission for 18 times The transmission address formula is as follows: Transmission address=TMRx_CTRL1 address (slave address) +DBADDR+DMA index; DMA index=DBLEN For example: DBLEN=7, DBADDR=TMR1_CTRL1 (slave address) means the address of the data to be transmitted, while the address +DBADDR+7 of TMRx_CTRL1 means the address of the data to be written/read, Data transmission will occur to: TMRx_CTRL1 address + seven registers...
Page 231 TMR5 option register (TMR5_OPT) Offset address: 0x50 Reset value: 0x0000 Field Name Description Reserved Timer5 Channel4 Input Remap Select 00: TMR5 Channel 4 is connected to GPIO 01: LSICLK internal clock is connected to TMR5_CH 4 input for calibration RMPSEL 10: LSECLK internal clock is connected to TMR5_CH4 input for calibration 11: RTC wake-up interrupt is connected to TMR5_CH4 input for...
Page 232: General-Purpose Timer (Tmr9/10/11/12/13/14)
General-purpose timer (TMR9/10/11/12/13/14) Introduction The general-purpose timer takes the time base unit as the core, and has the functions of input capture and output compare, and can be used to measure the pulse width, frequency and duty cycle, and generate the output waveform. It includes a 16-bit auto reload counter (realize count-up, count-down and center- aligned count).
Page 233: Tmr9/12 Structure Block Diagram
 Internal clock Timer function  Input capture  Output compare  PWM output mode  Forced output mode  Single-pulse mode output Interrupt and DMA request event  Update event (counter overrun/underrun, counter initialization)  Input capture  Output compare TMR9/12 structure block diagram Figure 54 General-purpose Timer TMR9/12 Structure Block Diagram TI1FP1...
Page 234: Tmr10/11/13/14 Structure Block Diagram
TMR10/11/13/14 structure block diagram Figure 55 General-purpose Timer TMR10/11/13/14 Structure Block Diagram TI1FP1 IC1PS OC1REF Output Channel 1 capture/ TMRx_CH1 Filter edge detector TMRx_CH1 Prescaler compare register control Auto reload CNT counter register CK_CNT CK_PSC Internal clock CK_INT Trigger Prescaler controller Enable, count Functional description...
Page 235 the counter (TMRx_CNT) is equal to the value of the auto reload (TMRx_AUTORLD), the counter will start to count again from 0, a count-up overrun event will be generated, and the value of the auto reload (TMRx_AUTORLD) is written in advance. When the counter overruns, an update event will be generated.
Page 236 will start to count again from (TMRx_AUTORLD), meanwhile, a count-down overrun event will be generated, and the value of the auto reload (TMRx_AUTORLD) is written in advance. When the counter overruns, an update event will be generated. At this time, the repeat count register, the auto reload register and the prescaler register will be updated.
Page 237 the counter value is (AUTORLD-1), a counter overrun event will be generated; in counting down, when the counter value is 1, a counter underrun event will be generated. The figure below is Timing Diagram when Division Factor is 1 or 2 in Center- aligned Mode Figure 58 Timing Diagram when Division Factor is 1 or 2 in Center-aligned Mode CK_PSC...
Page 238 In the input capture, the measured signal will enter from the external pin T1/2/3/4 of the timer, first pass through the edge detector and input filter, and then into the capture channel. Each capture channel has a corresponding capture register. When the capture occurs, the value of the counter CNT will be latched in the capture register CCx.
Page 239 request will be generated. PWM input mode (only applicable to TMR9/12) PWM input mode is a particular case of input capture. In PWM input mode, as only TI1FP1 and TI1FP2 are connected to the slave mode controller, input can be performed only through the channels TMRx_CH1 and TMRx_CH2, which need to occupy the capure registers of CH1 and CH2.
Page 240 Figure 460 PWM1 Center-aligned Mode Timing Diagram AUTORLD OCXREF In PWM mode 2, if the value of the counter CNT is less than that of the compare register CCx, the output level will be invalid; otherwise, it will be valid. Set the timing diagram in PWM mode 2 when CCx=5, AUTORLD=7 Figure 61 PWM2 Center-aligned Mode Timing Diagram AUTORLD...
Page 241: Tmr9/12 Register Address Mapping
Figure 62 Single-pulse Mode Timing Diagram AUTORLD DELAY PULSE OCxREF Forced output mode In the forced output mode, the comparison result is ignored, and the corresponding level is directly output according to the configuration instruction.  CCxSEL=00 for TMRx_CCMx register, set CCx channel as output ...
Page 242: Tmr9/12 Register Functional Description
Register name Description Offset address TMRx_AUTORLD Auto reload register 0x2C TMRx_CC1 Channel 1 capture/compare register 0x34 TMRx_CC2 Channel 2 capture/compare register 0x38 TMR9/12 register functional description Control register 1 (TMRx_CTRL1) Offset address: 0x00 Reset value: 0x0000 Field Name Description Counter Enable 0: Disable 1: Enable CNTEN...
Page 243 Field Name Description 0: Disable 1: Enable Clock Divide Factor For the configuration of dead time and digital filter, CK_INT provides the clock, and the dead time and the clock of the digital filter can be adjusted by setting this bit. CLKDIV 00：t CK_INT...
Page 244 Field Name Description 011: Encoder mode 3; according to the input level of another signal, the counter counts at the edge of TI1FP1 and TI2FP2. 100: Reset mode; the slave mode timer resets the counter after receiving the rising edge signal of TRGI and generates the signal to update the register.
Page 245 Field Name Description Trigger interrupt Enable TRGIEN 0: Disable 1: Enable 15:7 Reserved State register (TMRx_STS) Offset address: 0x10 Reset value: 0x0000 Field Name Description Update Event Interrupt Generate Flag 0: Update event interrupt does not occur 1: Update event interrupt occurs When the counter value is reloaded or reinitialized, an update event will be generated.
Page 246 Field Name Description The value of the counter is captured to TMRx_CC1 register, and CC1IFLG=1; this bit is set to 1 by hardware and cleared by software only when the channel is configured as input capture. Capture/compare Channel2 Repetition Capture Flag CC2RCFLG RC_W0 Refer to STS_CC1RCFLG...
Page 247 mode and input mode. The OCX in the register describes the function of the channel in the output mode, and the ICx in the register describes the function of the channel in the input mode. Output compare mode: Field Name Description Capture/Compare Channel 1 Select This bit defines the input/output direction and the selected input pin.
Page 248 Field Name Description Capture/Compare Channel2 Select This bit defines the input/output direction and the selected input pin. 00: CC2 channel is output 01: CC2 channel is input, and IC2 is mapped on TI2 CC2SEL 10: CC2 channel is input, and IC2 is mapped on TI1 11: CC2 channel is input, and IC2 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is closed...
Page 249 Field Name Description 1111: DIV=32，N=8 Sampling frequency=timer clock frequency/DIV; the filter length=N, indicating that a jump is generated by every N events. Capture/Compare Channel 2 Select 00: CC2 channel is output 01: CC2 channel is input, and IC2 is mapped on TI1 10: CC2 channel is input, and IC2 is mapped on TI2 CC2SEL 11: CC2 channel is input, and IC2 is mapped on TRC, and only works in...
Page 250 Field Name Description Reserved Capture/Compare Channel1 Output Polarity Configure When CC1 channel is configured as output: CC1NPOL remains in cleared state all the time CC1NPOL When CC1 channel is configured as input: This bit and CC1POL control the polarity of the triggered or captured signals TI1FP1 and TI2FP1 at the same time.
Page 251: Tmr10/11/13/14 Register Address Mapping
Channel 1 capture/compare register (TMRx_CC1) Offset address: 0x34 Reset value: 0x0000 Field Name Description Capture/Compare Channel 1 Value When the capture/compare channel 1 is configured as input mode: CC1 contains the counter value transmitted by the last input capture channel 1 event.
Page 252: Tmr10/11/13/14 Register Functional Description
Register name Description Offset address TMR11_OPT Option register 0x50 TMR10/11/13/14 register functional description Control register 1 (TMRx_CTRL1) Offset address: 0x00 Reset value: 0x0000 Field Name Description Counter Enable 0: Disable 1: Enable CNTEN When the timer is configured as external clock, gated mode and encoder mode, it is required to write 1 to the bit by software to start regular work;...
Page 253: State Register (Tmrx_Sts)
Field Name Description 11: Reserved 15:10 Reserved DMA/Interrupt enable register (TMRx_DIEN) Offset address: 0x0C Reset value: 0x0000 Field Name Description Update interrupt Enable UIEN 0: Disable 1: Enable Capture/Compare Channel1 Interrupt Enable CC1IEN 0: Disable 1: Enable 15:2 Reserved State register (TMRx_STS) Offset address: 0x10 Reset value: 0x0000 Field...
Page 254: Capture/Compare Channel1 Repetition Capture Flag
Field Name Description Capture/compare Channel1 Repetition Capture Flag 0: Repeat capture does not occur 1: Repeat capture occurs CC1RCFLG RC_W0 The value of the counter is captured to TMRx_CC1 register, and CC1IFLG=1; this bit is set to 1 by hardware and cleared by software only when the channel is configured as input capture.
Page 255 Field Name Description Capture/Compare Channel 1 Select This bit defines the input/output direction and the selected input pin. 00: CC1 channel is output 01: CC1 channel is input, and IC1 is mapped on TI1 CC1SEL 10: CC1 channel is input, and IC1 is mapped on TI2 11: CC1 channel is input, and IC1 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is closed...
Page 256 Field Name Description Capture/Compare Channel 1 Select 00: CC1 channel is output 01: CC1 channel is input, and IC1 is mapped on TI1 10: CC1 channel is input, and IC1 is mapped on TI2 CC1SEL 11: CC1 channel is input, and IC1 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is closed (TMRx_CCEN bit CC1EN=0).
Page 257 Field Name Description 1: Capture is enabled Capture/Compare Channel1 Output Polarity Configure When CC1 channel is configured as output: 0: OC1 high level is valid 1: OC1 low level is valid When CC1 channel is configured as input: CC1POL and CC1NPOL control the polarity of the triggered or captured signals TI1FP1 and TI2FP1 at the same time 00: Non-phase-inverting/rising edge: TIxFP1 is not reversed phase (triggered in gated and encoder mode),...
Page 258 Reset value: 0x0000 Field Name Description Prescaler Value 15:0 Clock frequency of counter (CK_CNT)＝f /(PSC+1) CK_PSC Auto reload register (TMRx_AUTORLD) Offset address: 0x2C Reset value: 0xFFFF Field Name Description Auto Reload Value 15:0 AUTORLD When the value of auto reload is empty, the counter will not count. Channel 1 capture/compare register (TMRx_CC1) Offset address: 0x34 Reset value: 0x0000...
Page 259: Basic Timer (Tmr6/7)
Basic timer (TMR6/7) Introduction The basic timers TMR6 and TMR7 have an unsigned 16-bit counter, auto reload register, prescaler and trigger controller. The basic timer provides time reference for general-purpose timer and provides clock for DAC. DMA request can be generated by configuration. Main characteristics Counter: 16-bit counter, which can only count up Prescaler: 16-bit programmable prescaler...
Page 260 Timebase unit The time base unit in the basic timer contains three registers:  16-bit counter register (CNT)  16-bit auto reload register (AUTORLD)  16-bit prescaler register (PSC) Counter CNT The basic timer only has one count mode: count-up Count-up mode When the counter is in count-up mode, the counter will count up from 0;...
Page 261: Register Address Mapping
Figure 64 Timer Timing Diagram, the internal clock division factor is 1 or 2 CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter overrun Update event CK_CNT PSC=2 0002 0003 0024 0025 0000 0001 0026 Counter register Counter overrun Update event Prescaler PSC The prescaler is 16 bits and programmable, and it can divide the clock frequency of the counter to any value between 1 and 65536 (controlled by TMRx_PSC register), and after frequency division, the clock will drive the...
Page 262: Register Functional Description
Register name Description Offset address TMRx_CEG Control event generation register 0x14 TMRx_CNT Counter register 0x24 TMRx_PSC Prescaler register 0x28 TMRx_AUTORLD Auto reload register 0x2C Register functional description Control register 1 (TMRx_CTRL1) Offset address: 0x00 Reset value: 0x0000 Field Name Description Counter Enable 0: Disable 1: Enable...
Page 263 Field Name Description Auto-reload Preload Enable When the buffer is disabled, the program modification TMRx_AUTORLD will immediately modify the values loaded to the counter; when the buffer is enabled, the program modification TMRx_AUTORLD will modify the ARPEN values loaded to the counter in the next update event. 0: Disable 1: Enable 15:8...
Page 264 State register (TMRx_STS) Offset address: 0x10 Reset value: 0x0000 Field Name Description Update Event Interrupt Generate Flag 0: Update event interrupt does not occur 1: Update event interrupt occurs When the counter value is reloaded or reinitialized, an update event will be generated.
Page 265 Field Name Description Prescaler Value 15:0 Clock frequency of counter (CK_CNT)＝f /(PSC+1) CK_PSC Auto reload register (TMRx_AUTORLD) Offset address: 0x2C Reset value: 0xFFFF Field Name Description Auto Reload Value 15:0 AUTORLD When the value of auto reload is empty, the counter will not count. www.geehy.com Page 264...
Page 266: Watchdog Timer (Wdt)
Watchdog timer (WDT) Introduction The watchdog is used to monitor system failures caused by software errors. There are two watchdog devices on the chip: independent watchdog and window watchdog, which improve the security, and make the time more accurate and the use more flexible. The independent watchdog will reset only when the counter is reduced to 0, and the value of refresh counter will not be reset until it is not reduced to 0.
Page 267 Note: The watchdog function is in the V power supply area and can work normally in the shutdown or standby mode. Functional description Key register Write 0xCCCC in the key register to enable the independent watchdog, then the counter starts to count down, and when the counter counts to 0x000, a reset will be generated.
Page 268: Window Watchdog Timer (Wwdt)
Window watchdog timer (WWDT) Introduction The window watchdog contains a 7-bit free-running down counter, prescaler and control register WWDT_CTRL, configuration register WWDT_CFG and state register WWDT_STS. The window watchdog clock comes from PCLK1, and the counter clock is obtained from the CK counter clock through frequency division by prescaler (configured by the configuration register).
Page 269: Iwdt Register Address Mappin
Figure 67 Window Watchdog Timing Diagram Counter Start Counter Start Window value 0x3F Window value Reload Generate Reload counter counter reset Generate reset CNT＞window value The calculation formula of window watchdog timer timeout is as follows: ×2 ×（T[5:0]+1） WWDT PCLK1 Wherein: ...
Page 270: Iwdt Register Functional Description
IWDT register functional description These peripheral registers can be operated by half word (16 bits) or word (32 bits). Key register (IWDT_KEY) Offset address: 0x00 Reset value: 0x0000 0000 (reset in standby mode) Field Name Description Allow Access IWDT Register Key Value Writing 0x5555 means enabled access to IWDT_PSC and IWDT_CNTRLD registers;...
Page 271: Wwdt Register Address Mappin
Field Name Description CNTUFLG=0. In the process of reading this register, when CNTUFLG=0 in IWDT_STS register, the read value is valid. The watchdog timeout cyclecan be calculated by the reload value and clock prescaled value. 31:12 Reserved State register (IWDT_STS) Offset address: 0x0C Reset value: 0x0000 0000 (not reset in standby mode) Field...
Page 272 Field Name Description Window Watchdog Enable This bit is set to 1 by software and can be cleared by hardware only after reset. When WWDTEN=1, WWDT can generate a reset. WWDTEN 0: Disable 1: Enable 31:8 Reserved Configuration register (WWDT_CFG) Offset address: 0x04 Reset value: 0x0000 007F Field...
Page 273: Real-Time Clock (Rtc)
Real-time clock (RTC) Full name and abbreviation description of terms Table 79 Full name and abbreviation description of terms Full name in English English abbreviation Second Alarm Prescaler Introduction It has sub-second, time and date registers with BCD coding, as well as corresponding alarm registers, and can realize timestamp function together with external pins.
Page 274: Functional Description
Figure 68 RTC Structure Block Diagram RTC_TAMP1 Backup and tamper RTC_TAMP2 sampling controller TSEN Timestamp RTC_TS controller TSFLG Timestamp Match ALRAFLG Alarm A TPxEN Calendar LSECLK Digital Asynchronous Synchronous Time and date HSECLK prescaler calibration prescaler Subsecond calibration RTC_AF2 register 7bit register 15bit...
Page 275 should be as low as possible. Considering power consumption, RTC internally adopts dual prescaler, 7-bit asynchronous prescaler APSC and 15-bit synchronous prescaler SPSC. RTCCLK first passes through the asynchronous prescaler, and the clock after frequency division reaches the synchronous prescaler. Two prescalers can be reasonably configured to generate a 1Hz clock for date.
Page 276 RTC uses 2 RTCCLK as a calibration cycle by default. In addition, 2 and 2 RTCCLK can be set as a calibration cycle through the registers CALW16 and CALW8. When LSECLK is used as RTCCLK clock source, the calibration cycle of RTC is 32s, 16s, 8s.
Page 277 is too small, to ensure the normal reading of date value, it is required to APB1 read the shadow register twice. If the date obtained twice is the same, the date is read successfully. After the shadow register is updated, the flag bit RSFLG will be set. The software can read the date only after the bit RSFLG is set.
Page 278 timestamp register. The timestamp polarity is detected through TSETECFG bit of the register RTC_CTRL. When RTC_TS pin recognizes the external timestamp edge signal, RTC will automatically latch the current date in the subsecond, time and date timestamp registers, and the timestamp flag bit TSFLG will be set to 1. If the timestamp interrupt is enabled, the timestamp interrupt processing will be triggered.
Page 279 Tamper signal filter TPSFSEL bit of the register RTC_TACFG is used to configure the sampling frequency of tamper detection, and TPFCSEL bit of RTC_TACFG is used to configure after how many valid tamper signals are detected continuously, an tamper event can be generated. In particular, if an tamper signal has been generated on the tamper detection pin before the tamper detection pin is enabled, an tamper event will be immediately generated on the enabled tamper detection pin.
Page 280: Register Address Mapping
Calibration multiplexing function output When CALOEN bit of RTC_CTRL register is set, RTC_AF1 will enable the calibration multiplexing function. Alarm and automatic wake-up signal When the alarm or automatic wake-up is running, these two events can be output as pulse signals. OUTSEL bit of RTC_CTRL register is used to select the signal output source, and POLCFG bit is used to configure the output polarity.
Page 281: Register Functional Description
Register functional description RTC time register (RTC_TIME) RTC_TIME is time shadow register, and this register can be written only in initialization mode to be put in write protection state. Offset address: 0x00 Reset value of backup domain: 0x0000 0000 System reset: RCMCFG =0: 0x0000 0000; RCMCFG =1: 0xXXXX XXXX Field Name Description...
Page 282 Field Name Description 19:16 Year Ones Unit in BCD Format Setup 23:20 Year Ten's Place Unit in BCD Format Setup 31:24 Reserved RTC control register (RTC_CTRL) The bits 7, 6 and 4 of this register can be written only in initialization mode.
Page 283 Field Name Description Time Format Configure TIMEFCFG 0: 24-hour/day format 1: AM/PM time format Coarse Digital Calibration Enable 0: Disable DCALEN 1: Enable Require APSC≥6 Alarm A Function Enable ALRAEN 0: Disable 1: Enable Alarm B Function Enable ALRBEN 0: Disable 1: Enable Wakeup Timer Enable WUTEN...
Page 284 Field Name Description Backup Value Setup BAKP This bit indicates whether the summer time has changed and is written by the user. Calibration Output Value Select When CALOEN=1, this bit is used to select the output signal of RTC_CALIB. CALOSEL 0: 512Hz 1: 1Hz The above frequency is valid when RTCCLK is 32.768kHz and the...
Page 285 Field Name Description Wakeup Timer Write Occur Flag When WUTEN=0 and the value of wake-up timer can be changed, this bit can be set by hardware. WUTWFLG 0: It is not allowed to update the wake-up timer configuration 1: It is allowed to update the wake-up timer configuration Shift Operation Pending Occur Flag 0: Not occur 1: Occurred...
Page 286 Field Name Description Wakeup Timer Occur Flag When the auto refresh counter counts to 0, this bit will be set to 1 WUTFLG RC_W0 by hardware; it is cleared by writing 0 by software. Clear this flag 1.5 RTCCLK cycles before WUTFLG is set to 1 again.
Page 287 RTC auto reload register (RTC_AUTORLD) This register can be written only when WUTEFLG of RTC_STS is set to 1, and it is in write protection state. Offset address: 0x14 Reset value of backup domain: 0x0000 FFFF System reset: 0xXXXX XXXX Field Name Description...
Page 288 RTC alarm A register (RTC_ALRMA) This register can be written only when ALRWFLG of RTC_STS is set to 1 or in initialization mode, and it is in write protection state. Offset address: 0x1C Reset value of backup domain: 0x0000 0000 System reset: 0xXXXX XXXX Field Name...
Page 289 Field Name Description SECT Second Ten's Place Unit in BCD Format Setup Alarm B Seconds Mask Enable SECMEN 0: If the "second" matches, set Alarm B 1: Mask the effect of the "second" value on Alarm B 11:8 MINU Minute Ones Unit in BCD Format Setup 14:12 MINT Minute Ten's Place Unit in BCD Format Setup...
Page 290 Field Name Description Sub Second Value Setup SUBSEC is the value of synchronous prescaler counter. It is determined by the following formula: 15:0 SUBSEC Subsecond value=(SPSC-SUBSEC)/(SPSC+1) After one shift operation is performed, SUBSEC may be greater than SPSC. The correct time/date is one second less than RTC_TIME/RTC_DATE.
Page 291 Field Name Description SECT Second Ten's Place Unit in BCD Format Setup Reserved 11:8 MINU Minute Ones Unit in BCD Format Setup 14:12 MINT Minute Ten's Place Unit in BCD Format Setup Reserved 19:16 Hour Ones Unit in BCD Format Setup 21:20 Hour Ten's Place Unit in BCD Format Setup Time Format Configure...
Page 292 Field Name Description Sub Second Value Setup 15:0 SUBSEC When a timestamp event occurs, SUBSEC [15:0] is the value in synchronous prescaler counter. 31:16 Reserved RTC precision calibration register (RTC_CAL) This register is in write protection state. Offset address: 0x3C Reset value of backup domain: 0x0000 0000 System reset: 0xXXXX XXXX Field...
Page 293 Field Name Description 1: Enable RTC_TAMP1 Input Active Level Configure When TPFCSEL!=00, this bit determines that RTC_TAMP1 will trigger an tamper detection event when the input maintains high/low level. 0: Low level TP1ALCFG 1: High level When TPFCSEL=00, this bit determines that RTC_TAMP1 triggers an tamper detection event when the input is on rising/falling edge.
Page 294 Field Name Description These bits detemine the number of sampling times after which the tamper event is activated on specific level (TAMP*TRG). TPFCSEL is valid for each input of RTC_TAMPx. 0x0: Activate the tamper event on the edge where RTC_TAMPx input is converted into valid level 0x1: Continuous sampling twice 0x2: Continuous sampling for four times...
Page 295 Field Name Description 23:15 Reserved Mask the Most-significant Bits Starting at This Bit Select 0x0: Alarm A is not compared. The alarm is set when the second unit increases by 1 0x1: When comparing with alarm A, SUBSEC[14:1] is not involved, and only SUBSEC[0] is involved 0x2: When comparing with alarm A, SUBSEC[14:2] is not involved, and only SUBSEC[1:0] is involved...
Page 296 Field Name Description 0xD: When comparing with alarm B, SUBSEC[14:13] is not involved, and only SUBSEC[12:0] is involved 0xE: When comparing with alarm B, SUBSEC[14] is not involved, and only SUBSEC[13:0] is involved 0xE: When comparing the alarm B, 15 SUBSEC bits all take part in, and the alarm can be activated only when all of them match.
Page 297: Hash Processor (Hash)
HASH processor (HASH) Introduction The hash processor complies with the secure hash algorithm, MD5 hash algorithm and HMAC hash algorithm. HMAC hash algorithm verifies the message through hash function. In addition, other algorithms are used to calculate 2 -1-bit message digest. HMAC algorithm includes calling SHA-1 or MD5 hash function twice.
Page 298: Register Address Mapping
efficiency of the process. The generating program and verification program of digital signature need to use the same hash algorithm. SHA-1 and MD5 are secure because of failing to find the corresponding message of a certain specified message digest or two different messages that generate the same message digest.
Page 299 Field Name Description (1) This bit will be cleared to zero by the hardware when the DMA transmits the last data of the transmission message. This bit cannot be cleared to zero when INITCAL=1. (2) If this bit is not set, but DMA transmission has been requested at this time, this bit will be cleared to zero but the current transmission cannot be suspended.
Page 300 Field Name Description 1: Data at least including one word 15:13 Reserved Key Select In HMAC mode: 0: Short key (≤64 bytes) LKEYSEL 1: Long key (>64 bytes) This bit is valid only when INITCAL bit and MODESEL bit are set to 1 at the same time.
Page 301 Reset value: 0x0000 0000 x is 0…4, that is, there are 5 registers, each of which is used to store digest results. [31:0] bit of HASH_DIG0 register is DIG0, [31:0] bit of HASH_DIG1 register is DIG1, and so on. Field Name Description 31:0...
Page 302 Field Name Description Busy Bit Whether the bush core is busy: BUSY 0: Idle 1: Busy 31:4 Reserved HASH exchange context register x (HASH_CTSWAPx) Offset address: 0xF8+(x*0x04), x=0…50 Reset value of HASH_CTSWAP0 register: 0x0000 0002 Reset value of HASH_CTSWAP1-50 register: 0x0000 0000 x is 0…50, that is, there are 51 registers.
Page 303: Digital Camera Interface (Dci)
Digital camera interface (DCI) Note: Only APM32F407/417xExG series products have such module. Full name and abbreviation description of terms Table 82 Full name and abbreviation description of terms Full name in English English abbreviation Digital Camera Interface Joint Photo Experts Group JPEG Horizontal Synchronization HSYNC...
Page 304: Structure Block Diagram
Structure block diagram Figure 69 DCI Structure Block Diagram HCLK DCI_PIXCLK DCI_D FIFO/Data Synchronizer Data extraction formatting DCI_HSYNC DCI_VSYNC Control/State register DMA interface HCLK Functional description Signal description The physical interface input signal of DCI (in slave mode) consists of 8/10/12/14-bit data DCI_ D, pixel clock PIXCLK, horizontal synchronization/data valid HSYNC and vertical synchronization VSYNC.
Page 305 As shown in the following table, the captured data of four widths are different in the storage position of 32-bit data word, and the number of pixel clock cycles for generating 32-bit data words is also different. Table 84 Position Arrangement of Four Widths and Number of PIXCLK Required 8-bit data 10-bit data 12-bit data...
Page 306 The synchronization code has 4 event types:  Frame start (FS)  Frame end (FE)  Line start (LS)  Line end (LE) It consists of 4 bytes, all of which are in the format of 0xFF 00 00 XX (synchronization code).
Page 307 Figure 70 Parameter Definitions in Cropping Window VSLINECNT HOFSCNT VLINECNT CCNT It should be noted that only when the value of CCNT is a multiple of 4, can data be transmitted through DMA. JPEG format Since JPEG is stored as data rather than frame or line, only when VSYNC is used as the start signal and HSYNC is used as the data enable signal, can the module receive JPEG images.
Page 308: Register Address Mapping
 RGB565 The frame buffers of the above three kinds of data are stored in raster mode, with 32-bit words and they support little-endian alignment format. Raster mode refers to start to scan from word 0 of pixel line 0 in the order of increasing address.
Page 309: Register Functional Description
Register name Description Offset address DCI_INTCLR DCI clear interrupt register 0x14 DCI_ESYNCC DCI embedded synchronization code register 0x18 DCI_ESYNCUM DCI embedded synchronization unmask register 0x1C DCI_CROPWSTAT DCI cropping window start register 0x20 DCI_CROPWSIZE DCI cropping window size register 0x24 DCI_DATA DCI data register 0x28 Register functional description...
Page 310 Field Name Description Frame Capture Rate Configure In continuous acquisition mode, this bit configures the frame capture frequency. 00: Capture all frames FCRCFG 01: Capture every other frame 10: Capture every three frames 11: Reserved Extended Data Mode Select the width of data to be captured by each PIXCLK. 00: 8 bits 11:10 EXDMOD...
Page 311 Field Name Description Overrun Raw Interrupt Status OVR_RINT 0: No overrun 1: Data underflow Synchronization Error Raw Interrupt Status In the embedded code synchronization mode, if the module does not receive the embedded code in the correct order, a SYNCERR_RINT synchronization error interrupt will be generated.
Page 312 Field Name Description Overrun Masked Interrupt Status OVR_MINT 0: Mask 1: Not mask Synchronization Error Masked Interrupt Status SYNCERR_MINT 0: Mask 1: Not mask VSYNC Signal Masked Interrupt Status VSYNC_MINT 0: Mask 1: Not mask Line Masked Interrupt Status LINE_MINT 0: Mask 1: Not mask 31:5...
Page 313 DCI embedded synchronization unmask register (DCI_ESYNCUM) Offset address: 0x1C Reset value: 0x0000 0000 This register is used to determine whether to mask the embedded code separator. When masked, the received data will not be compared with the separator. When the separator is unmasked, the module will compare the value in DCI_ESYNCC with the value of the corresponding bit of the data.
Page 314 Field Name Description Capture Count The value of this bit is the number of PIXCLK to be captured in the window. 13:0 CCNT 0x0000: 1 0x0001: 2 …… 15:14 Reserved Vertical Line Count Tis value is the number of lines included in the window. 29:16 VLINECNT 0x0000: 1 line...
Page 315: Universal Synchronous/Asynchronous Transceiver (Usart)
Universal synchronous/asynchronous transceiver (USART) Full name and abbreviation description of terms Table 87 Full name and abbreviation description of terms Full name in English English abbreviation Clear to Send Request to Send Most Significant Bit Least Significant Bit Guard Overrun Introduction USART (universal synchronous/asynchronous transceiver) is a serial communication device that can flexibly exchange full-duplex and half-duplex...
Page 316  Transmit the check bit  Check the received data Select speed and clock tolerance with programmable 8 or 16-time oversampling rate Independent transmitter and receiver enable bit Programmable baud rate generator Multiprocessor communication:  If the address does not match, it will enter the mute mode ...
Page 317: Functional Description
Functional description Table 88 USAR Pin Description Type Description USART_RX Input Data receiving Data transmission Output It is high level by default when the USART_TX I/O (single-line mode/smart transmitter is enabled and does not transmit card mode) data USART_CK Output Clock output Request to send in hardware flow control USART_nRTS...
Page 318 Table 89 Frame Format DBLCFG bit PCEN bit USART data frame Start bit+8-bit data+stop bit Start bit+7-bit data+odd-even parity check bit+stop bit Start bit+9-bit data+stop bit Start bit+8-bit data+odd-even parity check bit+stop bit Configurable stop bit Four different stop bits can be configured through STOPCFG bit of USART_CTRL2 register.
Page 319  Decide the word length by setting DBLCFG bit of USART_CTRL1 register.  Decide the number of stop bits by setting STOPCFG bit of USART_CTRL2 register.  If multi-buffer communication is selected, DMA should be enabled in USART_CTRL3 register.  Set the baud rate of communication in USART_BR register. ...
Page 320 TXBF bit is set, after completion of transmission of current data, the TX line will transmit a break frame, and after completion of transmission of break frame, the TXBF bit will be reset. At the end of the break frame, the transmitter inserts one or two stop bits to respond to the start bit.
Page 321 In single buffer mode, the RXBNEFLG bit can be cleared by reading USART_DATA register by software or by writing 0. In multi-buffer mode, after each byte is received, RXBNEFLG bit of USART_STS register will be set to 1, and DMA will read the data register to clear it. Break frame When the receiver receives a break frame, USART will handle it as receiving a frame error.
Page 322 Noise error When noise is detected in receiving process of the receiver:  Set NE flag on the rising edge of RXBNEFLG bit of USART_STS register.  Invalid data is transmitted from the shift register to USART_DATA register. Note: 8-time oversampling ratio cannot be used in LIN, smart card and IrDA modes. Frame error If the stop bit is not received and recognized at the expected receiving time due to excessive noise or lack of synchronization, a frame error will be detected.
Page 323 waken up from the mute mode when an idle frame is detected, meanwhile, the RXMUTEEN bit will be cleared by the hardware. RXMUTEEN can also be cleared by software. Figure 71 Idle Bus Exit Mute Mode RXBNEFLG set to 1 by hardware Data 1 Data 2 Data 3...
Page 324 CLKEN bit of USART_CTRL2 register decides whether to enter the synchronous mode. When USART enters the synchronous mode:  The LINMEN bit of USART_CTRL2 register, and IREN, HDEN and SCEN bits of USART_CTRL3 register must be cleared.  The start bit and stop bit of data frame have no clock output. ...
Page 325 Figure 75 USART Synchronous Transmission Timing Diagram (DBLCFG=1) DBLCFG=1(9-bit data） CK(CPOL=0,CPHA=0) CK(CPOL=0,CPHA=1) CK(CPOL=1,CPHA=0) CK(CPOL=1,CPHA=1) Start Stop TX (from master device) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 0 Bit 1 Bit 2 Bit 3...
Page 326 Figure 76 Break Frame Detection in Idle State Idle Data 1 Data 2 Break frame Data 3 Data 4 Data 5 frame FEFLG USART_DATA Data 1 Data 2 0x00 Data 3 Data 4 LBDFLG Break frame detection in data transmission state In the process of data transmission, if the RX pin detects the break frame, the currently transmitted data frame will generate FEFLG.
Page 327  During the communication, when the receiver detects a parity error, in order to inform the transmitter that the data has not been received successfully, the data line will be pulled down after half a baud rate clock, and keep pulling down for one baud rate clock. ...
Page 328 Figure 79 IrDA Mode Block Diagram Receive USART_RX decoder USART SIREN Transmit decoder USART_TX Hardware flow control The function of hardware flow control is to control the serial data stream between two devices through nCTS pin and nRTS pin. Figure 80 Hardware Flow Control between Two USART CTS flow control CTSEN bit of USART_CTRL3 register determines whether CTS flow control is enabled.
Page 329 enabled. If RTS flow control is enabled, when the receiver receives data, nRTS will be pulled to low level. When a data frame is received, nRTS will becomes high to inform the transmitter to stop transmitting data frame. DMA multi-processor communication USART can access the data buffer in DMA mode in order to reduce the burden of processors.
Page 330 Interrupt request Table 90 USART Interrupt Request Interrupt event Event flag bit Enable bit The receive register cannot be empty RXBNEFLG RXBNEIEN Overload error OVREFLG Line idle is detected IDLEFLG IDLEIEN Odd-even parity error PEFLG PEIEN LIN break frame flag LBDFLG LBDIEN Noise error...
Page 331: Register Address Mapping
USART mode USART1 USART2 USART3 UART4 UART5 Hardware flow control √ √ √ — — Multi-buffer √ √ √ √ — communication (DMA) Multi-processor √ √ √ √ √ communication Synchronous √ √ √ — — Smart card √ √ √...
Page 332 Field Name Description Frame Error Occur Flag 0: No frame error 1: A frame error or disconnection symbol appeared FEFLG When there is synchronous dislocation, too much noise or disconnection symbol, set to 1 by hardware; This bit can be cleared by software; first read USART_STS register, and then read USART_DATA register to complete clearing.
Page 333 Field Name Description LIN Break Detected Flag 0: LIN disconnection not detected 1: LIN disconnection detected LBDFLG RC_W0 When LIN disconnection is detected, set to 1 by hardware; This bit can be cleared by software; or cleared by writing 0 to this bit.
Page 334 Field Name Description Transmit Break Frame 0: Not transmit TXBF 1: Will transmit This bit can be set by software and cleared by hardware when the stop bit of the break frame is sent. Receive Mute Mode Enable 0: Normal working mode 1: Mute mode This bit is set or cleared by software, or cleared by hardware when RXMUTEEN...
Page 335 Field Name Description Parity Control Enable 0: Disable 1: Enable If this bit is set, a check bit will be inserted in the most significant bit PCEN when transmitting data; when receiving data, check whether the check bit of the received data is correct. The check control will not take effect until the current transmission of bytes is completed.
Page 336 Field Name Description This bit is valid only in synchronous mode; this bit does not exist on UART4 and UART5. Clock Phase Configure This bit indicates on the edge of which clock sampling is conducted 0: The first CPHA 1: The second This bit is valid only in synchronous mode;...
Page 337 Field Name Description Half-duplex Mode Enable HDEN 0: Disable 1: Enable NACK Transmit Enable During Parity Error in Smartcard Function 0: NACK is not sent SCNACKEN 1: Transmit NACK This bit does not exist on UART4 and UART5. Smartcard Function Enable 0: Disable SCEN 1: Enable...
Page 338 Field Name Description 31:12 Reserved Protection time and prescaler register (USART_GTPSC) Offset address: 0x18 Reset value: 0x0000 Field Name Description Prescaler Factor Setup Divide the frequency and provide clock for the system clock respectively; in different working modes, the valid bits of PSC have difference, specifically as follows: In infrared low-power mode: PSC[7:0] is valid.
Page 339: Internal Integrated Circuit Interface (I2C)
Internal integrated circuit interface (I2C) Full name and abbreviation description of terms Table 93 Full name and abbreviation description of terms Full name in English English abbreviation Serial Data Serial Clock System Management Bus SMBus Clock Serial Clock High SCLH Serial Clock Low SCLL Address Resolution Protocol...
Page 340 Two communication speeds  Standard mode  Fast mode Programmable clock extension State flag  Transmitter/Receiver mode flag  Flag for end of byte transmission  Flag of busy bus Error flag  Arbitration loss  Acknowledgment error  Wrong start bit or stop bit detected Interrupt source ...
Page 341: Structure Block Diagram
Structure block diagram Figure 82 I2C Functional Structure Diagram PEC register Data controller GPIO Shift register calculation Control Clock GPIO register controller ALTE Control logic circuit GPIO Interrupt The interface can be configured to the following modes:  Slave transmitting ...
Page 342 Special terms Description Multiple Multiple masters that control the bus at the same time without destroying masters information Synchronous The process of synchronizing the clock signals between two or more devices If more than one master tries to control the bus at the same time, only one master Arbitration can control the bus, and the information of the controlled master will not be destroyed...
Page 343 Three communication modes: Standard mode (up to 100KHz), fast mode (up to 400KHz), and fast mode plus (up to 1MHz). When multiple masters use the bus at the same time, to prevent the data collision, the bus arbitration mode is adopted to determine which device occupies the bus.
Page 344 Figure 85 Master Reads Data from Slave Remarks: （1） : This data is transmitted from master to slave S: Start signal （2） SLAVE ADDRESS: Slave address （3） : This data is transmitted from slave to master （4） R/W: Selection bit of transmission direction （5）...
Page 345 Data validity In the process of data transmission, the data on SDA line must be stable when the clock signal SCL is at high level. Only when the SCL is at the low level, can the level state of SDA be changed, and the bit transmission of each data needs a clock pulse.
Page 346 which master completes the transmission. Arbitration is conducted by bit. During each arbitration, when SCL is high, each master will check whether the SDA level is the same as that sent by itself. The arbitration process needs to last for many bits. Theoretically, if two masters transmit exactly the same content, they can successfully transmit without arbitration failure.
Page 347 Error flag bit Table 95 The following several error flag bits exist in I2C communication Error flag bit Description of error flag bit Answer error flag bit (AEFLG) No answer received Bus error flag bit (BERRFLG) An external stop or start condition is detected Arbitration loss flag bit (ALFLG) Arbitration loss is detected by the interface In slave mode, the received data is not read out, the...
Page 348: Register Address Mapping
I2C interrupt Table 96 I2C Interrupt Request Interrupt event Event flag bit Interrupt control bit Transmitting start bit completed STARTFLG Transmission completed/Address matching address signal ADDRFLG 10-bit address head segment transmission completed ADDR10FLG EVIEN Received stop signal STOPFLG Data byte transmission completed BTCFLG Receive buffer not empty RXBNEFLG...
Page 349 Reset value: 0x0000 Field Name Description I2C Enable I2CEN 0: Disable 1: Enable SMBus Mode Enable SMBEN 0: I2C mode 1: SMBus mode Reserved SMBus Type Configure SMBTCFG 0: SMBus device 1: SMBus master ARP Enable 0: Disable ARPEN 1: Enable If SMBTCFG=0, use the default address of SMBus device If SMBTCFG=1, use the primary address of SMBus PEC Enable...
Page 350 Field Name Description Acknowledge /PEC Position Configure This bit can be set to 1 or cleared by software; when I2CEN=0, it is cleared by hardware. ACKPOS 0: When receiving current byte, whether transmitting NACK/ACK, whether PEC is in shift register 1: When receiving next byte, whether transmitting NACK/ACK and whether PEC is in the next byte of shift register Packet Error Check Transfer Enable...
Page 351 Field Name Description Error Interrupt Enable 0: Disable ERRIEN 1: When the position 1 of any of the following state register is enabled, the interrupt will be generated: SMBALTFLG, TTEFLG, PECEFLG, OVRURFLG, AEFLG, ALFLG, and STS1_BERRFLG Event Interrupt Enable 0: Disable 1: When the position 1 of any of the following state registers is enabled, EVIEN the interrupt will be generated: STARTFLG, ADDRFLG, ADDR10FLG,...
Page 352 Field Name Description Slave Address Number Configure In the slave 7-bit address mode, it can be configured to identify the single-address mode and double-address mode; only ADDR1 is identified in single-address mode; both ADDR1 and ADDR2 can be identified in double-address mode ADDRNUM Single or double address registers can be identified in 7-bit address mode, specifically as follows:...
Page 353 Field Name Description When receiving data, if failing to read the data received in DATA register, and a new data is received then, set to 1 by hardwre; When transmitting data, if the DATA register is empty, to transmit the data in the shift register, set to 1 by hardware. This bit can be cleared after the software first reads STS1 register, and then reads or writes the DATA register;...
Page 354 Field Name Description cleared after the software writes 0; when I2CEN=0, it can be cleared by hardware. Master Mode Arbitration Lost Flag 0: No arbitration loss 1: In case of arbitration loss, I2C interface will automatically switch back to slave mode ALFLG RC_W0 "Arbitration loss in master mode"...
Page 355 Field Name Description This bit can be cleared by writing 0 by software; or be cleared by hardware when I2CEN=0. SMBus Alert Occur Flag 0: SMBus master mode, without alarm; SMBus slave mode, without alarm, SMBAlert pin level unchanged 1: SMBus master mode, with an alarm generated on the pin; SMBALTFLG RC_W0 SMBus slave mode, receiving an alarm, causing SMBAlert pin...
Page 356 Field Name Description (1) Stop bit is generated (2) Repeated start bit is generated (3) I2CEN=0 SMBus Device Received Default Address Flag in Slave Mode 0: Failed to receive the default address 1: Received the default address when ARPEN=1 This bit can be set to 1 by hardware; and be cleared by SMBDADDRFLG hardware when one of the following conditions is met: (1) Stop bit is generated...
Page 357 Field Name Description Tlow=16 × CLKS × T PCLK1 13:12 Reserved Fast Mode Duty Cycle Configure Here it is defined that the duty cycle=tlow/thigh FDUTYCFG 0: SCLK duty cycle is 2 1: SCLK duty cycle is 16/9 Master Mode Speed Configure SPEEDCFG 0: Standard mode 1: Fast mode...
Page 358: Serial Peripheral Interface/On-Chip Audio Interface (Spi/I2S)
Serial peripheral interface/On-chip audio interface (SPI/I2S) Full name and abbreviation description of terms Table 98 Full name and abbreviation description of terms Full name in English English abbreviation Most Significant Bit Least Significant Bit Master Out Slave In MOSI Master In Slave Out MISO Serial Clock Serial Data...
Page 359: Main Characteristics
Main characteristics Main characteristics of SPI Master and slave operation with 3-wire full duplex synchronous transmission and receiving Simplex synchronous transmission can be realized by two wires (the third bidirectional data line can be included/not included) Select 8-bitt or 16-bit transmission frame format Support multiple master device mode Support special transmission and receiving mark and can trigger interrupt...
Page 360: Spi Functional Description
MSB is always the first in the data direction Transmitting and receiving supports DMA function SPI functional description Description of SPI signal line Table 99 SPI Signal Line Description Pin name Description Master device: SPI clock outputs Slave device: SPI clock inputs Master device: Input the pin and receive data MISO Slave device: Output the pin and transmit data...
Page 361 SPI mode CPHA CPOL Sampling moment Idle SCK clock Even edge Low level Even edge High level Data frame format Set MSB or LSB to be first by configuring LSBSEL bit in SPI_CTRL1 register. Select to transmit/receive in 8/16-bit data frame format by configuring DFLSEL bit in SPI_CTRL1 register.
Page 362 In master mode: MOSI pin is data output, which MISO is data input TI protocol In slave mode, SPI interface supports TI protocol. It is controlled by FRFCFG bit of SPI_CTRL2 register. Both clock polarity and phase position conform to TI protocol.
Page 363 Half-duplex communication of SPI One clock line and one bidirectional data line  Enable this mode by setting BMEN of SPI_CTRL1 register  Control the data line to be input or output by setting BMOEN bit of SPI_CTRL1 register  SCK pin is used as clock, MOSI pin is used in master device to transmit data, and MISO pin is used in slave device to transmit data Data transmitting and receiving process in different SPI modes Table 101 Run Mode of SPI...
Page 364 Figure 91Connection in Half-duplex Mode (the master is used for receiving, while the slave is used for transmitting) Master device Slave device MISO MISO MOSI MOSI Figure 92 Connection in Half-duplex Mode (the master only transmits, while the slave receives) Figure 93 Bidirectional Line Connection Transmitting and receiving of processed data Data transmission...
Page 365 Slave mode: The SCK signal on the SCK pin starts to jump, while the NSS pin level is low, and the transmission process starts (before starting data transmission, make sure that the data has been written to the transmit buffer in advance).
Page 366 Full duplex transmitting and receiving process under master/slave device Enable SPI module: Configure SPIEN=1 of SPI_CTRL1 register. Write the first data to be sent to SPI_DATA register, and the TXBEFLG flag will be cleared. Wait until TXBEFLG flag bit is set to 1 (control by hardware), and write the second data bit to be sent.
Page 367 In the master device: Generate SCK clock immediately, and continuously receive data before SPI is disabled. Slave device: When SPI master device pulls down NSS and generates clock, receive data. Wait until the RXBNEFLG flag is set to 1, read data through SPI_DATA, and repeat the operation to receive data.
Page 368 Disable SPI (SPIEN=0) Clear CRCEN bit Set CRCEN bit to 1 Enable SPI (SPIEN=1) DMA function For high-speed data transmission, the request/response DMA mechanism in SPI improves the system efficiency and can transfer data to SPI transmit buffer promptly, and the receive buffer can read the data in time to prevent overflow. When SPI only transmits data, it is only needed to enable DMA transmission channel;...
Page 369 Wait until TXBEFLG flag bit is set to 1 Wait for clearing BSYFLG flag bit Close SPI (set SPIEN=0 of SPI_CTRL1 register) One-way transmit-only/bidirectional transmitting mode of master mode/slave mode After the last data is written into SPI_DATA register: Wait until TXBEFLG flag bit is set to 1 Wait for clearing BSYFLG flag bit Close SPI (set SPIEN=0 of SPI_CTRL1 register) One-way receive-only/bidirectional receiving mode of master mode/slave mode...
Page 370 SPI communication layer. When BSYFLG=1, it indicates SPI is communicating, but in the two-line receiving mode under the master device, BSYFLG=0 during the period of receiving of data. BSYFLG flag can be used to detect whether transmission is over to avoid damaging the last transmitted data.
Page 371: I2S Functional Description
OVRFLG flag can be cleared by reading SPI_DATA register and SPI_STS register according to the sequence. CRC error flag CRCEFLG By setting CRCEN bit of SPI_CTRL1 register, start CRC computing, CRC error flag, and check whether the received data is valid. When the value sent by SPI_TXCRC register does not match the value in SPI_RXCRC register, a CRC error will be generated, and CRCEFLG flag bit in SPI_STS register will be set to 1.
Page 372 I2S and SPI share four pins:  SD: Serial data, transmitting and receiving the data of 2-way time division multiplexing channel  WS: Chip selection, switching the data of left and right channels  CK: Serial clock; the clock signal is output in master mode, and is input in slave mode ...
Page 373 right channel is sent. I2S Philips standard In I2S Philips standard, the pin WS can indicate the data being sent comes from the left channel or the right channel. In I2S Philips standard, both WS and SD change on the falling edge of CK clock signal.
Page 374  The data to be received or sent is 0x62d8, which becomes 0x62D80000 after it is expanded to 32 bits, and it is necessary to write 0x62D8 to SPI_DATA register or read out from SPI_DATA register. Figure 96 I2S Philips Protocol Waveform (extending from 16 bits to 32 bits) SPI_CK SPI_WS 16-bit data...
Page 375 Figure 98 MSB Alignment Standard Waveform (24-bit data) SPI_CK SPI_WS 24-bit data The remaining 8 bits are forced to 0 High SPI_SD Right channel Left channel Figure 99 MSB Alignment Standard Waveform (extending from 16 bits to 32 bits) SPI_CK SPI_WS 16-bit data The remaining 16...
Page 376 Figure 101 LSB Alignment Standard Waveform (24-bit data) SPI_CK SPI_WS 8-bit data is forced 24-bit data to 0 High SPI_SD Right channel Left channel In the transmission process, if you want to transmit/receive 24-bit data, it is required to read/write the SPI_DATA register twice; for example: ...
Page 377 structure is 13 bits. Figure 103 PCM Standard Waveform SPI_CK SPI_WS 13-bit data Long frame 16-bit data High High SPI_SD In the master mode, the length of the synchronous WS signal of the short frame structure is 1 bit. Figure 104 PCM Standard Waveform SPI_CK SPI_WS Short...
Page 378 MCOEN CHLEN Audio sampling frequency (Fs) I2SxCLK/[（16*2）*（（2*I2SPSC）+ODDPSC）] I2SxCLK/[（32*2）*（（2*I2SPSC）+ODDPSC）] I2S mode I2S can be configured as follows: Transmit master or receive master of I2Sx is used in half-duplex mode Master that receives and transmits concurrently in full-duplex mode Table 104 I2S Run Mode Run mode Master Output...
Page 379 I2S master mode transmission process When the data is written to the transmit buffer, the transmission will start, and the data will be transferred from the transmit buffer to the shift register, the TXBEFLG flag position is set to 1, and the SCHDIR flag bit indicates the corresponding sound channel of the currently transmitted data.
Page 380  Wail for one I2S clock cycle (software delay)  I2SEN=0 All the other situations  Wait until the penultimate RXBNEFLG is set to 1  Wail for one I2S clock cycle (software delay)  I2SEN=0 BSYFLG flag clock is low during data transmission. I2S slave mode The configuration method of slave mode is basically the same as that of master mode.
Page 381 I2S can be disabled only when TXBEFLG flag bit is set to 1 and BSYFLG flag bit is cleared to 0. I2S slave mode receiving process RXBNEFLG bit is used to control the receiving sequence. The RXBNEFLG bit indicates whether the receive buffer is empty; after the receive buffer is full, the RXBNEFLG bit will be set to 1;...
Page 382 cleared. During continuous communication:  In the master transmitting mode, the BSYFLG flag bit is always high during the transmission period  In the slave mode, during transmission of each data item, the BSYFLG flag bit is set to 0 within one I2S clock cycle Channel flag bit SCHDIR In the transmitting mode, the SCHDIR flag bit indicates the data sent on the SD pin is in the left channel or the right channel.
Page 383: Register Address Mapping
Read SPI_DATA register to return the last correctly received data, and all the other newly received data will be lost. OVRFLG bit can be cleared by first reading SPI_STS register and then reading SPI_DATA register. Frame error flag FREFLG When I2S is configured as slave mode, this flag will be set to 1 by hardware. If the external maser arbitrarily changes the WS signal, this flag will be set to 1.
Page 384: Register Functional Description
Register name Description Offset address SPI_TXCRC SPI transmit CRC register 0x18 SPI_I2SCFG SPI I2S configuration register 0x1C SPI_I2SPSC SPI I2S prescaler register 0x20 Register functional description These peripheral registers can be operated by half word (16 bits) or word (32 bits).
Page 385 Field Name Description LSB First Transfer Select LSBSEL 0: First transmit the most significant bit (MSB) 1: First transmit the least significant bit (LSB) Internal Slave Device Select When CTRL1_SSEN=1 (software NSS mode), select internal NSS level by configuring the bit ISSEL 0: Internal NSS is low 1: Internal NSS is high...
Page 386 SPI control register 2 (SPI_CTRL2) Offset address: 0x04 Reset value: 0x0000 Field Name Description Receive Buffer DMA Enable When RXDEN=1, once RXBNEFLG flag is set, DMA request will be issued. RXDEN 0: Disable 1: Enable Transmit Buffer DMA Enable When this bit is set, once TXBEFLG flag is set, DMA request will be issued.
Page 387 Field Name Description Receive Buffer Not Empty Flag RXBNEFLG 0: Empty 1: Not empty Transmit Buffer Empty Flag TXBEFLG 0: Not empty 1: Empty Sound Channel Direction Flag 0: Indicate that the left channel is transmitting or receiving the required data SCHDIR 1: Indicate that the right channel is transmitting or receiving the required data...
Page 388 SPI data register (SPI_DATA) (not used in I2S mode) Offset address: 0x0C Reset value: 0x0000 Field Name Description Transmit Receive Data register When writing this register, the data will be written to the transmit buffer; when reading this register, the data in receive buffer will be read. 15:0 DATA The size of the buffer is consistent with the length of the data frame, that...
Page 389 SPI_I2S configuration register (SPI_I2SCFG) Offset address: 0x1C Reset value: 0x0000 Field Name Description Channel Length Configure The channel length refers to the data bits per audio channel 0: 16-bit width 1: 32-bit width CHLEN The vocal tract length can be configured successfully only when the vocal tract length is greater than the data length;...
Page 390 Field Name Description SPI/I2S Mode Select 0: Select SPI mode MODESEL 1: Select I2S mode Note: This bit can be set only when SPI or I2S is disabled. 15:12 Reserved SPI_I2S prescaler register (SPI_I2SPSC) (not used in SPI mode) Offset address: 0x20 Reset value: 0x0002 Field Name...
Page 391: Controller Area Network (Can)
Controller area network (CAN) Full name and abbreviation description of terms Table 107 Full name and abbreviation description of terms Full name in English English abbreviation First Input First Output FIFO Request Introduction CAN is abbreviation of Controller Area Network, and is serial communication protocol of ISO international standardization and supports CAN Protocol 2.0A and 2.0B.
Page 392 Message structure Figure 105 Standard Data Frame Frame Arbitration field Control field Data field CRC field ACK field End of frame start Figure 106 Extended Data Frame Frame Arbitration field Arbitration field Control field Data field CRC field ACK field End of frame start Note:...
Page 393 initialization mode. Message receiving and transmitting is disabled in initialization mode. Normal mode Clear the INITREQ bit of the configuration register CAN_MCTRL through software to request to enter the normal mode from the initialization mode; wait for the hardware to clear the INITFLG bit to enter the normal mode. Message receiving and transmitting is allowed in normal mode.
Page 394 In this mode, the sent data are directly transmitted to the input end for receiving, the data are not received from the bus, and all data can be sent to the bus. Figure 108 CAN Works in Loopback Mode CANTX CANRX Loopback silent mode Set the LBKMEN and SILMEN bits of the configuration register CAN_BITTIM to...
Page 395 Figure 110 CAN Works in Normal Mode CANTX CANRX Data transmission Conversion of transmiting mailbox state Conversion process of transmiting mailbox state: First select an empty mailbox to set, submit the transmitting request to the CAN bus controller by setting the TXMREQ bit of the configuration register CAN_TXMIDx to 1, and then the mailbox immediately enters the registration state.
Page 396 by hardware; the other is that the mailbox fails to transmit, the mailbox becomes predetermined and the transmitting request is aborted. Automatic retransmission is disabled Generally, in time triggered communication mode, automatic retransmission should be disabled. In the mode that the automatic retransmission is disabled, the message is sent only once, and no matter what the result is (success, error or arbitration loss), the hardware will not transmit the message again automatically.
Page 397 Figure 111 One 32-bit Filter Figure 112 Two 16-bit Filters Filtering mode Mask bit mode In this mode, it is only required to use some bits of the message identifier as a list to form the mask, and the message ID should be the same as the mask, and then the message can be received Table 108 Mask Bit Mode Example …….
Page 398 Bit timing and baud rate Bit timing The CAN peripheral bit timing of APM32 contains three segments: synchronization segment (SYNC_SEG), time segment 1 (BS1) and time segment 2 (BS2), and the sampling points are at the junction of BS1 and BS2 segments.
Page 399 Interrupt Events generating transmitting interrupt:  The hardware sets REQCFLG0 bit of the register CAN_TXSTS to 1, and the transmiting mailbox 0 becomes idle  The hardware sets REQCFLG1 bit of the register CAN_TXSTS to 1, and the transmiting mailbox 1 becomes idle ...
Page 400: Register Address Mapping
Figure 113 Event Flag and Interrupt Generation CAN_INTEN Transmit REQCFLG0 TXMEIEN interrupt CAN_TXSTS REQCFLG1 REQCFLG2 FMIEN0 FMNUM0 FIFO 0 Interrupt FFULLIEN0 CAN_RXF0 FFULLFLG0 FOVRIEN0 FOVRFLG0 FMPIEN1 FMNUM1 FIFO 1 Interrupt FFULLIEN1 FFULLFLG1 CAN_RXF1 FOVRIEN1 FOVRFLG1 ERRIEN ERRWIEN ERRWFLG ERRPIEN ERRPFLG CAN_ERRSTS BOFFIEN BOFLG...
Page 401: Register Functional Description
Table 110 CAN Register Address Mapping Register name Description Offset address CAN_MCTRL CAN main control register 0x00 CAN_MSTS CAN main state register 0x04 CAN_TXSTS CAN transmit state register 0x08 CAN_RXF0 CAN receive FIFO 0 register 0x0C CAN_RXF1 CAN receive FIFO 1 register 0x10 CAN_INTEN CAN interrupt enable register...
Page 402 Field Name Description Request to Enter Sleep Mode 0: Exit the sleep mode 1: Request to enter the sleep mode. SLEEPREQ If the AWUPCFG bit is set to 1, when the RX signal detects CAN message, this bit will be cleared by hardware; after reset, reset this bit to 1;...
Page 403 Reset value: 0x0000 0C02 Field Name Description Being Initialization Mode Flag This bit is set to 1 or cleared by hardware. INITFLG 1: Exit the initialization mode 1: Being in the initialization mode; this bit is confirmation for initialization request bit of the CAN_MCTRL register. Being Sleep Mode Flag This bit is set to 1 or cleared by hardware SLEEPFLG...
Page 404 Field Name Description Mailbox 0 Request Completed Flag When the last transmission or abortion request of the mailbox 0 is completed, this bit is set to 1 by hardware; when receiving the transmission request, this bit is cleared by hardware; it is written REQCFLG0 RC_W1 to 1 or cleared by software.
Page 405 Field Name Description Mailbox 1 Transmission Error Flag When mailbox 1 fails to transmit, this bit is set to 1 by hardware; and written to 1 and cleared by software. TXERRFLG1 RC_W1 0: Meaningless 1: Failed to transmit 14:12 Reserved Mailbox 1 Abort Request Flag If there is no message waiting for transmitting in mailbox 1, this bit is ineffective.
Page 406 Field Name Description Transmit Mailbox 0 Empty Flag When the Transmiting mailbox 0 is empty, this bit is set to 1 by hardware. TXMEFLG0 0: There is message to be sent in mailbox 0 1: There is no message to be sent in mailbox 0 Transmit Mailbox 1 Empty Flag When the Transmiting mailbox 1 is empty, this bit is set to 1 by hardware.
Page 407 Field Name Description Receive FIFO 0 Overrun Flag When there are three messages in FIFO0 and then a new message is received, it means the FIFO0 overrun; this bit is set to 1 by FOVRFLG0 RC_W1 hardware and written to 1 and cleared by software. 0: No overrun 1: Overrun is generated Release Receive FIFO0 Output Mailbox to Receive Massage...
Page 408 CAN interrupt enable register (CAN_INTEN) Offset address: 0x14 Reset value: 0x0000 0000 Field Name Description Transmit Mailbox Empty Interrupt Enable When REQCFLGx bit is set to 1, it means transmission has been completed, and the transmiting mailbox is empty; if this bit is set to 1, TXMEIEN an interrupt will be generated.
Page 409 Field Name Description Error Warning Interrupt Enable When ERRWFLG bit is set to 1, an error warning will occur; if this bit is set to 1, ERRIFLG shall be set and a warning error interrupt will be ERRWIEN generated. 0: ERRIFLG bit is not set 1: ERRIFLG bit is set to 1 Error Passive Interrupt Enable When ERRPFLG bit is set to 1, a pssive error will occur;...
Page 410 Field Name Description Error Warning Occur Flag When the value of the receiving error counter or transmitting error counter ≥96, this bit is set to 1 by hardware. ERRWFLG 0: No error warning 1: Error warning occurred Error Passive Occur Flag When the value of the receiving error counter or transmitting error counter ≥127, this bit is set to 1 by hardware.
Page 411 Field Name Description 15:10 Reserved Set the time segment 1 (Time Segment 1 Setup) 19:16 TIMSEG1 Time occupied by time period 1 tBS1 = tCAN x (TIMSEG1+1). Set the time segment 2 (Time Segment 2 Setup) 22:20 TIMSEG2 Time occupied by time period 2 tBS2 = tCAN x (TIMSEG2+1). Reserved Resynchronization Jump Width 25:24...
Page 412 Field Name Description Identifier Type Select IDTYPESEL 0: Stanard identifier 1: Extended identifier Extended Identifier Setup 20:3 EXTID[17:0] Low byte of extended identity label. Standard Identifier Or Extended Identifier According to the content of IDTYPESEL bit, these bits are 31:21 STDID[10:0]/EXTID[28:18] standard identifier...
Page 413 Receive FIFO mailbox identifier register (CAN_RXMIDx) (x=0..1) Offset address: 0x1B0, 0x1C0 Reset value: 0xXXXX XXXX, X=undefined bit Field Name Description Reserved Remote Frame Transmission Request RFTXREQ 0: Data frame 1: Remote frame Identifier Type Select IDTYPESEL 0: Stanard identifier 1: Extended identifier Extended Identifier Setup 20:3 EXTID[17:0]...
Page 414 Receive FIFO mailbox high-byte data register (CAN_RXMDHx) (x=0..1) Offset address: 0x1BC, 0x1CC Reset value: 0xXXXX XXXX, X=undefined bit Field Name Description DATABYTE4 Data Byte 4 of the Message 15:8 DATABYTE5 Data Byte 5 of the Message 23:16 DATABYTE6 Data byte 6 of the Message 31:24 DATABYTE7 Data byte 7 of the Message...
Page 415 Field Name Description Filterx Scale Configure The value of x is within 0-27. 27:0 FSCFGx 0: Two 16 bits 1: Single 32 bits 31:28 Reserved Note: Only when CAN_FCTRL (FINITEN =1) is set to make the filter in initialization mode, can this register be written.
Page 416 Field Name Description Configure Filter15 Associated with FIFO FFASS15 Refer to FFASS0 for specific description. Configure Filter16 Associated with FIFO FFASS16 Refer to FFASS0 for specific description. Configure Filter17 Associated with FIFO FFASS17 Refer to FFASS0 for specific description. Configure Filter18 Associated with FIFO FFASS18 Refer to FFASS0 for specific description.
Page 417 Field Name Description Filter4 Active FACT4 Refer to FACT0 for specific description. Filter5 Active FACT5 Refer to FACT0 for specific description. Filte6 Active FACT6 Refer to FACT0 for specific description. Filter7 Active FACT7 Refer to FACT0 for specific description. Filter8 Active FACT8 Refer to FACT0 for specific description.
Page 418 Field Name Description Filter26 Active FACT26 Refer to FACT0 for specific description. Filter27 Active FACT27 Refer to FACT0 for specific description. 31:28 Reserved Register x of CAN filter group i (CAN_FiBANKx) (i＝0..27；x=1..2) Offset address: 0x240..0x31C CAN_F0BANK1 offset address: 0x240 CAN_F0BANK2 offset address: 0x244 CAN_F1BANK1 offset address: 0x248 CAN_F1BANK2 offset address: 0x24C...
Page 419: Secure Digital Input/Output Interface (Sdio)
Secure digital input/output interface (SDIO) Full name and abbreviation description of terms Table 111 Full name and abbreviation description of terms Full name in English English abbreviation First Input First Output FIFO Command Path State Machine CPSM Data Path State Machine DPSM Introduction The secure digital input/output interface can connect SD card, SD I/O card,...
Page 420 the clock signal, the data unit manages the data transmission, and the command unit manages the command transmission. APB2 bus interface: Operate the registers in SDIO adapter, used for FIFO unit for data transmission, generate an interrupt and DMA request signal. Figure 114 SDIO Structure Block Diagram SDIO Interrupt...
Page 421  Data: It can be transmitted from the master to the card or from the card to the master. Transmit through data cable. The number of data cables for data transmission can be 1 (D0), 4 (D0-D3), or 8 (D0-D7). The basic operation on the multimedia card/SD/SD I/O bus is command/response structure.
Page 422 Figure 117 SDIO (Multi-) Data Block Write Operation Command Response Response Command From host to device Data block Data block From host to From host to device device Single-block write operation Multi-block write operation Data stop operation : Busy Figure 118 SDIO Data Flow Read Operation From host to From host to From device to...
Page 423  SDIO_CLK: Clock provided by SDIO controller to the card. Each clock cycle directly transmits 1-bit command or data on the command line (SDIO_ CMD) and all data lines (SDIO)_ D). SDIO_ CLK frequency is within 0-20MHz for MMC card V3.31, within 0-48MHz for MMC card V4.2, and within 0-25MHz for SD or SD I/O card.
Page 424 Data unit The data unit realizes the data transmission between the master and the card. When the data width is 8 bits, SDIO_D[7:0] signal line is used for data transmission. When the data width is 4 bits, SDIO_D[3:0] signal line is used for data transmission.
Page 425 DS_WaitR waits for the start bit of received data 1. Data receiving ends DS_Idle 2. DPSM is turned off DS_Idle 3. Data timeout DS_Idle 4. Receive the start bit before timeout DS_Receive DS_Receive receives the card data and writes them to data FIFO 1.
Page 426 APB2 interface APB2 interface realizes access to SDIO register, data FIFO and generation of interrupt and DMA request. It includes data FIFO unit, register unit and interrupt/DMA request control logic. SDIO interrupt When at least one of the selected state flags is high, the interrupt logic will generate an interrupt request.
Page 427 MMC and SD card. The master can use CMD1 (MMC), ACMD41 (SD memory card), and CMD5 (SD I/O) to capture the content of this register. CID register: The card identification register (CID) is 128-bit wide. It contains the card identification information used in the card identification phase. Each read/write (RW) card shall have a unique identification number.
Page 428 Table 114 Command Format [45:40] [39:8] [7:1] Width Numerical Value Description Start Bit Transmission Bit Command Index Parameter CRC7 End bit SD I/O supports two types of response, both of which support CRC error detection.  48-bit short response  136-bit long response Table 115 Short Response Format [45:40] [39:8]...
Page 429 Command Response Short Type Parameter Description Index format name SEND_REL Request the card to [31:0] CMD3 ATIVE_AD release new relative Stuffing bit card address (RCA) 31:16]DSR Set DSR registers of all CMD4 [15:0]Stuffin SET_DSR cards. g bit [31:25]Reser ved bit Only apply to I/O card.
Page 430 Command Response Short Type Parameter Description Index format name STOP_TRA [31:0] Force the card to stop CMD12 NSMISSIO Stuffing bit transmission. [31:16]RCA The selected card SEND_STA CMD13 [15:0]Stuffin transmits its state g bit register. The master reads the [31:0] BUSTEST_ CMD14 adtc reverse bus test data...
Page 431 Comman Response Type Parameter Short name Description d Index format [31:0] Stuffing PROGAM_C Program the programmable bits CMD27 adtc in the card CSD. If the card has write protection function, this command will set the write protection bit of the [31:0]Data SET_WRITE CMD28...
Page 432 In the read wait state, after 2 SDIO_CK clock cycles, DPSM drive SDIO_ D2 is 0. In this state, if RWSTOP bit is set, DPSM will stay for 2 more SDIO_CK clock cycles in the waiting state, and (according to SDIO specification) the drive SDIO_D2 is 1 in one clock cycle.
Page 433 SDIO supports these operations only when SDIO_CMD ATACMD bit is set. Command completion signal CE-ATA defines the command completion signal. The device uses this signal to notify the master that the ATA command is completed or encounters an error, and ATA command is terminated Command completion and closing signal The master can transmit a command to complete the function of closing the signal and canceling the device return command to complete the signal.
Page 434 Numerical Clear Name Type Description Value conditions Reserved for the command related to application. 0=No error AKE_SEQ_ERROR Verification sequence error. 1=Error Reserved for SD I/O card The card expects ACMD, or 0=Not allowed the instruction command APP_CMD 1=Allowed has been interpreted as an ACMD command.
Page 435 Numerical Clear Name Type Description Value conditions Encounter existing write 0=Not protection data block, and WP_ERASE_SKIP protected only part of address space 1=Protected is erased. It can be any of the following errors: It has been written into the CID register and cannot be overridden CID/CSD_OVERW 0=No error...
Page 436 Numerical Clear Name Type Description Value conditions 0=Card When this bit is set, it CARD_IS_LOCKED unlocked means the card has been 1=Card locked locked. 0=No error Attempt to program the data WP_VIOLATION 1=Error block of a write protection. 0=No error Illegal erase group selected ERASE_PARAM 1=Error...
Page 437 Numerical Clear Name Type Description Value conditions The address parameter in the command is beyond the allowed range of the card. A multi-data block or data ADDRESS_OUT_O 0=No error stream read/write operation F_RANGE 1=Error (even starting from a legal address) attempts to read or write the part beyond the capacity of the card.
Page 438 Clear Name Type Numerical Value Description conditio 399:312 Reserved ERASE_OFF 401:400 ERASE_TIME Fixed offset value (See the 407:402 added in erase instructions below) Erase the timeout value (See the 423:408 ERASE_SIZE of specified range of instructions below) UNIT_OF_ERASE_AU The number of AU that (See the 427:424 Reserved...
Page 439 Clear Name Type Numerical Value Description conditio The card is in secret 0=Not in the secret operation mode SECURED_M mode (see "SD 1=In the secret mode Confidentiality Specification"). 00=1 (default) Current data bus DAT_BUS_WI 01-Reserve width defined by 511:510 10=4-bit width SET_BUS_WIDTH 11=Reserved command.
Page 440 great. Setting this field for FFH means infinitely great. Table 126 Mobility Perfromance Code PERFORMANCE_MOVE Definition of Numerical Value Undefined 1MB/s 2MB/s …… …… 254MB/s Infinitely great AU_SIZE These four bits indicate the length of AU, and the value is the multiple of the power of 2 in 16KB.
Page 441 ERASE_SIZE This 16-bit field gives the value of NERASE, and when MERASE number of AU is erased, ERASE_TIMEOUT defines the timeout period. If the master can determine the value of NERASE in a certain erase, the erase progress can be displayed. Table 129 ERASE_SIZE Codes ERASE_SIZE Definition of Numerical Value...
Page 442: Register Address Mapping
Register address mapping Table 132 SDIO Register Address Mapping Register name Description Offset address SDIO_PWRCTRL SDIO power control register 0x00 SDIO_CLKCTRL SDIO clock control register 0x04 SDIO_ARG SDIO parameter register 0x08 SDIO_CMD SDIO command register 0x0C SDIO_CMDRES SDIO command response register 0x10 SDIO_RESx SDIO response x register...
Page 443 SDIO clock control register (SDIO_CLKCTRL) Offset address: 0x04 Reset value: 0x0000 0000 SDIO_CLKCTRL register controls SDIO_CLK to output the clock. Field Name Description Clock Divide Factor This domain defines the division factor between input clock (SDIOCLK) CLKDIV and output clock (SDIO_CLK): SDIO_CLK frequency=SDIOCLK/[CLKDIV + 2].
Page 444 This register cannot be written within 7 HCLK clock cycles after writing data. For SD I/O card, SDIO_CLK can be stopped during read wait period, and then SDIO_CLKCTRL register does not control SDIO_CLK. SDIO parameter register (SDIO_ARG) Offset address: 0x08 Reset value: 0x0000 0000 Command parameters are also part of the command, and SDIO_ARG register contains 32-bit command parameters and is sent to the card together with the...
Page 445 Field Name Description Enable CMD Completion Enable command completion signal. CMDCPEN 0: Disable 1: Enable Interrupt Enable 0: Enable INTEN 1: Disable CE-ATA Command 0: Invalid ATACMD 1: Switch CPSM to CMD61 31:15 Reserved Note: This register cannot be written within 7 HCLK clock cycles after writing data. The multimedia card can transmit two kinds of responses: 48-bit short response or 136-bit long response.
Page 446 Always receive the most significant bit of card state first, and the lowest bit of SDIO_RES3 register is always 0. SDIO data timer register (SDIO_DATATIME) Offset address: 0x24 Reset value: 0x0000 0000 Field Name Description Data Timeout Period 31:0 DATATIME Record the data timeout period in card bus clock cycle.
Page 447 Field Name Description 0100: Block length=24=16 bytes 0101: Block length=25=32 bytes 0110: Block length=26=64 bytes 0111: Block length=27=128 bytes 1000: Block length=28=256 bytes 1001: Block length=29=512 bytes 1010: Block length=210=1024 bytes 1011: Block length=211=2048 bytes 1100: Block length=212=4096 bytes 1101: Block length=213=8192 bytes 1110: Block length=214=16384 bytes 1111: Reserved Read Wait Start...
Page 448 (1) Static flag (bit [23:22, 10:0]): Write SDIO interrupt clear register to clear these bits. (2) Dynamtic flag (bits [21:11]: The state of these bits changes according to the logic of corresponding part. Field Name Description COMRESP Command Response Received (CRC detection failure) DBDR Data Block Sent/Received (CRC detection failure) Command Response Timeout...
Page 449 SDIO clear interrupt register (SDIO_ICF) Offset address: 0x38 Reset value: 0x0000 0000 SDIO_ICF is a write-only register, and the corresponding bit in SDIO_STS state register will be cleared in corresponding register bit. Field Name Description DBCE Flag Clear Clear DBCE flag. DBCE 0: Invalid 1: Clear...
Page 450 Field Name Description DBCP Flag Clear Clear DBCP flag. DBCP 0: Invalid 1: Clear 21:11 Reserved SDIOIT flag clear bit Clear SDIOIT flag. SDIOIT 0: Invalid 1: Clear ATAEND flag clear bit Clear ATAEND flag. ATAEND 0: Invalid 1: Clear 31:24 Reserved SDIO interrupt mask register (SDIO_MASK)
Page 451 Field Name Description Rx FIFO Overrun Error Interrupt Enable Enable/Disable receive FIFO overrun error interrupt. RXORER 0: Disable 1: Enable Command Response Received Interrupt Enable Enable/Disable receiving response interrupt. CMDRESRC 0: Disable 1: Enable Command Sent Interrupt Enable Enable/Disable command sent interrupt since the software has set/cleared this bit.
Page 452 Field Name Description Tx FIFO Full Interrupt Enable Enable/Disable transmit FIFO full interrupt. TXFUL 0: Disable 1: Enable Rx FIFO Full Interrupt Enable Enable/Disable receive FIFO full interrupt. RXFUL 0: Disable 1: Enable Tx FIFO Empty Interrupt Enable Enable/Disable transmit FIFO empty interrupt. TXEPT 0: Disable 1: Enable...
Page 453 SDIO data FIFO register (SDIO_FIFODATA) Offset address: 0x80 Reset value: 0x0000 0000 Field Name Description Receive And Transmit FIFO Data 31:0 DATA Data to be written into FIFO or read out from FIFO. www.geehy.com Page 452...
Page 454: Usb_Otg
USB_OTG Introduction This chip is embedded with three USB controllers in total. OTG_FS OTG_FS can support both host and slave functions to comply with the On-The- Go supplementary standard of USB 2.0 specification, and can also be configured as " Host only" or "Slave only" mode, to fully comply with USB 2.0 specification, and support host negotiation protocol (HNP) and session request protocol (SRP).
Page 455: Otg_Fs Global Register Functional Description
Offset Register name Description address OTG_FS_GRSTCTRL Full-speed OTG reset control register 0x10 OTG_FS_GCINT Full-speed OTG module interrupt register 0x14 OTG_FS_GINTMASK Full-speed OTG module interrupt mask register 0x18 OTG_FS_GRXSTS Full-speed OTG read debug receive state register 0x1C OTG_FS_GRXSTSP Full-speed OTG state read and pop register 0x20 OTG_FS_GRXFIFO Full-speed OTG receive FIFO size register...
Page 456 Field Name Description Note: It can be used only in device mode Reserved Host Negotiation Success This bit will be cleared to 0 when HNPREQ of this register is set to 1 HNSUC 0: Host negotiation fails 1: Host negotiation succeeds Note: It can be used only in device mode Host Negotiation Protocol Request (HNP Request) 0: Not transmit HNP request...
Page 457 Full-speed OTG interrupt register (OTG_FS_GINT) Offset address: 0x04 Reset value: 0x0000 0000 Field Name Description Reserved Session End Flag SEFLG RC_W1 When V <0.8V, it means that V is not used for B-session, and this bit will be set to 1. Reserved Session Request Success Bit Change SREQSUCCHG...
Page 458 Field Name Description Periodic TXFIFO Empty Level 0: PTXFE interrupt means that periodic TXFIFIO is half-empty PTXFEL 1: PTXFE interrupt means that periodic TXFIFIO is all-empty Note: It can be accessed only in master mode 31:9 Reserved Full-speed OTG USB configuration register (OTG_FS_GUSBCFG) Offset address: 0x0C Reset value: 0x0000 0A00 Field...
Page 459 Full-speed OTG reset register (OTG_FS_GRSTCTRL) Offset address: 0x10 Reset value: 0x2000 0000 Field Name Description Core Soft Reset This bit controls HCLK and PCLK reset Clear each interrupt and all control state register bits to 0 except the followings: - GCLK bit in OTG_FS_PCGCTRL - PCLKSTOP bit in OTG_FS_PCGCTRL - PHYCLKSEL bit in OTG_FS_HCFG - DSPDSEL bit in OTG_FS_DCFG...
Page 460 Field Name Description 00001: Refresh periodic TXFIFO 10000: Refresh all TXFIFO In device mode: 00000: Refresh TXFIFO 0 00001: Refresh TXFIFO 1 …… 00101: Refresh TXFIFO 15 10000: Refresh all TXFIFO 30:11 Reserved AHB Master Idle AHBMIDL This bit indicates whether the AHB master device is idle. Full-speed OTG module interrupt register (OTG_FS_GCINT) Offset address: 0x14 Reset value: 0x0400 0020...
Page 461 Field Name Description Global IN Non-periodic NAK Effective Interrupt This bit indicates that GINAKSET bit of OTG_FS_DCTRL register is valid; this bit can be cleared by clearing GINAKCLR bit of OTG_FS_DCTRL register. GINNPNAKE As the priority of STALL is higher than that of NAK bit, generation of this interrupt cannot mean that USB has sent NAK signal.
Page 462 Field Name Description OUT Endpoint Interrupt This bit will be set to 1 when a pending interrupt occurs to one OUT endpoint Determine the number of OUT endpoint to which an interrupt ONEP occurs by reading OTG_FS_DAEPINT register, and determine the causes of the interrupt by reading OTG_FS_DOEPINTx register.
Page 463 Field Name Description Session Request/New Session Interrupt In different modes, the conditions for triggering this interrupt are: SREQ RC_W1  Session request is detected in master mode  In device mode, V is within the range of B-device Resume/Remote Wakeup Interrupt In different modes, the conditions for triggering this interrupt are: RWAKE RC_W1...
Page 464 Field Name Description 1: Not mask Note: It can be accessed only in device mode USB Suspend Interrupt Mask 0: Mask USBSUSM 1: Not mask Note: It can be accessed only in device mode USB Reset Interrupt Mask 0: Mask USBRSTM 1: Not mask Note: It can be accessed only in device mode...
Page 465 Field Name Description 23:22 Reserved Host Port Interrupt Mask 0: Mask HPORTM 1: Not mask Note: It can be accessed only in master mode Host Channels Interrupt Mask 0: Mask HCHM 1: Not mask Note: It can be accessed only in master mode Periodic TXFIFO Empty Interrupt Mask 0: Mask PTXFEM...
Page 466 Field Name Description Data Packet ID This bit indicates the received data packet ID (PID) 00：DATA0 16:15 DPID 10：DATA1 01：DATA2 11：MDATA Packet Status This bit indicates the status of the received data packet. 0010: Received IN data packet 20:17 PSTS 0011: IN transmission completed 0101: Data synchronization error 0111: Channel stop...
Page 467 Field Name Description RXFIFO Depth 15:0 RXFDEP RXFIFO is in word, and the depth range is: 16~256. 31:16 Reserved Full-speed OTG TXFIFO configuration register (OTG_FS_GTXFCFG) Offset address: 0x28 Reset value: 0x0000 0200 Master mode Field Name Description Nonperiodic TXFIFO RAM Start Address 15:0 NPTXSA This bit indicates the start address of non-periodic TXFIFO RAM.
Page 468 Field Name Description ….. 0xn: n positions are available (0≤n≤8) Others: Reserved Nonperiodic Transmit Request Queue Bit 24: Terminate (last data selected for channel/endpoint) Bit [26:25]: 00: IN/OUT token 30:24 NPTXRQ 01: The transmit data packet length is 0 (IN in device mode/OUT in master mode) 10: PING/CPLIT token 11: Stop channel instruction...
Page 469: Otg_Fs Host Mode Register Address Mapping
Field Name Description Product ID 31:0 Product ID can be programmed by this bit. Full-speed OTG host periodic TXFIFO size register (OTG_FS_GHPTXFSIZE) Offset address: 0x100 Reset value: 0x0200 0600 Field Name Description 15:0 HPDTXFSA Host Periodic TXFIFO Start Address Host Periodic TXFIFO Depth 31:16 HPDTXFDEP TXFIFO is in word, and the minimum value is 16.
Page 470: Otg_Fs Host Mode Register Functional Description
Register name Description Offset address Full-speed OTG host channel-X interrupt mask OTG_FS_HCHIMASKX 0x50C+20*X register (X=0…7) Full-speed OTG host channel-X transmission size OTG_FS_HCHTSIZEX 0x510+20*X register (X=0…7) OTG_FS host mode register functional description Full-speed OTG host configuration register (OTG_FS_HCFG) Offset address: 0x400 Reset value: 0x0000 0000 Field Name...
Page 471 Full-speed OTG host frrame information register (OTG_FS_HFIFM) Offset address: 0x408 Reset value: 0x0000 3FFF Field Name Description Frame Number 15:0 FNUM This bit is used to indicate the current frame number. This bit will be cleared to zero when reaching 0x3FFF. Frame Remaining Time This bit is used to indicate the current remaining time of frame.
Page 472 Full-speed OTG host all-channel interrupt register (OTG_FS_HACHINT) Offset address: 0x414 Reset value: 0x0000 0000 Field Name Description All Channels Interrupts 15:0 ACHINT No. X bit represents interrupt of Channel X. Up 16 channels. 31:16 Reserved Full-speed OTG host all-channel interrupt mask register (OTG_FS_HACHIMASK) Offset address: 0x418 Reset value: 0x0000 0000...
Page 473 Field Name Description Port Resume 0: Resume signal is not driven 1: Resume signal is driven Port Suspend PSUS 0: Port is not suspended 1: Port is suspended Port Reset The prot can start reset only when this bit is set to 1 for over 10ms.
Page 474 Field Name Description This bit indicates the number of the device endpoint connected to the host. Endpoint Direction EDPDRT 0：OUT 1：IN Reserved Low-speed Device LSDV This bit indicates the low-seed device is connected. Endpoint Type This bit is used to select the transmission type of endpoint. 00: Control 19:18 EDPTYP...
Page 475 Field Name Description RXSTALL RC_W1 STALL Response Received Interrupt RXNAK RC_W1 NAK Response Received Interrupt RXTXACK RC_W1 ACK Response Received/Transmitted Interrupt Reserved Transaction Error Indicate that one of the following error occurs: CRC failure TERR RC_W1 Timeout Bit stuffing error EOP error BABBLE RC_W1...
Page 476: Otg_Fs Device Mode Register Address Mapping
Field Name Description Transaction Error Mask TERRM 0: Mask 1: Not mask Babble Error Mask BABBLEM 0: Mask 1: Not mask Frame Overrun Error Mask FOVRM 0: Mask 1: Not mask Data Toggle Error Mask DTOGM 0: Mask 1: Not mask 31:11 Reserved Full-speed OTG host channel-X transmission size register...
Page 477: Otg_Fs Device Mode Register Functional Description
Register name Description Offset address OTG_FS_DCTRL Full-speed OTG device control register 0x804 OTG_FS_DSTS Full-speed OTG device state register 0x808 Full-speed OTG device IN endpoint interrupt mask OTG_FS_DINIMASK 0x810 register Full-speed OTG device OUT endpoint interrupt mask OTG_FS_DOUTIMASK 0x814 register OTG_FS_DAEPINT Full-speed OTG device all-endpoint interrupt register 0x818 Full-speed OTG device all-endpoint interrupt mask...
Page 478 Field Name Description Device Speed Select This bit selects the maximum enumeration speed of the device connected to the host, DSPDSEL 11：FS（48MHz） Others: Reserved Transmit the Received OUT Packet on Nonzero-length Status 0: After receiving the OUT data packet, transmit the data packet to the application program, and reply the handshake signal according SENDOUT to the NAK and STALL bits of the endpoint...
Page 479 Field Name Description Global OUT NAK Status 0: Transmit the handshake signal according to FIFO state and NAK GONAKSTS and STALL bit state 1: No data is received, and all data packets except the SETUP transaction reply the NAK signal Test Mode Select 000: Disable the test 001：Test_J...
Page 480 Field Name Description Erratic Error If any irregular error occurs, this bit will be set to 1. At this time, ERTERR communication can be resumed only by performing soft disconnection. Reserved 21:8 SOFNUM Frame Number of the Received SOF 31:22 Reserved Full-speed OTG device IN endpoint interrupt mask register (OTG_FS_DINIMASK)
Page 481 Field Name Description Endpoint Disable Interrupt Mask EPDISM 0: Mask 1: Not mask Reserved SETUP Phase Complete Mask SETPCMPM 0: Mask 1: Not mask OUT Token Received when Endpoint Disabled Mask OTXEMPM 0: Mask 1: Not mask 31:5 Reserved Full-speed OTG device all-endpoint interrupt register (OTG_FS_DAEPINT) Offset address: 0x818 Reset value: 0x0000 0000...
Page 482 Field Name Description Device V Discharge Time 15:0 VBUSDTIM Discharge time after V impulses during SRP period. Value=Discharge time (number of PHY clock)/1024 31:16 Reserved Full-speed OTG device V pulse time register (OTG_FS_DVBUSPTIM) Offset address: 0x82C Reset value: 0x0000 05B8 Field Name Description...
Page 483 Field Name Description Reserved NAK Status 0: The module replies non-NAK handshake signal according to the FIFO state NAKSTS 1: The module replies the NAK handshake signal on this endpoint. At this time, even if there is space in TXFIFO, the module will still stop transmitting data.
Page 484 Field Name Description 14:11 Reserved USB Active Endpoint This bit indicates whether the endpoint is activated in the current USBAEP configuration and interface. After USB is reset, this bit will be cleared to 0 (except endpoint 0). Even Odd Frame This bit is used to indicate the frame number transmitted/received by the endpoint (for synchronization IN) or the PID of data packet (for interrupt/batch IN).
Page 485 Field Name Description NAK Set When performing write operation to this bit, the NAK bit of the NAKSET endpoint will be set to 1. This bit can control the transmission of NAK handshake signal. DATA0 PID Set  Used for interrupt/batch IN endpoints: When performing write operation to this bit, PID will be set to DATA0.
Page 486 Field Name Description Timeout Interrupt RC_W1 This bit is only applicable to the control IN endpoints, indicating that the response to the recently received IN token has timed out. Receive IN Token Interrupt when FIFO is empty This bit is only applicable to non-periodic IN endpoints, indicating that ITXEMP RC_W1 IN token is received when the corresponding TXFIFO of the endpoint...
Page 487 Field Name Description Endpoint Transfer Size 18:0 EPTRS This bit indicates the data size contained by endpoint x in one data transmission (in byte). Endpoint Packet Count 28:19 EPPCNT This bit indicates the number of data packets contained by endpoint x in one data transmission.
Page 488 Field Name Description USB Active Endpoint This bit indicates whether the endpoint is activated in the current USBAEP configuration and interface. This bit is always set to 1. Reserved NAK Status 0: The module replies non-NAK handshake signal according to the FIFO state NAKSTS 1: The module replies the NAK handshake signal on this endpoint.
Page 489 Field Name Description Maximum Packet Size 10:0 MAXPS This bit configures the maximum data packet size of endpoint. (in byte). 14:11 Reserved USB Active Endpoint This bit indicates whether the endpoint is activated in the current USBAEP configuration and interface. After USB is reset, this bit will be cleared to 0 (except endpoint Even Odd Frame This bit is used to indicate the frame number...
Page 490 Field Name Description NAK Clear NAKCLR When performing write operation to this bit, the NAK bit of the endpoint will be cleared to 0. NAK Set When performing write operation to this bit, the NAK bit of the NAKSET endpoint will be set to 1. This bit can control the transmission of NAK handshake signal.
Page 491 Field Name Description Transfer Complete Interrupt TSFCMP RC_W1 This bit indicates that the transmission on the endpoint has been completed. Endpoint Interrupt Disable EPDIS RC_W1 This bit means that the endpoint is disabled. Reserved SETUP Phase Complete Interrupt This bit is only applicable to the control OUT endpoint, SETPCMP RC_W1 indicating that the SETUP phase has been completed.
Page 492: Full-Speed Otg Power And Clock Gating Control Register (Otg_Fs_Pcgctrl)
Field Name Description Reserved Full-speed OTG device OUT endpoint x transmission size register (OTG_FS_DOEPTRS) (x=1~3, endpoint number) Offset address: 0xB10+0x20m; m=1~3 Reset value: 0x0000 0000 This register can be modified only after EPEN bit of OTG_FS_DOEPCTRLx register is set to 1; this register can be read only after EPEN bit of OTG_FS_DOEPCTRLx register is cleared to 0 Field Name...
Page 493: Otg_Hs1 Global Register Address Mapping
Field Name Description Gate HCLK 0: When the USB communication is restored or the session is restarted, it is allowed to stop providing the clock to modules other than AHB bus slave interface, main interface GCLK and wake-up 1: When the USB communication is suspended or the session is invalid, stop providing the clock for the modules other than AHB bus slave interface, main interface and wake-up...
Page 494: Otg_Hs1 Global Register Functional Description
Offset Register name Description address OTG_HS1_DTXFIFO4 High-speed OTG device IN endpoint TXFIFO size register 4 0x110 OTG_HS1_DTXFIFO5 High-speed OTG device IN endpoint TXFIFO size register 5 0x114 OTG_HS1_DTXFIFO6 High-speed OTG device IN endpoint TXFIFO size register 6 0x118 OTG_HS1_DTXFIFO7 High-speed OTG device IN endpoint TXFIFO size register 7 0x11C OTG_HS1 global register functional description High-speed OTG control state register (OTG_HS1_GCTRLSTS)
Page 495 Field Name Description Device HNP Enable 0: Disable DHNPEN 1: Enable Note: It can be used only in device mode 15:12 Reserved Connector ID Status 0: OTG_HS1 controller is in Device A mode CIDSTS 1: OTG_HS1 controller is in Device B mode Note: It can be used in both device and master modes Long/Short Debounce Time 0: Long debounce time...
Page 496 Field Name Description Host Negotiation Flag HNFLG RC_W1 When USB host negotiation request is detected, this bit will be set to 1. A-Device Timeout Flag If this bit is set to 1, it indicates timeout when A-device is ADTOFLG RC_W1 waiting for B-device to connect.
Page 497 High-speed OTG USB configuration register (OTG_HS1_GUSBCFG) Offset address: 0x0C Reset value: 0x0000 0A00 Field Name Description FS Timeout Calibration The additional delay of PHY includes the number of PHY clocks SEFLG and FS timeout interval. The status of data line may be different for different PHY..
Page 498 Field Name Description ULPI Auto-Resume This bit indicates whether ULPI PHY supports auto-resume function. ULPIAR 0: Not supported 1: Supported ULPI Clock Power This bit indicates whether internal clock power supply is turned off when PHY is suspended. ULPICLKP 0: Open 1: Not off ULPI External V Drive Select...
Page 499 High-speed OTG reset control register (OTG_HS1_GRSTCTRL) Offset address: 0x010 Reset value: 0x2000 0000 Field Name Description Core Soft Reset This bit controls HCLK and PCLK reset. Clear each interrupt and all CSR register bits to 0 except the followings:  GCLK bit in OTG_HS1_PCGCTRL ...
Page 500 Field Name Description TXFIFO Number Refresh the FIFO number with TXFIFO refresh bits, and these bits can only be changed after the refresh TXFFIO is cleared to 0. In master mode: 00000: Refresh non-periodic TXFIFO 00001: Refresh periodic TXFIFO 10000: Refresh all TXFIFO 10:6 TXFNUM In device mode:...
Page 501 Field Name Description Non-periodic TXFIFO Empty Interrupt This interrupt will be triggered when the non-periodic TXFIFO is NPTXFEM not empty and there is space for writable entries in the request queue. Note: It can be accessed only in master mode Global IN Non-periodic NAK Effective Interrupt This bit indicates that SGINAK bit of OTG_HS_DCTL register is valid;...
Page 502 Field Name Description IN Endpoint Interrupt This bit will be set to 1 when a suspended interrupt occurs to one IN endpoint. Determine the OUT endpoint to which an interrupt occurs by INEP reading OTG_HS1_DAEPINT register, and determine the causes of the interrupt by reading OTG_HS1_DIEPINTx register;...
Page 503 Field Name Description Periodic TXFIFO Empty Interrupt This interrupt will be triggered when the periodic TXFIFO is PTXFE empty and there is space for writable entries in the request queue. Note: It can be accessed only in master mode. Reserved Connector ID Status Change Interrupt CINSTSC RC_W1...
Page 504 Field Name Description Global IN Nonperiodic NAK Effective Interrupt Make 0: Mask the interrupt GINNPNAKEM 1: Interrupt Note: It can be accessed only in device mode Global OUT NAK Effective Interrupt Mask 0: Mask the interrupt GONAKEM 1: Interrupt Note: It can be accessed only in device mode Reserved Early Suspend Interrupt Mask 0: Mask the interrupt...
Page 505 Field Name Description OUT Endpoint Interrupt Mask 0: Mask the interrupt OUTEPM 1: Interrupt Note: It can be accessed only in device mode Incomplete Isochronous IN Transfer Interrupt Mask 0: Mask the interrupt IIINTXM 1: Interrupt Note: It can be accessed only in device mode Incomplete Periodic Transfer Interrupt Mask In master mode, this bit controls whether to mask incomplete periodic transmission interrupt.
Page 506 High-speed OTG read debug receive state register/high-speed OTG state read and pop register (OTG_HS1_GRXSTS/OTG_HS1_GRXSTSP) Read offset address: 0x01C Pop offset address: 0x020 Reset value: 0x0000 0000 Master mode Field Name Description Channel Number CHNUM This bit indicates the received data is transmitted by which channel. Byte Count 14:4 BCNT...
Page 507 Field Name Description 0100: SETUP event completed 0110: Received SETUP data packet Others: Reserved Frame Number These bits are valid when synchronous OUT endpoint is supported. 24:21 FNUM These bits are the 4 least significant bits of the packet frame number received on the USB.
Page 508 Field Name Description Nonperiodic TXFFIO Space Available These bits indicate the size of available space of non-periodic TXFIFO. (In 32-bit words) hx0: Non-periodic TXFIFO is full hx1: 1 word 15:0 NPTXFSA hx2: 2 words ….. hxn: n words are available (0≤n≤16) Others: Reserved Non-periodic Transmit Request Space Available This bit indicates the available space size of non-periodic transmit...
Page 509 Field Name Description I2C Enable I2CEN 0: Disable 1: Enable I2C ACK This bit indicates whether to receive ACK from I2C. 0：NAK 1：ACK This bit is valid when I2C is enabled and I2CSTSFLG bit is cleared to 0. Reserved I2C Device Address Select 27:26 DADDRSEL These bits are selected for I2C slave device address of the full-...
Page 510 Field Name Description B Device V Sensing Enable BDVBSEN 0: Disable 1: Enable SOF Pulse Available on PAD Output Enable This bit selects whether SOF pulse can be output from PAD. SOFPOUT 0: No 1: Yes Sensing Disable VBSDIS 0: Enable V sensing 1: Disable V sensing...
Page 511: Otg_Hs1 Host Mode Register Address Mapping
OTG_HS1 host mode register address mapping Table 138 OTG_HS1 Host Mode Register Address Mapping Register name Description Offset address OTG_HS1_HCFG High-speed OTG host configuration register 0x400 OTG_HS1_HFIVL High-speed OTG host frame interval register 0x404 OTG_HS1_HFIFM High-speed OTG host frame information register 0x408 High-speed OTG host periodic transmission state OTG_HS1_HPTXSTS...
Page 512 Field Name Description 11: Reserved Note: Software reset is required before change. HS Support This bit is used to control whether the connected device supports HS communication. HSSPT 0: Support HS/FS/LS 1: Only support FS/LS, and do not support HS 31:3 Reserved High-speed OTG host frame interval register (OTG_HS1_HFIVL)
Page 513 Field Name Description hxn: dxn words (0≤dxn≤dx512) Others: Reserved Periodic Transmit Request Queue Available Space This bit indicates the available space of transmit request queue (in 32-bit word), hx00: TXFIFO is full hx01: 1 word 23:16 QSPACE hx10: 2 words hxn: dxn words (0≤dxn≤dxHPDTXFDEP) Others: Reserved Note: HPDTXFDEP bit is in OTG_HS1_GHPTXFIFO register.
Page 514 High-speed OTG host port control state register (OTG_HS1_HPORTCSTS) Offset address: 0x440 Reset value: 0x0000 0000 Field Name Description Port Connect Flag This bit indicates whether this port is connected to the device. PCNNTFLG 0: Not connected 1: Connected Port Connect Interrupt for Flag Triggering PCINTFLG RC_W1 An interrupt will be triggered when the port connection is...
Page 515 Field Name Description Port Power This bit is used to control power-on of the port. 0: Power down 1: Power on Port Test Mode Select This bit is used to select the mode signal generated by the port. 0000: Test is disabled 0001：Test_J 16:13 PTSEL...
Page 516 Field Name Description Count Function Select Through SPLEN bit of HCHSCTRLX register, this bit can be selected for the counter used for indication. When SPLEN=0: This bit specifies the number of transactions to be executed by the periodic endpoint per micro-frame, or the number of data packets to be obtained by the channel during non-periodic transmission.
Page 517 Field Name Description 11: All Do Complete Split 0: Reserved DO_CMP_SPL 1: Transmit the request to the host to perform complete split transaction 30:17 Reserved Split Enable SPLEN 0: Disable 1: Enable; the channel is enabled to execute split transaction High-speed OTG host channel-X interrupt register (OTG_HS1_HCHINTX) (X=0…11) Offset address: 0x508+20*X...
Page 518 Field Name Description Transfer Complete Normally Mask TSFCMPNM 0: Mask 1: Interrupt Transfer Complete Abnormally Mask TSFCMPANM 0: Mask 1: Interrupt AHB Error Mask AHBERRM 0: Mask 1: Interrupt STALL Response Received Interrupt Mask RXSTALLM 0: Mask 1: Interrupt NAK Response Received Interrupt Mask RXNAKM 0: Mask 1: Interrupt...
Page 519: Otg_Hs1 Device Mode Register Address Mapping
Field Name Description Packet Count 28:19 PCKTCNT This bit is used to record the number of transmitted or received data packets. Data PID This bit is used to set the initial PID when the host transmits data communication and is maintained during transmission. 00：DATA0 30:29 DATAPID...
Page 520: Otg_Hs1 Device Mode Register Functional Description
Offset Register name Description address OTG_HS1_DTHCTRL High-speed OTG device threshold control register 0x830 High-speed OTG device IN endpoint FIFO empty OTG_HS1_DIEIMASK 0x834 interrupt mask register High-speed OTG device single-endpoint interrupt OTG_HS1_DEPINT 0x838 register High-speed OTG device single-endpoint interrupt mask OTG_HS1_DEPIMASK 0x83C register High-speed OTG device IN endpoint 1 interrupt mask...
Page 521 Field Name Description Device Speed Select This bit is used to select the speed of this module. 00: High speed DSPDSEL 01: Reserved 10: Reserved 11: Full speed Transmit the Received OUT Packet on Nonzero-length Status At the transmission OUT transaction stage, when the module receives a data packet with non-zero length, select the handshake signal to be transmitted by the program.
Page 522 Field Name Description Soft Disconnect Soft disconnect means that the host cannot learn that the device is connected, and the device cannot receive the signal on USB. SDCNNT 0: Work normally 1: The application program transmits soft disconnection signal Note: The USB will be always disconnected until this bit is cleared to 0.
Page 523 Field Name Description Suspend Status SUSSTS 0: Non-suspended state 1: Suspended state Enumerated Speed Enumeration speed after controlling OTG_HS1 to detect the speed through chirp sequence. 00: High speed ENUMSPD 01: Reserved 10: Reserved 11: Full speed Erratic Error ERTERR 0: No irregular error 1: Irregular error is detected Reserved...
Page 524 Field Name Description FIFO Underrun Mask FUDRM 0: Mask 1: Interrupt BNA Interrupt Mask BNAM 0: Mask 1: Interrupt 31:10 Reserved High-speed OTG device OUT endpoint interrupt mask register (OTG_HS1_DOUTIMASK) Offset address: 0x814 Reset value: 0x0000 0000 Field Name Description Transfer Completed Interrupt Mask TSFCMPM 0: Mask...
Page 525 The corresponding bits of the register correspond to the bits of OTG_HS1_DIEPINTx/OTG_HS1_DOEPINTx, and the corresponding endpoint interrupt bits need to be consistent. Field Name Description All IN Endpoint Interrupts 15:0 INEPINT No. X bit indicates interrupt of IN endpoint X. Up to 16 IN endpoints.
Page 526 Field Name Description 31:12 Reserved High-speed OTG device threshold control register (OTG_HS1_DTHCTRL) Offset address: 0x830 Reset value: 0x0000 0000 Field Name Description Nonisochronous IN Endpoints Threshold Enable NSINTHEN 0: Disable 1: Enable Isochronous IN Endpoint Threshold Enable SINTHEN 0: Disable 1: Enable Transmit Threshold Length 10:2...
Page 527 Reset value: 0x0000 0000 Field Name Description Reserved IN1INT In Endpoint 1 Interrupt 16:2 Reserved OUT1INT OUT Endpoint 1 Interrupt 31:18 Reserved High-speed OTG device single-endpoint interrupt mask register (OTG_HS1_DEPIMASK) Offset address: 0x83C Reset value: 0x0000 0000 Field Name Description Reserved IN1M In Endpoint 1 Interrupt Mask...
Page 528 Field Name Description IN Endpoint NAK Effective Mask IEPNAKEM 0: Mask 1: Interrupt Reserved FIFO Underrun Mask TXFUDRM 0: Mask 1: Interrupt BNA Interrupt Mask BNAM 0: Mask 1: Interrupt 12:10 Reserved NAK Interrupt Mask NAKM 0: Mask 1: Interrupt 31:14 Reserved High-speed OTG device OUT endpoint 1 interrupt mask...
Page 529 Field Name Description NAK Interrupt Mask NAKM 0: Mask the interrupt 1: Interrupt NYET Interrupt Mask NYETM 0: Mask the interrupt 1: Interrupt 31:15 Reserved High-speed OTG device IN endpoint x control register (OTG_HS1_DIEPCTRLx) (x=0~7, endpoint number) Offset address: 0x900+0x20m；m=0~7 Reset value: 0x0000 0000 Field Name...
Page 530 Field Name Description STALL Handshake  For uncontrolled and non-synchronous IN endpoints (read/write mode is RW): When this bit is set to 1, the device will reply STALL to all STALLH RW/RS tokens from the USB host. This bit can only be cleared to 0 by software.
Page 531 Reset value: 0x0000 0080 Read this register when ONEP bit of OTG_HS1_GCINT register is set to 1; Read OTG_HS1_DAEPINT register to obtain the accurate endpoint number of the device endpoint x interrupt register, and then read the register; only when the corresponding bit of the register is cleared to 0, can the corresponding bit of OTG_HS1_DAEPINT register and OTG_HS1_GCINT register be cleared to 0.
Page 532 Field Name Description 31:14 Reserved High-speed OTG device IN endpoint 0 transmission size register (OTG_HS1_DIEPTRS0) Offset address: 0x910 Reset value: 0x0000 0000 This register can be modified only after EPEN bit of OTG_HS1_DIEPCTRL0 register is set to 1; this register can be read only after EPEN bit of OTG_HS1_DIEPCTRL0 register is cleared to 0.
Page 533 High-speed OTG device IN endpoint x DMA address register (OTG_HS1_DIEPDMAx) (x=1~5, endpoint number) Offset address: 0x914+0x20m; m=1~5 Reset value: 0xXXXX XXXX Field Name Description DMA Address 31:0 DMAADDR This bit indicates the start address of external storage, and is used to store or obtain the endpoint data High-speed OTG device IN endpoint x TXFIFO state register (OTG_HS1_DITXFSTSx) (x=0~5, endpoint number) Offset address: 0x918+0x20m;...
Page 534 Field Name Description Endpoint Type 19:18 EPTYPE This bit is set to 00 by hardware, indicating control type of the endpoint. Snoop Mode Enable SNMEN In snoop mode, the correctness of OUT data packets is not checked before they are transmitted to the storage area. STALL Handshake The program can only set this bit to 1 and when the endpoint STALLH...
Page 535 Field Name Description 1: Odd frame Endpoint Data PID Used for interrupt/batch IN endpoints: 0：DATA0 1：DATA1 NAK Status 0: The module replies non-NAK handshake according to the FIFO state 1: The module replies the NAK handshake signal on this NAKSTS endpoint.
Page 536 Field Name Description Odd Frame Set OFSET When performing write operation to this bit, EOF bit of synchronous OUT endpoint will be set to odd frame. Endpoint Disable Data transmission on the endpoint can be stopped by setting this bit to 1. EPDIS This bit needs to be cleared to 0 before the endpoint disable interrupt bit is set to 1;...
Page 537 Field Name Description 13:7 Reserved NYET Interrupt NYET RC_W1 When the non-synchronous OUT endpoint responds to the NYET handshake signal, the interrupt will be generated. 31:15 Reserved High-speed OTG device OUT endpoint 0 transmission size register (OTG_HS1_DOEPTRS0) Offset address: 0xB10 Reset value: 0x0000 0000 This register can be modified only after EPEN bit of OTG_HS1_DOEPCTRL0 register is set to 1;...
Page 538: High-Speed Otg Power And Clock Gating Control Register
Field Name Description Endpoint Packet Count 28:19 EPPCNT This bit indicates the number of data packets contained by endpoint x in one data transmission. Receive Data PID or SETUP Packet Count  For synchronous OUT endpoints, this bit indicates the PID of the last received data packet.
Page 539: Otg_Hs2 Register Address Mapping
Field Name Description 1: When the USB communication is suspended or the session is invalid, stop providing the clock for the modules other than AHB bus slave interface, main interface and wake-up Reserved PHY Suspend PHYSUS This bit means that PHY is suspended. 31:5 Reserved OTG_HS2 register address mapping...
Page 540 Field Name Description Power on Core This signal is used to get ultra-low power, high active poweron_core 0: Power-down the core (analog domain) 1: Power-on the core (analog domain) is in working state In normal use, this pin suggest to tie H. 31:1 Reserved USB PLL enable register (USB_PLL_EN)
Page 541: Ethernet
Field Name Description TX Bit Stuff Enable Indicates if the DATA_OUT[7:0] lines needs to be bit stuffed or not. txbitstuffenable 0: Disable 1: Enable 31:1 Reserved Debounce filter bypass enable register (USB_DBNCE_FLTR_BYPASS) Offset address: 0x238 Reset value: 0x0000 0000 Field Name Description Bypass debounce filters for avalid, bvalid, vbusvalid,...
Page 542 Support 10/100Mbp data transmission rate Half-duplex operation  Support CSMA/CD protocol  Provide back pressure flow control Full-duplex operation  Support IEEE 802.3x flow control  If the flow control input signal disappears, the zero-range pause frame will be automatically transmitted ...
Page 543 During multi-frame storage of the receive FIFO, the receiving state vector is inserted into the receive FIFO after EOF transmission, so that the receiving state of these frames will not be stored by the receive FIFO In storage and forwarding mode, all error frames will be filtered in receiving process and not be forwarded to the application program Generate pulses for lost or damaged frames in the receive FIFO to support data statistics...
Page 544: Functional Description
Double-buffer (buffering ring) or linked list (chain) descriptor link Byte aligned addressing supported by data buffer Optimize packet-oriented DMA transmission Descriptor architecture, which allows transmission of large data blocks with minimal CPU intervention (each descriptor can transmit up to 8KB data) Comprehensive state when reporting normal operation and transmission errors...
Page 545 AF11 Port PB11 ETH_MII_TX_EN/ETH_RMII_TX_EN PB12 ETH_MII_TXD0/ETH_RMII_TXD0 PB13 ETH_MII_TXD1/ETH_RMII_TXD1 ETH_MDC ETH_MII_TXD2 ETH_MII_TX_CLK ETH_MII_RXD0/ETH_RMII_RXD0 ETH_MII_RXD1/ETH_RMII_RXD1 ETH_MII_TXD3 ETH_PPS_OUT PG11 ETH_MII_TX_EN/ETH_RMII_TX_EN PG13 ETH_MII_TXD0/ETH_RMII_TXD0 PG14 ETH_MII_TXD1/ETH_RMII_TXD1 ETH_MII_CRS ETH_MII_COL ETH_MII_RXD2 ETH_MII_RXD3 PI10 ETH_MII_RX_ER SMI, MII and RMII Ethernet peripherals include MAC 802.3 with dedicated DMA controller. It supports MII and RMII used by default and switches them through select bit.
Page 546 time. Both MDC clock line and MDIO data line are used as multiplexing function I/O in the microcontroller:  MDC: Periodic clock, which provides reference timing when transmitting data at 2.5MHz. The minimum high/low-level time of MDC is 160ns. The minimum cycle of MDC is 400ns. In idle state, the SMI management interface drives the MDC clock signal to low level.
Page 547 CR bit HCLK clock MDC clock 35-60MHz AHB clock/26 150-180MHz AHB clock/102 101、110、111 Reserved SMI write operation When MB bit and MW bit of MAC_ADDR are set to 1 by application program, SMI will trigger write operation of PHY register by transmitting PHY address, and register address in PHY, and writing data.
Page 548 Table 144 TX Interface Signal Encoding MII_TX_EN MII_TXD [3:0] Description 0000-1111 Normal frame internal 0000-1111 Normal data transmission Table 145 RX Interface Signal Encoding MII_RX_DV MII_RX_ER MII_RXD [3:0] Description 0000-1111 Normal frame internal 0000 Normal frame internal 0001-1101 Reserved 1110 Error carrier detection 1111 Reserved...
Page 549 MII/RMII selection When the Ethernet controller is not in reset mode or the clock is enabled, the application program needs to set MII/RMII mode. Media access control (MAC 802.3) The access method of IEEE 802.3 international standard applicable to LAN is CSMA/CD.
Page 550 Address assignment is based on the following types  Single address: The physical address related to THE special station in the network.  Group address: A multi-destination address related to one or more stations in a given network. There are two kinds of multicast addresses, namely, multicast group address and broadcast address.
Page 551 to the end of the Ethernet frame, the CRC will not be transmitted. However, when MAC is set to attach filling to the frame less than 60 bytes, CRC will be attached to the end of the filling frame. Transmit data packets Transmission of data packets contains transmission of single data packet and multiple data packets, and their operation mode is different.
Page 552 Retransmitting during conflict In half-duplex mode, when transmitting frames to MAC, collision event may occur on the MAC line interface. The MAC may even indicate retrying before finishing receiving the frame. Then the frame will be retransmitted and pop up from the FIFO again.
Page 553 Receive checksum offload The IPC bit in the MAC_CFG register controls the receive checksum offload. This function is to detect and process IPv4 and IPv6 frames in received Ethernet frame to ensure data integrity. The MAC identifies IPv4 or IPv6 frames by checking the type field of the received Ethernet frame.
Page 554 each received frame at the end of receiving of each frame. MII/RMII receive bit sequence Each half byte is transmitted from the two bits received on RMII to MII, and the transmitting order is from low to high. MAC interrupt Various events can generate an interrupt to the MAC core, and the MAC_ISTS register describes various event interrupts.
Page 555 Unicast source address filtering The MAC performs perfect filtering according to the source address of the received frame. By default, the MAC compares the SA field with the value in the SA register. When Bit 30 in the corresponding register is set, the MAC address register will be configured to contain SA for comparison.
Page 556 Frame DAIF DISBF DA filtering operation type and discard the pause control frame If PCTRLF=0x, fail when perfect/group filter matches, and discard the pause control frame If PCTRLF=0x, fail when hash filter matches, and discard the pause control frame If PCTRLF=0x, fail when hash or perfect/group filter matches, and discard the pause control frame Table 148 Source Address Filtering...
Page 557  Jabber timeout  Delay conflict  Excessive delay  Excessive conflict If there are no following errors during receiving, the received frame is a “good frame”:  Short frame  CRC error  MII_RXER input error  Alignment error (for 10/100Mb/s only) ...
Page 558 Precision time protocol (IEEE 1588PTP) The IEEE 1588 standard defines a protocol. It is suitable for systems that communicate through LAN supporting multicast message transmission and synchronous heterogeneous systems, including clocks with different fixing accuracy, resolution and stability. It supports precision clock synchronization in measurement and control systems which are realized by technologies such as network communication, LAN computing and distributed objects.
Page 559 Calibration method Synchronizing or updating the system time in a process is the coarse calibration method, and synchronizing or updating the system time in order to reduce the system time jitter is the precision calibration method. System time calibration method The 64-bit PTP time is refreshed by the PTP input reference clock HCLK.
Page 560 Host bus burst access DMA attempts fixed-length burst transmission on the AHB main interface. The maximum length of the burst depends on the PBL bit of DMABMOD register. The receive and transmit descriptors access the 16 bytes to be read with the maximum possible burst size.
Page 561 corresponding transmit descriptor 0 bit will be set to 1. If the second condition occurs, AINTS bit and TXUNF bit of ETH_DMASTS register will be set, and if the information is written to the transmission descriptor 0, the transmission polling will also be suspended. Functional description of general transmit descriptor The general transmit descriptor structure consists of four 32-bit words.
Page 562 Field Name Description IP Payload Error When this bit is set to 1, it indicates that the MAC transmitter detects an error in the TCP, UDP, or ICMP IP packet payload. The transmitter IPERR will check the payload length received in the IPv4 or IPv6 header according to the actual number of bytes of TCP, UDP or ICMP IP packets received from the application program.
Page 563 Field Name Description Second Address Chained When this bit is set to 1, the second address in the descriptor is the TXCH address of the next descriptor, not the address of the second buffer, and TXDES1[28:16] is "irrelevant" value. The priority of TXDES0[21] is higher than TXDES0[20].
Page 564 Field Name Description 0: This describer belongs to CPU 1: This describer belongs to DMA DMA will clear this bit when the frame transmission is completed or the buffer allocated in the descriptor is empty. All bits of the first descriptor of this frame should be set after all subsequent descriptors belonging to the same frame are set.
Page 565 Field Name Description Transmit Buffer 2 Address Pointer (Next descriptor address) / Transmit frame timestamp high It indicates the location of the data in the memory to the DMA. When all data have been transmitted, the DMA can use these bits to return the timestamp data. TXADDR2: When TXDES0[31]=1 and the descriptor ring structure is used, these bits indicate the physical address of buffer 2.
Page 566 Field Name Description Transmit Frame Timestamp High This bit field will be updated by the DMA with the 32 most significant bits 31:0 TXFTSH of the timestamp captured for the corresponding transmitted frame. The bit field contains a timestamp only when LS=1. Rx DMA Obtain receiving descriptor The receiver always tries to get an additional descriptor to add to the frame to...
Page 567 Functional description of general receive descriptor The general receive descriptor structure consists of four 32-bit words. If the timestamp function or IPv4 checksum offload is activated, the enhanced descriptor must be used. Receive descriptor word 0 (RXDES0) Field Name Description Payload Checksum Error / extended status available When this bit is set, the TCP, UDP or ICMP checksum calculated by the core does not match the checksum field of the received...
Page 568 Field Name Description Last Descriptor LDES When this bit is set, the buffer pointed to by the descriptor is the last buffer of the frame. First Descriptor When this bit is set, the descriptor contains the first buffer of the FDES frame.
Page 569 Field Name Description 0: This describer belongs to CPU 1: This describer belongs to DMA This bit will be cleared when DMA completes frame receiving or the allocated buffer in the descriptor is full. Table 149 Configuration in Normal Descriptor Format Bit 0 Bit 5 Bit 7...
Page 570 Field Name Description Receive Buffer 2 Size It indicates the size of the second data buffer. The buffer size must be a multiple of 4, 8, or 16, depending on the bus width, even if the 28:16 RXBS2 value of the buffer 1 address pointer is not aligned. When the buffer size is not a multiple of 4, 8, or 16, the generated behavior is undefined.
Page 571 Field Name Description Receive Buffer 2 Address Pointer (Next Descriptor Address) / Receive Frame Timestamp High It indicates the location of the data in the memory to the DMA. When all data have been transmitted, the DMA can use these bits to return the timestamp data. RXADDR1: When RXDES0[OWN]=1 and the descriptor ring structure is used, these bits indicate the physical address of buffer 2.
Page 572 Field Name Description IP header error When this bit is set, the 16-bit IPv4 header checksum calculated by the IPHERR core does not match the received checksum, or the IP datagram version does not match the Ethernet type value. IP payload error When this bit is set, the 16-bit IP payload checksum calculated by the IPPERR core does not match the received checksum.
Page 573: Mac Register Address Mapping
Field Name Description Receive Frame Timestamp Low This bit field will be updated by the DMA with the 32 least significant bits of the timestamp captured for the corresponding received frame. 31:0 RXFTSL DMA updates the bit field only for the last descriptor of the received frame.
Page 574: Mac Register Functional Description
Offset Register name Description address MAC_HTL Hash table low-bit register 0x0C MAC_ADDR MII address register 0x10 MAC_DATA MII data regisster 0x14 MAC_FCTRL Receive flow control register 0x18 MAC_VLANT VLAN tag register 0x1C MAC_REMWKUPFFL Remote wake-up frame filter register 0x28 MAC_PMTCTRLSTS PMT control and state register 0x2C MAC_DBG...
Page 575 Field Name Description Deferral Check The deferral check function enables MAC. When the delay of the transmitting state machine exceeds the mode of 24288 bits multiplied by 10 or 100 Mbps, the MAC will identify the frame aborted state, and set the excessive delay error in the transmitted frame state.
Page 576 Field Name Description Disable Receive Own When it is confirmed that phy_txen_o is in half-duplex mode, MAC will DISRXO disable receiving frames. When this bit is reset, MAC will receive all packets transmitted by PHY. This bit is not applicable if the MAC is working in full-duplex mode.
Page 577 Field Name Description Promiscuous Mode The address filtering module will pass all incoming frames, regardless of destination address or source address. The SA or DA state bits of the receiving state word are always cleared. Hash Unicast The MAC filters the destination address of unicast frames according to the hash table.
Page 578 Field Name Description If it matches the perfect filter or Hash filter set for the HMC or HUC bit, it will configure the address filter to pass the frame. When this bit is low and the HUC or HMC bit is set, the frame will be passed only when the Hash filter matches.
Page 579 Field Name Description Clock Range The selection of CR clock range determines the frequency of HCLK and is used to determine the frequency of MDC clock: Select HCLK MDC clock 000：60-100 MHz-HCLK/42 001：100-150 MHz-HCLK / 62 010：20-35 MHz-HCLK/16 011：35-60 MHz-HCLK/26 100：150-168 MHz-HCLK/102 101, 110, 111: Reserved Reserved...
Page 580 Field Name Description Transmit Flow Control Enable In full-duplex mode, when this bit is set, MAC will enable the flow control operation to transmit the pause frame. When this bit is reset, the flow control operation of MAC will be disabled, and MAC will not transmit any pause frame.
Page 581 VLAN tag register (MAC_VLANT) Offset address: 0x1C Reset value: 0x0000 0000 This register contains the IEEE 802.1Q VLAN tag, used to identify the VLAN frame. The MAC compares No. 13 and No. 14 bytes of the received frame (length/type) with 0x8100, and compares the next 2 bytes with VLAN tag; if the match is successful, set the receive VLAN bit of the received frame state.
Page 582 Field Name Description Filter 0 Command This 4-bit command controls filter x operation. Bit 3 specifies the address type and defines the destination address type of the mode. FL0COM When this bit is set to 1, the mode is applicable only to multicast frames.
Page 583 Field Name Description Filter 2 Offset This register defines the offset (within the frame range) of the frame to be detected by the filter x. This 8-bit mode offset is the offset of the 23:16 FL2OFF first byte of the filter x to be detected. The minimum allowable value is 12, which indicates the 13th byte of the frame (the offset value 0 indicates the first byte of the frame).
Page 584 Field Name Description Power Down When this bit is set to 1, all received frames will be discarded. When receiving the magic packet or wake-up frame, this bit will be automatically cleared to zero and the power-down mode will be disabled.
Page 585 Field Name Description MAC Receive Frame FIFO Controller Status When set to high, it indicates that the FIFO read/write controller of the MAC receive frame FIFO controller is active. RFCFCSTS 0: Write controller status 1: Read controller status Reserved RX FIFO Write Controller Active Status RWCSTS When set to high, it indicates that the RX FIFO write controller is valid and transmitting the received frame to FIFO.
Page 586 Field Name Description TX Status FIFO Full Status TXSTSFSTS When set to high, it indicates that TX FIFO is full. Therefore, no more frames can be received for transmission. 31:26 Reserved Interrupt state register (MAC_ISTS) Offset address: 0x38 Reset value: 0x0000 0000 Field Name Description...
Page 587 Field Name Description Time Stamp Trigger Interrupt Mask TSTIM If this bit is set to 1, generation of timestamp interrupts will be disabled. 15:10 Reserved MAC address 0 high register (MAC_ADDR0H) Offset address: 0x40 Reset value: 0x0010 FFFF Field Name Description MAC address 0 high bit [47:32] It contains the first 16 bits (47:32) of the first 6 bytes of MAC address...
Page 588 Field Name Description Bit 24: ADDR1L [7:0] Address Select Compare the MAC address 1 [47:0] with the DA field of the ADDRSEL received frame 1: Compare the MAC address 1 [47:0] with the SA field of the received frame Address Enable ADDREN 0: The address filter will ignore the address used for filtering 1: The address filter uses the MAC address 1 for filtering...
Page 589 MAC address 2 low register (MAC_ADDR2L) Offset address: 0x54 Reset value: 0xFFFF FFFF Field Name Description MAC Address 2 low bit [31:0] (MAC Address 2) This bit field contains the low 32 bits of the first 6-byte MAC address 31:0 ADDR2L 2.
Page 590: Mmc Register Address Mapping
MMC register address mapping Table 151 MMC Register Address Mapping Register name Description Offset address MMC_CTRL Control register 0x100 MMC_RXINT Receive interrupt register 0x104 MMC_TXINT Transmit interrupt register 0x108 MMC_RXINTMASK Mask receive interrupt register 0x10C MMC_TXINTMASK Mask transmit interrupt register 0x110 Transmitted good frames single collision MMC_TXGFSCCNT...
Page 591 Field Name Description MMC Counter Preset When this bit is set, all counters will be initialized or preset to almost full value or almost half value according to the above bit 5. This bit MCNTP will be automatically cleared to zero after 1 clock cycle. This bit, together with bit 5, is used to debug and test the generation of interrupt which is caused because the MMC counter changes to half the full value or full value.
Page 592 Field Name Description 20:16 Reserved Transmitted Good Frames TXGF RC_R This bit will be set when the transmitted good frame counter reaches half of its maximum value. 31:22 Reserved Mask receive interrupt register (MMC_RXINTMASK) Offset address: 0x10C Reset value: 0x0000 0000 Field Name Description...
Page 593 Transmitted good frames single collision counter register (MMC_TXGFSCCNT) Offset address: 0x14C Reset value: 0x0000 0000 Field Name Description Transmitted Good Frames Single Collision Counter 31:0 TXGFSCCNT Transmitted good frames single collision counter. Transmitted good frames more collision counter register (MMC_TXGFMCCNT) Offset address: 0x150 Reset value: 0x0000 0000 Field...
Page 594: Ptp Register Address Mapping
PTP register address mapping Used to support the register of precision network clock synchronization which is in accordance with IEEE 1588 standard. Table 152 PTP Register Address Mapping Register name Description Offset address PTP_TSCTRL Timestamp control register 0x700 PTP_SUBSECI Subsecond increment register 0x704 PTP_TSH Timestamp high bit register...
Page 595 Field Name Description ime Stamp System Time Update When this bit is set, the system time will be updated with the value specified in the timestamp high-bit update register and TSSTUD timestamp low-bit update register. TSSTINIT and TSSTUD must be read as zero before this bit is set. After the update is completed, this bit will be cleared to zero.
Page 596 Field Name Description Time Stamp Snapshot for Master Node Select TSSMNSEL 0: Slave node 1: Master node Time stamp Clock Node Select 00: Ordinary clock 17:16 TSCLKNSEL 01: Boundary clock 10: End-to-end transparent clock 11: Point-to-point transparent clock Time Stamp PTP Frame Filtering MAC Address Enable TSSPTPFMACEN When this bit is set and PTP is transmitted directly through Ethernet, this bit will filter PTP frames by using MAC address.
Page 597 Reset value: 0x0000 0000 Field Name Description System Time Subseconds Value 30:0 STSUBSEC System subsecond time, with precision of 0.46ns. System Time Select This bit indicates positive and negative values of the system time. 0: Positive STSEL 1: Negative Since the system time should always be positive, this bit is generally zero.
Page 598 Field Name Description Target Time Stamp High Value Storage second time. When the value of the timestamp matches or 31:0 TTSH exceeds two target timestamp registers at the same time, the MAC will generate an interrupt. Target timestamp low bit register (PTP_TTSL) Offset address: 0x720 Reset value: 0x0000 0000 Field...
Page 599: Dma Register Address Mapping
Field Name Description Note: As PPS output has irregular waveform at higher frequency, do not use the PPS output with frequency other than 1Hz as much as possible when using digital flip. 31:4 Reserved DMA register address mapping Table 154 DMA Register Address Mapping Register name Description Offset address...
Page 600 Field Name Description 1: The priority of Rx is higher than that of Tx Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword skipped between two unlinked descriptors Address skip starts from the end of the current descriptor to the beginning of the next descriptor. When the DSL value is equal to 0, DMA will regard the descriptor table as continuous in ring mode.
Page 601 Field Name Description When reset to low level, the PBL value in bit [13:8] is applicable to two kinds of DMA engines. PBLx4 Mode When set to high level, this bit will multiply the programmed PBL value PBLx4 by four times. Therefore, the DMA will transmit data at a maximum beam number of 4, 8, 16, 32, 64 and 128 according to the PBL value.
Page 602 Field Name Description Start of Receive List This field contains the base address of the first descriptor in the receive 31:0 RXSTA descriptor list. LSB bits [1:0, 2:0, or 3:0] of 32-bit, 64-bit, or 128-bit bus width is ignored and is regarded as all zero by DMA. Therefore, these LSB bits are read-only.
Page 603 Field Name Description Receive Buffer Unavailable This bit indicates that the host owns the next descriptor in the receive list and DMA cannot get it. The receiving process is suspended. To resume processing of the receive descriptor, the RXBU RC_W1 host should change the ownership of the descriptor and issue a receive poll demand command.
Page 604 Field Name Description ETH_DMASTS[2]: Transmit buffer is unavailable ETH_DMASTS[6]: Receive interrupt ETH_DMASTS[14]: Early receive interrupt Only the unmasked bit affects the normal interrupt summary bit. This is a sticky bit and it must be cleared each time the corresponding bit that causes this bit to be set is cleared. Receive Process State This field indicates the receive DMA FSM state.
Page 605 Field Name Description source to clear this bit to 0. When this bit is high, an interrupt will be generated after it is enabled. PMT Flag This bit indicates an interrupt event in the PMT module of MAC. The software must read the PMT control and state register in the PMTFLG MAC to obtain the exact cause of the interrupt and clear its source to clear this bit to 0.
Page 606 Field Name Description 00：64 01：32 10：96 11：128 Reserved Forward Undersized Good Frames When it is set, Rx FIFO will forward small frames, including padding bytes and CRC. When it is reset, Rx FIFO will discard all frames less than 64 bytes unless a frame has been transmitted because the receiving threshold is low, such as RTC=01.
Page 607 Field Name Description Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic will be reset to its default value, so all data in Tx FIFO will be lost or refreshed. This bit FTXF will be cleared internally when the refresh operation is completed. Before this bit is cleared, it should not be written into the operation mode register.
Page 608 Field Name Description Receive Overflow Interrupt Enable When this bit is set to 1 through bit [15], the receive overflow interrupt RXOVFEN will be enabled. When this bit is reset, the overflow interrupt will be disabled. Transmit Underflow Interrupt Enable When this bit is set to 1 through bit [15], the transmit underflow interrupt TXUNFEN will be enabled.
Page 609 Field Name Description ETH_DMASTS[13]: Fatal bus error Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary will be enabled. When this bit is reset, the normal interrupt summary will be disabled. This bit can enable the following interrupts: NINTSEN ETH_DMASTS[0]: Transmit interrupt ETH_DMASTS[2]: Transmit buffer is unavailable...
Page 610 Field Name Description Host Transmit Descriptor Address Pointer HTXDADDRP Pointer updaged by DMA during operation. 31:1 Reserved Current host receive descriptor register (ETH_DMAHRXD) Offset address: 0x104C Reset value: 0x0000 0000 Field Name Description Host Receive Descriptor Address Pointer HRXDADDRP Pointer updaged by DMA during operation. 31:1 Reserved Current host transmit buffer address register...
Page 611: Analog-To-Digital Converter (Adc)
Analog-to-digital converter (ADC) Full name and abbreviation description of terms Table 155 Full Name and Abbreviation Description of ADC Terms Full name in English English abbreviation Analog watchdog Conversion Injected Regular Start Scan SCAN Single SINGLE Automatic Group Discontinuous DISC Count Dual DUAL...
Page 612: Introduction
Full name in English English abbreviation Length Regular Channels Injected Channel Injected Group INJG Automatic Conversion Analog Watchdog Discontinuous Mode DISC Scan Mode SCAN Continuous Conversion CONTC Single Conversion SINGLEC External External Trigger EXTTRG Sample Time SMPTIM Sequence Number Introduction The series product has 3 ADC with 12-bit precision.
Page 613: Functional Description
Mode input channel category  External GPIO input channel  One internal temperature sensor (V ) input channel SENSE  One internal reference voltage (V ) input channel REFINT  One internal backup voltage (V ) input channel Channel conversion mode ...
Page 614 Name Description Signal type Equivalent to analog power supply of V and: Input, analog power 2.4V≤V ≤V (3.6V) during full-speed operation, supply 1.8V≤V ≤V (3.6V) during low-speed operation Input, analog Low-end/Negative reference voltage used by ADC, V REF- reference negative REF- electrode Input, analog power...
Page 615 After one conversion of regular channel is over, the converted data will be stored in 16-bit ADC_REGDATA register, and EOCFLG bit will be set to 1. If configuration EOCIEN bit is set to 1, an interrupt will be generated. After one conversion of injected channel is over, the converted data will be stored in 16-bit ADC_INJDATA1 register, and INJEOCFLG bit will be set to 1.
Page 616 Conversion mode of single ADC and one group of channels Single ADC and multiple channels Enable the scan mode under single-ADC multi-channel condition, the conversion is triggered by software rather than externally, the result of data conversion is right aligned, and the data of ADC conversion results are transmitted to the memory by DMA.
Page 617 Channel conversion sequence Configuration of regular sequence registers:  Configure REGSEQC1~REGSEQC6 bits of the register ADC_REGSEQ3 to set No. 1~6 conversion channels  Configure REGSEQC7~REGSEQC12 bits of the register ADC_REGSEQ2 to set No. 7~12 conversion channels  Configure REGSEQC13~REGSEQC16 bits of the register ADC_REGSEQ1 to set No.
Page 618 Figure 124 Scan Mode Timing Diagram Regular trigger EOCFLG Injection trigger EOCFLG Discontinuous mode This mode is suitable for a group of channels, which is equivalent to continuous conversion of multiple channels in a group of channels. For regular groups, this mode is started by REGDISCEN bit of configuration register ADC_CTRL1;...
Page 619 Figure 125 Discontinuous Mode Timing Diagram Regular trigger EOCFLG Injection trigger EOCFLG Injected channel management Trigger injection: Start by clearing INJGACEN bit of the register ADC_CTRL1 and configuring the SCANEN bit. If a software trigger or external trigger is generated during the conversion of regular group channels, the injected conversion will be triggered.
Page 620 Figure 127 Automatic Injection Timing Diagram Regular group Injected group EOCFLG INJEOCFLG Dual or triple ADC mode and conversion mode of one group of channels For products with two or more ADC modules, dual or triple ADC mode is used. ADC1 is the master ADC by default, while others are the slave ADC by default, and the ADC mode is set by configuring ADCMSEL bit in ADC1_CCTRL register.
Page 621 converted. Alternate mode The alternate mode means multiple ADC convert a regular channel group alternately. The external trigger event is determined by REGEXTTRGSEL of the register ADC1_CTRL2. Dual ADC mode: After triggering, ADC1 starts first, ADC2 starts after delay, and the delay is configured through SMPDEL2 bit of the register ADC_CCTRL.
Page 622 External trigger Register configuration of external trigger is as follows:  The external event trigger of regular group channel is enabled by REGEXTTRGSEL bit of configuration register ADC_CTRL2  The external event trigger of injected group channel is started by INJGEXTTRGSEL bit of configuration register ADC_CTRL2.
Page 623 Trigger source INJGEXTTRGSEL[3:0] Trigger type TMR4_CC3 1000 TMR4_TRGO 1001 TMR5_CC4 1010 TMR5_TRGO 1011 TMR8_CC2 1100 TMR8_CC3 1101 TMR8_CC4 1110 EINT Line 15 1111 External pin Data register Regular data register ADC_REGDATA is a 32-bit ADC regular data register. In single-ADC mode, only the lower 16 bits are used to store the converted data.
Page 624: Register Address Mapping
Determine by EOCFLG bit of configuration register ADC_STS. Interrupt of end of conversion of injected group channels An interrupt will be generated after the conversion of injected channels is completed; read the value of the regular data register in the interrupt function. Determine by INJEOCFLG bit of configuration register ADC_STS.
Page 625: Register Functional Description
Register name Description Offset address ADC_INJDATAx ADC injected data register X 0x3C–0x48 ADC_REGDATA ADC regular data register 0x4C ADC_CSTS ADC general-purpose state register 0x00 ADC_CCTRL ADC general-purpose control register 0x04 Applicable to dual and triple mode general rule data ADC_CDATA 0x08 registers Register functional description...
Page 626 Field Name Description Analog Watchdog Channel Select 00000: ADC analog input channel 0 00001: ADC analog input channel 1 …… AWDCHSEL 01111: ADC analog input channel 15 10000: ADC analog input channel 16 10001: ADC analog input channel 17 10010: ADC analog input channel 18 Other value: Reserved EOC Interrupt Enable Used to enable the generation of interrupt after the conversion is...
Page 627 Field Name Description Discontinuous Mode Channel Number Configure 000: One channel 15:13 DISCNUMCFG 001: Two channels …… 111: Eight channels 21:16 Reserved Enable the Analog Watchdog Function On the Injected Channels INJAWDEN 0: Disable 1: Enable Enable the Analog Watchdog Function On the Regular Channels REGAWDEN 0: Disable 1: Enable...
Page 628 Field Name Description 1: EOCFLG bit will be set to 1 at the end of each regular conversion Data Alignment Mode Configure DALIGNCFG 0: Right alignment 1: Left alignment 15:12 Reserved Select the External Trigger Event to Start the Injected Group Conversion 0000: CC4 event of timer 1 0001: TRGO event of timer 1...
Page 629 Field Name Description Enable the External Trigger for Regular Channels 00: Trigger detection is disabled 29:28 REGEXTTRGEN 01: Trigger detection on rising edge 10: Trigger detection on falling edge 11: Trigger detection on rising edge and falling edge Start Conversion of Regular Channels REGSWSC 0: Reset state 1: Start conversion of regular channels...
Page 630 Field Name Description Data Offset For Injected Channel x When converting the injected channels, these bits define the values to 11:0 INJDOFx be subtracted from the original converted data, and the result of the conversion can be read in the ADC_INJDATAx register. 31:12 Reserved Analog watchdog high-threshold register (ADC_AWDHT)
Page 631 ADC regular sequence register 2 (ADC_REGSEQ2) Offset address: 0x30 Reset value: 0x0000 000 Field Name Description Conversion In Regular Sequence REGSEQC7 Refer to the description of REGSEQC13. Conversion In Regular Sequence REGSEQC8 Refer to the description of REGSEQC13. Conversion In Regular Sequence 14:10 REGSEQC9 Refer to the description of REGSEQC13.
Page 632 Field Name Description Conversion In Injected Sequence INJSEQC1 Define the channel number of No. 1 conversion in injected sequence (0~17) INJSEQC2 Conversion In Injected Sequence 14:10 INJSEQC3 Conversion In Injected Sequence) 19:15 INJSEQC4 Conversion In Injected Sequence）n Injected Sequence) Injected Channel Sequence Length These bits are defined by software as the number of channels in injected channel conversion sequence, and the conversion sequence INJSEQC(4-INJSEQLEN) →INJSEQ (5-INJSEQLEN) →INJSEQC(6-...
Page 633 Reset value: 0x0000 0000 Field Name Description AWDFLG1 Analog Watchdog Flag of ADC1 EOCFLG1 End of Conversion Flag of ADC1 INJEOCFLG1 Injected Channel End Of Conversion Flag of ADC1 INJCSFLG1 Injected Channel Start Flag of ADC1 REGCSFLG1 Regular Channel Start Flag of ADC1 OVRFLG1 Overrun Flag of ADC1 Reserved...
Page 634 Field Name Description 00111: Only alternate mode 01001: Only alternate trigger mode Triple mode: ADC1, ADC2 and ADC3 work together 10001: Regular simultaneous+ injected simultaneous combined mode 10010: Regular simultaneous+ alternate trigger combined mode 10011: Reserved 10101: Only injected simultaneous mode 10110: Only regular simultaneous mode 10111: Only alternate mode...
Page 635 Applicable to dual and triple mode general rule data registers (ADC_CDATA) Offset address: 0x08 (this offset address is only related to ADC1 base address+0x300) Reset value: 0x0000 0000 Field Name Description 1st Data Item Of A Pair Of Regular Conversions 15:0 DATA1 In dual mode, these bits include regular data of ADC1...
Page 636: Digital-To-Analog Converter (Dac)
Digital-to-analog converter (DAC) Full name and abbreviation description of terms Table 160 Full Name and Abbreviation Description of DAC Terms Full name in English English abbreviation Linear Feedback Shift Register LFSR Introduction DAC is a digital/analog converter that can be configured to input 8-bit or 12-bit data and output voltage.
Page 637 DAC_DATAOCHx. When the channel trigger is disabled (TRGENCHx bit in the register DAC_CTRL is set to 0), write the value in DAC_DHx register and it will be automatically transferred to DAC_DATAOCHx after one APB1 clock cycle. When the channel trigger is enabled (TRGENCHx bit in the register DAC_CTRL is set to 1), write the value in DAC_DHx register and it will be transferred to DAC_DATAOCHx after different clock cycles according to the selected trigger source.
Page 638 DAC waveform generation Each channel of DAC can independently generate noise and triangle wave. DAC double-channel conversion When two channels work at the same time, the written data can be written to the common registers: DH8RDUAL, DH12RDUAL and DH12LDUAL, so as to effectively use the bus bandwidth.
Page 639 Configure two channels and use different trigger sources; Enable the triangle wave generation function of two channels, and set different triangular amplitudes. Synchronous trigger Synchronous software startup Disable the trigger mode of two channels; after writing data, wait for one APB1 clock cycle and then transfer to DAC_DATAOCH1 and DAC_DATAOCH2 registers at the same time.
Page 640: Register Address Mapping
Enable the triangle wave generation function of two channels, and set different triangular amplitudes. Register address mapping Table 161 DAC Register Address Mapping Register name Description Offset address DAC_CTRL DAC control register 0x00 DAC_SWTRG DAC software Trigger Register 0x04 DAC_DH12R1 DAC Channel 1 12-bit right-aligned data holding register 0x08 DAC_DH12L1...
Page 641 Field Name Description 000: TMR6 TRGO event 001: TMR8 TRGO event 010: TMR7 TRGO event 011: TMR5 TRGO event 100: TMR2 TRGO event 101: TMR4 TRGO event 110: External interrupt line 9 111: Software trigger DAC Channel1 Noise/Triangle Wave Generation Enable 00: Waveform is not generated WAVENCH1 01: Noise waveform is generated...
Page 642 Field Name Description DAC Channel2 Trigger Source Select The trigger source can be selected through this register when Channel 2 trigger is enabled (TRGENCH2=1) 000: TMR6 TRGO event 001: TMR8 TRGO event 010: TMR7 TRGO event 21:19 TRGSELCH2 011: TMR5 TRGO event 100: TMR2 TRGO event 101: TMR4 TRGO event 110: External interrupt line 9...
Page 643 Field Name Description DAC Channel1 Software Trigger Enable This bit can be set to 1 and cleared by software; once the data in the register DAC_DH1 is transferred to the register DAC_DATAOCH1, this SWTRG1 bit will be cleared by hardware. 0: Disable 1: Enable DAC Channel2 Software Trigger Enable...
Page 644 DAC Channel 2 12-bit right-aligned data holding register (DAC_DH12R2) Offset address: 0x14 Reset value: 0x0000 0000 Field Name Description 11:0 DATA DAC Channel2 12-bit Right-Aligned Data 31:12 Reserved DAC Channel 2 12-bit left-aligned data holding register (DAC_DH12L2) Offset address: 0x18 Reset value: 0x0000 0000 Field Name...
Page 645 Field Name Description 15:4 DATACH1 DAC Channel1 12-Bit Left-Aligned Data 19:16 Reserved 31:20 DATACH2 DAC Channel212-Bit Left-Aligned Data Dual-DAC 8-bit right-aligned data holding register (DAC_DH8RDUAL) Offset address: 0x28 Reset value: 0x0000 0000 Field Name Description DATACH1 DAC Channel1 8-bit Right-Aligned Data 15:8 DATACH2 DAC Channel2 8-bit Right-Aligned Data...
Page 646: Random Number Generator (Rng)
Random number generator (RNG) Introduction RNG is a random number generator, which provides a 32-bit random number in the master reading based on continuous analog noise. Main characteristics Provide 32-bit random number generated by the analog generator The interval between two consecutive random numbers is 40 PLLCLK48 clock signal cycles Monitor RNG entropy to mark abnormal behaviors Disabling RNG can reduce the power consumption...
Page 647: Register Address Mapping
Do not use the first random number generated after RNGEN bit is set, and it should be saved for comparison with the next random number. Each random number needs to be compared with the previous random number. If any pair is equal, it means that the continuous random number generator test fails.
Page 648 Field Name Description 31:4 Reserved RNG state register (RNG_STS) Offset address: 0x04 Reset value: 0x0000 0000 Field Name Description Data Ready 0: RNG_ Data register is not ready, and the random data is not available 1: RNG_ Data register is ready, and the random data is DATARDY available An interrupt will be pending when INTEN=1.
Page 649 Field Name Description Random Data 31:0 DATA 32-bit data number. www.geehy.com Page 648...
Page 650: Cryp
CRYP Note: Only APM32F415xG/APM32F417xExG series products have such module. Introduction The encryption processor can encrypt and decrypt the data to be transmitted with DES, triple DES or AES algorithms. Main characteristics Support DES, TDES and AES encryption and decryption operations DES/TDES ...
Page 651: Dma
generated. When DMA is used for memory data transmission, data transmission will be carried out in burst mode. The burst length of AES is 4 words, and the burst length of DES/TDES is 2 words and 4 words. Configure INEN bit and OUTEN bit of CRYP_DMACTRL register to 1 to enable DMA request, all transmissions and processing are managed by the DMA and encryption processor, and the DMA interrupt indicates the end of the processing process.
Page 652 Field Name Description 010：DES-ECB 011：DES-CBC 100：AES-ECB 101：AES-CBC 110：AES-CTR 111: Decide AES key according to decryption mode Data Type Select 00: 32-bit data DTSEL 01: 16-bit data or half word 10: 8-bit data or byte 11: Bit data or bit string Key Size Select 00: 128-bit key length KSIZESEL...
Page 653 Field Name Description 31:5 CRYP data input register (CRYP_DATAIN) Offset address: 0x08 Reset value: 0x00 0000 Field Name Description Data Input Read = Return the contents of the input FIFO when the CRYP bit is 0; 31:0 DATAIN otherwise, an uncertain value will be returned Write = Write the contents of the input FIFO CRYP data output register (CRYP_DATAOUT) Offset address: 0x0C...
Page 654 CRYP original interrupt state register (CRYP_INTSTS) Offset address: 0x18 Reset value: 0x0000 0001 Field Name Description Input FIFO Service Raw Interrupt Status INISTS 0: Not suspended 1: Suspended Output FIFO Service Raw Interrupt Status OUTISTS 0: Not suspended 1: Suspended 31:2 Reserved CRYP mask interrupt state register (CRYP_MINTSTS)
Page 655 CRYP_K2L (offset address: 0x2C) Field Name Description 31:0 x=96-127，y=2.32-2.1 CRYP_K2R (offset address: 0x34) Field Name Description 31:0 x=64-95，y=2.64-2.33 CRYP_K3L (offset address: 0x38) Field Name Description 31:0 x=32-63，y=3.32-3.1 CRYP_K3R (offset address: 0x3C) Field Name Description 31:0 x=0-31，y=3.64-3.33 CRYP initialization vector register (CRYP_IV0…1 (L/R)) Offset address: 0x40-0x4C Reset value: 0x0000 0000 CRYP_IV0L (offset address: 0x40)
Page 656: Cyclic Redundancy Check Computing Unit (Crc)
Cyclic redundancy check computing unit (CRC) Introduction The cyclic redundancy check (CRC) computing unit can get 32-bit CRC computing result by calculating the input data through a fixed generator polynomial, which is mainly used to detect or verify the correctness and integrity of the data after transmission or saving.
Page 657 Independent data register (CRC_INDATA) Offset address: 0x04 Reset value: 0x0000 0000 Field Name Description Independent 8bit Data Can be used for temporary storage of 1-byte data. INDATA CRC rest generated by RST bit of the register CRC_CTRL has no effect on this register.
Page 658: Chip Electronic Signature
Chip electronic signature Introduction The chip electronic signature is used to match the firmware or external device. Register functional description 96-bit unique chip ID of unique device Base address: 0x1FFF 7A10 Offset address: 0x00 Field Name Description 31:0 U_ID[31:0] Unique identity flag 31:0 bit Offset address: 0x04 Read-only, the value has been prepared before leaving the factory Field...
Page 659: Version History
Version History Table 165 Document Version History Date Version Change History September, 2021 V1.0 (1) “SCLKSWSTS” changed to “SCLKSELSTS” April 1, 2022 V1.1 (2) Modify DMC pins (3) The APM32F405/415xG model is added (1) Modify the Arm trademark (2) Add the statement June 17, 2022 V1.2 (3) Add the note in Chapter3.5.3.1 ”Erase/write option byte”...
Page 660 Statement This document is formulated and published by Geehy Semiconductor Co., Ltd. (hereinafter referred to as “Geehy”). The contents in this document are protected by laws and regulations of trademark, copyright and software copyright. Geehy reserves the right to make corrections and modifications to this document at any time.
Page 661 4. Information Reliability The relevant data in this document are obtained from batch test by Geehy Laboratory or cooperative third-party testing organization. However, clerical errors in correction or errors caused by differences in testing environment may occur inevitably. Therefore, users should understand that Geehy does not bear any responsibility for such errors that may occur in this document.
Page 662 DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY USERS OR THIRD PARTIES). 8. Scope of Application The information in this document replaces the information provided in all previous versions of the document. © 2021-2022 Geehy Semiconductor Co., Ltd. - All Rights Reserved www.geehy.com Page 661...

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Geehy SEMICONDUCTOR APM32F405/415 G Series User Manual

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