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Geehy SEMICONDUCTOR APM32F030 6 8 C Series User Manual

Arm cortex -m0+ based 32-bit mcu
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User Manual
APM32F030x6x8xC
®
®
Arm
Cortex
-M0+ based 32-bit MCU
Version: V1.4
www.geehy.com
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Summary of Contents for Geehy SEMICONDUCTOR APM32F030 6 8 C Series

  • Page 1 User Manual APM32F030x6x8xC ® ® Cortex -M0+ based 32-bit MCU Version: V1.4 www.geehy.com Page 0...

  • Page 2: Table Of Contents

    Contents Introduction and Document Description Rules ........6 Introduction ....................... 6 Document Description Rules ..................6 System Architecture ................9 Full Name and Abbreviation Description of Terms ............ 9 System Architecture Block Diagram ................. 9 Memory Mapping ....................11 Startup Configuration ....................11 FLASH Memory ..................
  • Page 3 Main Characteristics ....................59 Interrupt and Exception Vector Table ..............59 External Interrupt and Event Controller (EINT) ......... 61 Introduction ......................61 Functional Description .................... 61 Register Address Mapping ..................63 Register Functional Description ................63 Direct Memory Access (DMA) ............. 66 Introduction ......................
  • Page 4 General-purpose Timer (TMR3) ............131 14.1 Introduction ......................131 14.2 Main Characteristics ..................... 131 14.3 Structure Block Diagram ..................132 14.4 Functional Description ..................132 14.5 Register Address Mapping ..................145 14.6 Register Functional Description ................146 General-purpose Timer (TMR14) ............160 15.1 Introduction ......................
  • Page 5 19.4 IWDT Register Address Mapping ................. 221 19.5 IWDT Register Functional Description ..............222 19.6 WWDT Register Address Mapping ............... 224 19.7 WWDT Register Functional Description ............... 224 Real-time clock (RTC) ................ 226 20.1 Full Name and Abbreviation Description of Terms ..........226 20.2 Introduction ......................
  • Page 6 24.3 Functional Description ..................312 24.4 Register Address Mapping ..................316 24.5 Register Functional Description ................316 Cyclic Redundancy Check Computing Unit (CRC) ......323 25.1 Introduction ......................323 25.2 Functional Description ..................323 25.3 Register Address Mapping ..................323 25.4 Register Functional Description ................

  • Page 7: Introduction And Document Description Rules

    Introduction and Document Description Rules Introduction This reference manual provides application developers with all the information about how to use MCU (micro-controller) system architecture, memory and peripherals. ® ® ® ® For information about Arm Cortex -M0+ core, please refer to Arm Cortex -M0+ Technical Reference Manual;...
  • Page 8 Full name in English English abbreviation Enable Disable Clear Select Configure Contrl CTRL Controller Reset Stop STOP Load Calibration Initialize INIT Error Status Ready Software Hardware Source System Peripheral Address ADDR Direction Clock Input Output Interrupt Data DATA Size SIZE Divider Prescaler Multiplier...
  • Page 9 Table 3 Full Name and Abbreviation of Modules Full name in English English abbreviation Reset and Clock Management Power Management Unit Nested Vector Interrupt Controller NVIC External Interrupt /Event Controller EINT Direct Memory Access Debug MCU DBG MCU General-Purpose Input Output Pin GPIO Alternate Function Input Output Pin AFIO...

  • Page 10: System Architecture

    System Architecture Full Name and Abbreviation Description of Terms Table 4 Full Name and Abbreviation Description of Terms Full name in English English abbreviation Advanced High-Performance Bus Advanced Peripheral Bus System Architecture Block Diagram The main system mainly consists of two master modules and four slave modules. The main modules are Arm ®...
  • Page 11 Figure 1 APM32F030x6x8xC System Architecture Block Diagram Arm® Cortex®-M0+ (Fmax:48MHz) NVIC Flash Bus matrix GPIOs Flash (A-D,F) SRAM interface AHB1/APB TMR1/3/6/7/1 bridge 4/15/16/17 WWDT IWDT SYSCFG SPI1/2 EINT USART1-6 I2C1/2 DBGMCU Note: APM32F030x6x8 has no USART3-6 and no TMR7. Table 5 Bus Name Name Instruction ®...

  • Page 12: Memory Mapping

    Memory Mapping The memory mapping address is totally 4GB address. The assigned addresses include the core (including core peripherals), on-chip Flash (including main memory area, system memory area and option bytes), on-chip SRAM, and bus peripherals (including AHB and APB peripherals). Please refer to the data manual of the corresponding model for specific information of various addresses.

  • Page 13: Flash Memory

    FLASH Memory This chapter mainly introduces the storage structure, read, erase, write, read/write protection, unlock/lock characteristics of Flash, and the involved register functional description. Full Name and Abbreviation Description of Terms Table 7 Full Name and Abbreviation Description of Terms Full name in English English abbreviation Flash Memory Controller...

  • Page 14: Functional Description

    Block Name Address area Size (byte) Sector Main memory area Page 31 0x0800 7C00–0x0800 7FFF Main memory area … … … … Main memory area Page 60 0x0800 F000–0x0800 F3FF Main memory area Page 61 0x0800 4000–0x0800 F7FF Fan 15 Main memory area Page 62 0x0800 8000–0x0800 FBFF...
  • Page 15 Different wait cycles should be configured for different system clocks:  0 wait cycle: 0<system clock≤24MHz  1 wait cycle: 24MHz<system clock≤48MHz Prefetch buffer It can improve the reading speed and every time it is reset, the prefetch buffer will be automatically opened; the read interface with prefetch buffer. It can be configured only when the system clock is consistent with AHB clock and is less than 24MHz, and can be used only when the system clock is consistent with AHB clock.

  • Page 16: Option Byte

    products, the basic unit of write protection is 4 pages (i.e. KB). Read protection The read protection has three levels, namely, Level 0, Level 1 and Level 2, which are specifically described as follows: Table 10 Difference among Read Protection Levels Category READPROT Description...
  • Page 17 3.4.3.4 Unlock/Lock option byte After the system reset, the option byte is locked by default. Only when the option byte is unlocked correctly, can it be modified. The difference between option byte unlocking and flash unlocking is that FMC_OBKEY register rather than FMC_KEY register writes the KEY value.

  • Page 18: Register Address Mapping

    Initial Address Option byte Functional description value 0x1FFF F806 Data1 0xFF User data byte 1 0x1FFF F807 nData1 0x00 Data complementary code 0x1FFF F808 WRP0 0xFF Write protection configuration 0 0x1FFF F809 nWRP0 0x00 WRP0 complementary code 0x1FFF F80A WRP1 0xFF Write protection configuration 1 0x1FFF F80B...

  • Page 19: Register Functional Description

    Register name Description Offset address FMC_CTRL2 Control register 2 0x10 FMC_ADDR Address register 0x14 FMC_OBCS Option byte control/state register 0x1C FMC_WRTPROT Write protection register 0x20 Register Functional Description Control register 1 (FMC_CTRL1) Offset address: 0x00 Reset value: 0x0000 0000 Field Name Description Wait State Configure...
  • Page 20 State register (FMC_STS) Offset address: 0x0C Reset value: 0x0000 0000 Field Name Description Busy Flag BUSYF This bit indicates that a flash operation is in progress. These bits can only perform write operation, and 0 is returned when read operation is performed. Reserved Programming Error Flag This bit will be set by software when the value before the address is edited is...
  • Page 21 Field Name Description When STS_PEF=1 or STS_WPEF=1, set this bit to generate an interrupt. Reserved Operation Complete Interrupt Enable 0: Operation completion interrupt is disabled OCIE 1: Operation completion interrupt is enabled When STS_OCF=1, set this bit to generate an interrupt. Force Option Byte Load When this bit is set to 1, force to reload the option byte to generate system reset.
  • Page 22 Field Name Description nReset in STOP Mode RSTSTOP 0: Generate 1: Not generate nReset in STANDBY Mode RSTSTDB 0: Generate 1: Not generate Reserved nBOOT1 nBoot1 Mode Configure VDDAMONI Monitor SRAMPARITY SRAM Parity Check Reserved 23:16 DATA0 Data0 31:24 DATA1 Data1 Write protection register (FMC_WRTPROT) Offset address: 0x20...

  • Page 23: System Configuration Controller (Syscfg)

    System Configuration Controller (SYSCFG) Full Name and Abbreviation Description of Terms Table 14 Full Name and Abbreviation Description of Terms Full name in English English abbreviation Fast Mode Plus System Configuration Controller SYSCFG SYSCFG is mainly used to manage address mapping and control interrupts, specifically: controlling the fast mode plus of I2C on some IO ports;...
  • Page 24 Field Name Description Memory Mapping Select Control the memory mapping address 0x0000 0000. After reset, the parameters of these bits are determined by actual MMSEL BOOT. X0: Main flash mapping address: 0x0000 0000 01: System flash mapping address: 0x0000 0000 11: Embedded SRAM mapping address: 0x0000 0000 Reserved ADC DMA Request Remap...
  • Page 25 Field Name Description FM+ Driving Capability Activate for I2C1) 0: The fast mode plus is only controlled by I2CPxxFM+ bit. I2C1FMP 1: All pins of I2C1 can be seleccted for fast mode plus by GPIO_AFx. Reserved Fast Mode Plus Driving Capability Activate for I2C PA9 and PA10 23:22 I2CFMP...
  • Page 26 Field Name Description EINT3 Configure These bits are controlled by software to be rewritten to select the external 15:12 EINT3 interrupt source of EINT3. The selected external interrupt sources represented by values of the bits are shown in Table 16 31:16 Reserved External interrupt register 2 (SYSCFG_EINTCFG2)
  • Page 27 Field Name Description EINT10 Configure These bits are controlled by software to be rewritten to select the external 11:8 EINT10 interrupt source of EINT10. The selected external interrupt sources represented by values of the bits are shown in Table 16 EINT11 Configure These bits are controlled by software to be rewritten to select the external 15:12...
  • Page 28 Field Name Description SRAM Parity Error Flag When an SRAM parity error is detected, this bit will be set by hardware. SRAMEFLG RC_W1 This bit will be cleared when the software writes "1". 0: No SRAM parity check bit error is detected 1: SRAM parity check bit error 31:9 Reserved...

  • Page 29: Reset And Clock Management (Rcm)

    Reset and Clock Management (RCM) Full Name and Abbreviation Description of Terms Table 17 Full Name and Abbreviation Description of Terms Full name in English English abbreviation Reset and Clock Management Reset Power-On Reset Power-Down Reset High Speed External Clock HSECLK Low Speed External Clock LSECLK...
  • Page 30  Load option byte reset  Power reset A system reset will occur in case of any of the above events. Besides, the reset event source can be identified by viewing the reset flag bit in RCM_CSTS (control/state register). Generally speaking, when the system is reset, the values of all registers except the reset flag bit of RCM_CSTS will be reset to the reset value.

  • Page 31: Power Reset

    Figure 2 "System Reset" Reset Circuit External System Filter reset reset NRST WWDT reset IWDT reset Power reset Software reset Low-power management reset Load option byte reset Exit from standby mode Power Reset "Power reset" reset source is as follows: ...
  • Page 32  External crystal/ceramic resonator  External clock of user The hardware configuration of the two kinds of clock sources is shown in the figure below. Figure 3 HSECLK/LSECLK Clock Source Hardware Configuration Clock source Hardware configuration OSC_IN OSC_OUT External clock GPIO External clock source...

  • Page 33: Internal Clock Source

    5.3.1.2 LSECLK low-speed external clock signal LSECLK clock signal is generated by LSECLK external crystal/ceramic resonator and LSECLK external clock two kinds of clock sources. Table 19 Clock Source Generting LSECLK Name Instruction The cock is provided to to MCU through OSC32_IN pin. The signal can be generated by ordinary function signal transmitter (in debugging), crystal oscillator and other signal generators;...
  • Page 34 that of HSECLK crystal oscillator; even after calibration, its clock frequency accuracy is still inferior to that of HSECLK crystal oscillator. 5.3.2.2 LSICLK low-speed internal clock signal Main characteristics of LSICLK LSICLK is generated by RC oscillator, within the range of 40kHz (30kHz and 60kHz.

  • Page 35: Clock Tree

    Clock Tree Figure 4 APM32F030x6x8xC Clock Tree HSICLK HSICLK Flash programming I2C1/2 interface HSICLK HSICLK AHB/Core/ Memory//DMA AHBPSC PLLMUL PLLCLK SYSCLK HCLK HSICLK /1,2 ×2,×3 System Timer 8MHz /512 ×16 /1,/2,/ APB_CLK 4,/8,/1 /1,2 peripheral APBPSC OSC_OUT TMR1/3/6/1 HSECLK HSECLK OSC ×1,×2 4/15/16/17 4-32MHz...
  • Page 36 Clock Source Selection of RTC HSECLK/32, LSECLK or LSICLK can be selected as RTCCLK clock source by setting RTCSRCSEL bit in RCM_RTCCTRL. The selection of clock source can be changed only when the RTC domain is reset. Only when PCLK is greater than or equal to RTCCLK, can the system operate RTC normally.

  • Page 37: Low Power Mode

    circuit diagram is as follows: Figure 5 TMR14 Indirect Measurement Clock Frequency Circuit Diagram The input capture of TMR14 can select to connect the internal clock (RTCCLK, HSECLK/32, MCOCLK) of a GPIO port or a MCU by configuring RMPSEL bit of TMRx_OPT register of TMR14.

  • Page 38: Register Functional Description

    Register name Description Offset address RCM_RTCCTRL RTC domain control register 0x20 RCM_CSTS Control/State register 0x24 RCM_IORST I/O pin reset register 0x28 RCM_CFG2 Clock configuration register 2 0x2C RCM_CFG3 Clock configuration register 3 0x30 RCM_CTRL2 Clock control register 2 0x34 Register Functional Description Clock control register 1 (RCM_CTRL1) Offset address: 0x00 Reset value: 0x0000 XX83;...
  • Page 39 Field Name Description High Speed External Clock Bypass Configure Bypass mode refers to the mode in which external clock is used as the HSECLK clock source; otherwise the resonator is used as the HSECLK HSEBCFG clock source. 0: Non-bypass mode 1: Bypass mode Clock Security System Enable CSSEN...
  • Page 40 Field Name Description 1000: SYSCLK 2-divided frequency 1001: SYSCLK 4-divided frequency 1010: SYSCLK 8-divided frequency 1011: SYSCLK 16-divided frequency 1100: SYSCLK 64-divided frequency 1101: SYSCLK 128-divided frequency 1110: SYSCLK 256-divided frequency 1111: SYSCLK 512-divided frequency Note: When the prescaler factor of AHB clock is greater than 1, the prefetch buffer must be enabled.
  • Page 41 Field Name Description Main Clock Output Select Set or cleared by software. 0000: No clock output 0001: HSICLK14 is output as a clock 0010: LSICLK is output as a clock 27:24 MCOSEL 0011: LSECLK is output as a clock 0100: SYSCLK is output as a clock 0101: HSICLK is output as a clock 0110: HSECLK is output as a clock 0111: PLLCLK is output as a clock...
  • Page 42 Field Name Description Clock Security System Interrupt Flag When the external 4-16MHz oscillator clock fails, it is set to 1 by hardware. CSSFLG When CSSCLR is set to 1 by software, this bit will be cleared. 0: No security system interrupt caused by HSE clock failure 1: Clock security system interrupt is caused by HSE clock failure LSICLK Ready Interrupt Enable Enable or disable internal 40kHz RC oscillator ready interrupt.
  • Page 43 APB peripheral reset register 2 (RCM_APBRST2) Offset address: 0x0C Reset value: 0x0000 0000 Access: Access in the form of word, half word and byte, without wait cycle. All bits can be reset or cleared by software. Field Name Description SYSCFG Reset SYSCFG 0: No effect 1: Reset...
  • Page 44 APB peripheral reset register 1 (RCM_APBRST1) Offset address: 0x10 Reset value: 0x0000 0000 Access: Access in the form of word, half word and byte, without wait cycle Field Name Description Reserved Timer 3 Reset TMR3 0: No effect 1: Reset Reserved Timer 6 Reset TMR6...
  • Page 45 Field Name Description USART5 Reset USART5 0: No effect 1: Reset I2C1 Reset I2C1 0: No effect 1: Reset I2C2 Reset I2C2 0: No effect 1: Reset 27:23 Reserved Power Interface Reset 0: No effect 1: Reset 31:29 Reserved AHB peripheral clock enable register (RCM_AHBCLKEN) Offset address: 0x14 Reset value: 0x0000 0014 Access: Access in the form of word, half word and byte, without wait cycle...
  • Page 46 Field Name Description I/O PortA Clock Enable 0: Disable 1: Enable I/O PortB Clock Enable 0: Disable 1: Enable I/O PortC Clock Enable 0: Disable 1: Enable I/O PortD Clock Enable 0: Disable 1: Enable Reserved I/O PortF Clock Enable 0: Disable 1: Enable 31:23...
  • Page 47 Field Name Description TMR1 Timer Clock Enable TMR1 0: Disable 1: Enable SPI 1 Clock Enable SPI1 0: Disable 1: Enable Reserved USART1 Clock Enable USART1 0: Disable 1: Enable Reserved TMR15 Timer Clock Enable TMR15 0: Disabled 1: Enabled TMR16 Timer Clock Enable TMR16 0: Disable...
  • Page 48 Field Name Description Timer 6 Clock Enable TMR6 0: Disable 1: Enable Timer 7 Clock Enable TMR7 0: Disable 1: Enable Reserved Timer 14 Clock Enable TMR14 0: Disable 1: Enable 10:9 Reserved Window Watchdog Clock Enable WWDT 0: Disable 1: Enable 13:12 Reserved...
  • Page 49 RTC domain control register (RCM_RTCCTRL) Offset address: 0x20 Reset value: 0x0000 0018, which can be reset effectively only by RTC domain Access: Access in the form of word, half word and byte, with 0 to three wait cycles When the register is accessed continuously, the waiting state will be inserted. Note: Only when BPWEN bit in PMU_CTRL is set to 1, can LSEEN, LSEBCFG, RTCSRCSEL and RTCCLKEN be changed.
  • Page 50 Field Name Description RTC Domain Software Reset Set 1 or clear 0 by software RTCRST 0: Reset is not activated 1: Reset RTC domain (only affecting LSECLK oscillator, RTC clock and register RCM_RTCCTRL) 31:17 Reserved Control/State register (RCM_CSTS) Offset address: 0x24 Reset value: 0xXXX0 0000, except reset flag, all are cleared by system reset, and reset flag can only be cleared by power reset.
  • Page 51 Field Name Description 0: No power-on/power-down reset occurs 1: Power-on/power-down reset occurs Software Reset Occur Flag Set 1 by hardware; clear 0 by software by writing RSTFLGCLR bit. SWRSTFLG 0: Not occur 1: Occurred Independent Watchdog Reset Occur Flag When independent watchdog reset occurs in V area, it is set to 1 by hardware and cleared by software by writing IWDTRSTFLG...
  • Page 52 Field Name Description I/O Port F Reset PFRST 0: Invalid 1: Reset 31:23 Reserved Clock configuration register 2 (RCM_CFG2) Offset address: 0x2C Reset value: 0x0000 0000 Access: Access in the form of word, half word and byte, without wait cycle Field Name Description...
  • Page 53 Field Name Description HSICLK14 Enable Set 1 or clear 0 by software. HSI14EN 0: Internal 14MHz oscillator OFF 1: Internal 14MHz oscillator ON HSICLK14 Ready Flag This bit is set by hardware to indicate the state of HSICLK14 oscillator. HSI14RDFLG 0: Not ready 1: Ready ADC Interface Turn On HSICLK14...

  • Page 54: Power Management Unit (Pmu)

    Power Management Unit (PMU) Full Name and Abbreviation Description of Terms Table 21 Full Name and Abbreviation Description of Terms Full name in English English abbreviation Power Management Unit Power On Reset Power Down Reset Introduction The power supply is the foundation for stable operation of a system, with working voltage of 2.0 ~ 3.6V, and 1.5V power supply can be provided through the built-in voltage regulator.

  • Page 55: Functional Description

    Functional Description Power Domain The power domain of the product includes: V power domain, V power domain, and 1.5V power domain. 6.4.1.1 V Power Domain Power supply is provided through V pins to power the voltage regulator, standby circuit, IWDT, HSECLK, I/O (except PC13, PC14, PC15 pins) and wake-up logic.

  • Page 56: Power Consumption Control

    Figure 7 Power-on Reset and Power-down Reset Oscillogram Hysteresis voltage Hysteresis time Reset Power Consumption Control 6.4.3.1 Reduce the power consumption in low-power mode There are three low-power modes: sleep mode, stop mode and standby mode. The power consumption is reduced by closing the core and clock source and setting the voltage regulator.

  • Page 57: Stop Mode

    Effect on Effect on Voltage Mode Instruction Entry mode Wake-up mode 1.5V area area regulator clock clock Rising edge of HSECLK WKUP pin, RTC is turned PDDSCFG bit alarm event, Standby 1.5V power off +SLEEPDEEP external reset on bit +WFI or WFE NRST pin, IWDT reset Sleep mode...

  • Page 58: Register Address Mapping

    Table 25 Standby Mode Characteristics Instruction SLEEPDEEP bit of the core register is set to 1, PDDSCFG bit of the register Enter PMU_CTRL is set to 1, WUEFLG bit is set to 0 and when executing WFI or WFE instruction, the system will enter the standby mode immediately. Wake up by rising edge of WKUP pin, RTC alarm, wake-up, tamper, timestamp event Wake-up or NRST pin external reset and IWDT reset.
  • Page 59 Field Name Description 0: Write is disabed 1: Write is enabled 31:9 Reserved Power control/state register (PMU_CSTS) Offset address: 0x04 Reset value: 0x0000 000X (not cleared when waking up from standby mode) Compared with the standard APB read, it requires extra APB cycle to read this register Field Name...

  • Page 60: Nested Vector Interrupt Controller (Nvic)

    Nested Vector Interrupt Controller (NVIC) Full Name and Abbreviation Description of Terms Table 27 Full Name and Abbreviation Description of Terms Full name in English English abbreviation Non Maskable Interrupt Introduction The Cortex-M0+ core in the product integrates nested vectored interrupt controller (NVIC), which is closely coupled with the core, and can handle exceptions and interrupts and power management control efficiently and with low delay.
  • Page 61 Name Vector No. Priority Vector address Description FLASH Can be set 0x0000_004C FLASH interrupt Can be set 0x0000_0050 RCM interrupt EINT0_1 Can be set 0x0000_0054 EINT line [1:0] interrupt EINT2_3 Can be set 0x0000_0058 EINT line [3:2] interrupt EINT4_15 Can be set 0x0000_005C EINT line [15:4] interrupt 0x0000_0060...

  • Page 62: External Interrupt And Event Controller (Eint)

    External Interrupt and Event Controller (EINT) Introduction The interrupts/events contain internal interrupt/event and external interrupt/event. In this manual, external interrupt refers to the interrupt/event caused by I/O pin input signal, which is EINTx in interrupt vector table; other interrupts are internal interrupts/events.
  • Page 63 When interrupt is used for wake-up, the interrupt handler function will be triggered, and normal interrupt configuration can wake up the core. When an event is used to wake up the core, the interrupt handler function will not be triggered, which will reduce the wake-up time, and the configuration method is: （1）...

  • Page 64: Register Address Mapping

    External Interrupt and Event Channel Name External Interrupt and Event Line No. Reserved EINT 29 Reserved EINT 30 Reserved EINT 31 Note: RTC wake-up event only supports APM32F030xC Register Address Mapping Table 31 External Interrupt/Event Controller Register Mapping Register name Description Offset address EINT_IMASK...
  • Page 65 Field Name Description 1: Enable Reserved Enable the rising trigger event and interrupt on Line x (Rising Trigger Event Enable and Interrupt of Line x) 22:19 RTENx 0: Disable 1: Enable 30:23 Reserved Enable the rising trigger event and interrupt on Line 31 (Rising Trigger Event Enable and Interrupt of Line 31) RTEN31 0: Disable...
  • Page 66 Field Name Description an interrupt (event) will be generated. 0: No effect 1: Software generates an interrupt (event) Reserved Software interrupt on Line x (Software Interrupt Event on Line x) This bit can be set to 1 by software, and be cleared by writing 1 to the corresponding bit of EINT_IPEND.

  • Page 67: Direct Memory Access (Dma)

    Direct Memory Access (DMA) Introduction DMA (Direct Memory Access) can realize direct data transmission between peripheral devices and memory or between memory and memory without CPU intervention, thus saving CPU resources for other operations. DMA has a controller, which has five channels. Each channel can manage multiple DMA requests, but each channel can only start one DMA request at the same time.
  • Page 68 Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 TMR6 TMR6_UP TMR7 TMR7_UP TMR15_CH1 TMR15_UP TMR15 TMR15_TRIG TMR15_COM TMR16_CH1 TMR16_CH1 TMR16 TMR16_UP TMR16_UP TMR17_CH1 TMR17_CH1 TMR17 TMR17_UP TMR17_UP SPI1_RX SPI1_TX SPI2_RX SPI2_TX USART1_TX USART1_RX USART USART1_TX USART1_RX USART2_TX USART2_RX I2C1_TX I2C1_RX...

  • Page 69: Dma Channel

    CxS[3:0] Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 0011 SPI1_RX SPI1_TX SPI2_RX SPI2_TX 0100 TMR1_CH1 TMR1_CH2 0101 TMR3_CH1 0110 TMR3_TRIG TMR17_CH1 TMR17_CH1 TMR16_CH1 TMR16_CH1 0111 TMR17_UP TMR17_UP TMR16_UP TMR16_UP 1000 USART1_RX USART1_TX USART1_RX USART1_TX USART1_RX 1001 USART2_RX USART2_TX USART2_RX USART2_TX...
  • Page 70 Figure 10 Transmission Width with Source of 8bits and Target of 32bits Source Target Data0 Data0 Data1 Data2 Data3 Data1 Data2 Data3 Figure 11 Transmission Width with Source of 32bits and Target of 8bits Source Target Data0 Data0 Data1 Data4 Data2 Data8 Data3...
  • Page 71 Figure 12 Transmission Width with Source of 16bits and Target of 16bits Figure 13 Transmission Width with Source of 16bits and Target of 32bits Source Target Data0 Data0 Data1 Data1 Data2 Data3 Data4 Data2 Data5 Data3 Data6 Data7 Data4 Data5 Data6 Data7 www.geehy.com...
  • Page 72 Figure 14 Transmission Width with Source of 32bits and Target of 16bits Source Target Data0 Data0 Data1 Data1 Data2 Data4 Data3 Data5 Data4 Data8 Data5 Data9 Data6 DataC Data7 DataD Data8 Data9 DataA DataB DataC DataD DataE DataF 9.3.2.3 Address setting The transmission address supports two modes: fixed mode and pointer increment mode.

  • Page 73: Register Address Mapping

    to the initial value and continue DMA operation until the CIRMODE bit is cleared and the system exits the circular mode 9.3.2.5 DMA request priority setting Arbitrator When multiple DMA channel requests occur, an arbiter is needed to manage the response sequence.

  • Page 74: Register Functional Description

    DMA_CHSEL DMA channel selection register 0xA8 Register Functional Description DMA interrupt state register (DMA_INTSTS) Offset address: 0x00 Reset value: 0x0000 0000 Field Name Description ChannelxGlobal Interrupt Occur Flag (x=1…5) Indicate whether TC, HT or TE interrupt is generated on the channel; 16，...
  • Page 75 Field Name Description ChannelxHalf Transfer Complete Clear (x=1…5) 18，14， Clear the corresponding HTFLG flag in interrupt state register. HTCLRx 0: Invalid 10，6，2 1: Clear the HTFLG flag ChannelxTransfer Error Occur Clear (x=1…5) 19，15， Clear the corresponding TERRFLG flag in interrupt state register. TERRCLRx 0: Invalid 11，7，3...
  • Page 76 Field Name Description Channel Priority Level Configure 00: Low 13:12 CHPL 01: Medium 10: High 11: Highest Memory to Memory Mode Enable M2MMODE 0: Disable 1: Enable 31:15 Reserved DMA Channel x transmission quantity register (DMA_CHNDATAx) (x=1…5) Offset address: 0x0C+20 x (channel number-1) Reset value: 0x0000 0000 Field Name...
  • Page 77 Field Name Description When MSIZE= '01' (16 bits) and MEMADDR[0] bit is not used, it will be aligned with 16-bit address automatically during transmission. When MSIZE= '10' (32 bits) and MEMADDR[1:0] bit is not used, it will be aligned with 32-bit address automatically during transmission. DMA channel selection register (DMA_CHSEL) (only apply to APM32F030xC) Offset address: 0xA8...

  • Page 78: Debug Mcu (Dbgmcu)

    Debug MCU (DBGMCU) Full Name and Abbreviation Description of Terms 10.1 Table 35 Full Name and Abbreviation Description of DBGMCU Terms Full name in English English abbreviation Frame Clock FCLK Data Watchpoint Trigger Break Point Unit Introduction 10.2 APM32F030 series uses Arm ®...

  • Page 79: Functional Description

    Functional Description 10.4 （1） Realize the on-line programming and debugging of the chip （2） Using KEIL/IAR and other software to achieve on-line debugging, downloading and programming （3） Flexible implementation of production of bus-line programmer Register Address Mapping 10.5 Table 36 DBGMCU Register Address Mapping Register name Description Offset address...
  • Page 80 Field Name Description reset (the clock is provided by the 8MHz internal RC oscillator HSICLK), so the software needs to reconfigure the clock controller to start PLL, crystal oscillator, etc. 1: In the stop mode when both FCLK and HCLK are turned on, both FCLK and HCLK are provided by internal RC oscillator.
  • Page 81 Field Name Description Reserved Configure RTC Work Status When Core Is in Halted Whether RTC counter continues to work when the core RTC_STS stops work 0: Continue to work 1: Stop working Configure Window Watchdog Work Status When Core Is in Halted Whether WWDT continues to work when the core is WWDT_STS halted...
  • Page 82 Field Name Description Configure TMR17 Work Status When Core is in Halted Whether TMR17 counter continues to work when the core stops work TMR17_STS 0: Continue to work 1: Stop working 31:19 Reserved www.geehy.com Page 81...

  • Page 83: Full Name And Abbreviation Description Of Terms

    General-purpose/Alternate Function Input/Output Pin (GPIO/AFIO) Full Name and Abbreviation Description of Terms 11.1 Table 37 Full Name and Abbreviation Description of Terms Full name in English English abbreviation P-channel Metal Oxide Semiconductor P-MOS N-channel Metal Oxide Semiconductor N-MOS Main Characteristics 11.2 （1）...

  • Page 84: Structure Block Diagram

    Structure Block Diagram 11.3 Figure 16 GPIO Structure Block Diagram Push-pull, open- Write Bit set/clear drain, disable register Output data P-MOS register Read-write Output DDIOx control From on-chip Multiplexing function output peripheral N-MOS PULL I/O pin PULL Read Input data DOWN register TTL Schmitt...

  • Page 85: Output Mode

    The initial level state of pull-up/pull-down input mode is high level if pull-up, and low level if pull-down; when connecting the equipment, it is determined by the external input level and load impedance. Figure 17 I/O Structure in Input Mode Read Input data register...

  • Page 86: Multiplexing Mode

    Figure 18 I/O Structure in Output Mode DDIOx Push-pull, open-drain, Write Bit set/clear PULL disable register Output data P-MOS register Read-write Output From on-chip control Multiplexing function output peripheral I/O pin N-MOS PULL DOWN Multiplexing Mode In multiplexing mode, it can be set as push-pull multiplexing and open-drain multiplexing In push-pull/open-drain multiplexed mode: ...
  • Page 87  Weak pull-up and pull-down resistors are disabled  Read the value of the input state register to be 0 Figure 20 Analog Function I/O Structure Analog input I/O pin Analog output External Interrupt/Wake-up Line All GPIO ports have external interrupt function. If you want to use external interrupt line, the port must be configured as input mode.
  • Page 88 Remapping Each peripheral has multiple multiplexing functions, but only one multiplexing function input can be selected for a pin, so the multiplexing function of the peripheral can be mapped to other I/O pins, that is, the multiplexing function signal can be reassigned to a pin address. The multiplexing function and remapping address table of pins are shown in the data manual.

  • Page 89: Register Address Mapping

    register of Port A and Port B. If you want to write GPIOx_LOCK register, a specific write/read sequence should be transmitted. I/O configuration can be locked by configuring the lock register (GPIOx_LOCK). When a port bit executes the locking program, the configuration of port bit cannot be modified before the next reset.
  • Page 90 Field Name Description PortxPin y Mode Configure (y=0…15) 00: Input mode (state after reset) 01: Generarl output mode 31:0 MODEy[1:0] 10: Multiplexing function mode 11: Analog mode Port output mode register (GPIOx_OMODE) (x=A…D, F) Offset address: 0x04 Reset value: 0x0000 0000 Field Name Description...
  • Page 91 Port bit output data register (GPIOx_ODATA) (x=A..D, F) Offset address: 0x14 Reset value: 0x0000 0000 Field Name Description PortxPin y Output Data (y=0…15) Read and write operation can be performed by software 15:0 ODATAy For atomic bit setting/setting, the ODATAy bit can be set separately by writing GPIOx_BSC or GPIOx_BR register 31:16...
  • Page 92 Field Name Description The value of LOCKy cannot be changed during the write sequence of the operation lock key. Any error in the write sequence of operation lock key will abort the lock. After the first lock sequence on any bit of the port, any read access on the LOCKKEY bit will return "1"...
  • Page 93 Field Name Description 0110：AF6 0111：AF7 1000: Reserved 1001: Reserved 1010: Reserved 1011: Reserved 1100: Reserved 1101: Reserved 1111: Reserved 1110: Reserved Port reset register (GPIOx_BR) (x=A…D, F) Offset address: 0x28 Reset value: 0x0000 0000 Field Name Description PortxPin y Reset Configure (y=0…15) These bits can only perform write operation, and the returned value is 0x0000 when reading these bits.

  • Page 94: Timer Overview

    Timer Overview Full Name and Abbreviation Description of Terms 12.1 Table 39 Full Name and Abbreviation Description of Terms Full name in English English abbreviation Timer Update Request Event Capture Compare Length Timer Category and Main Difference 12.2 In this series of products, there are three types of timers: advanced timer, general-purpose timer and basic timer (watchdog timer is described in other chapters).
  • Page 95 Specific Advanced Basic Item content/Cate General-purpose timer timer timer gory Output channel Complement ary output 3 groups channel General DMA request PWM mode None None None Functi Single-pulse None None mode Forced output None mode Dead-time None None None insertion Timer term Table 41 Definitions and Terms of Pins Name...
  • Page 96 Name Description TIx，TI1 Timer input TIxF，TI1F Timer input filter TI1_ED Timer input edge detection TIxFPx，TI1FP1 Timer input filter polarity ICx，IC1 Input capture ICxPS，IC1PS Input capture prescaler Trigger capture Breaking signal OCx，OC1 Timer output coparison channel OCxREF，OC1REF Output compare reference signal Trigger interrupt Breaking interrupt CCxI，CC1I...

  • Page 97: Advanced Timer (Tmr1)

    Advanced Timer (TMR1) Introduction 13.1 The advanced timer TMR1 takes the time base unit as the core, and has the functions of input capture, output compare and breaking input, including a 16-bit auto load counter. The advanced timer supports complementary output, repeat count and programmable dead-time insertion function, and is more suitable for motor control.

  • Page 98: Structure Block Diagram

    Structure Block Diagram 13.3 Figure 22 TMR1 Structure Block Diagram Clock failure event Polarity TMRx_BKIN selection TMRx_CH4 TIxFP3 TMRx_CH4 OC4REF Output Channel x capture ICxPS control Prescler TIxFP4 Filter edge OC3REF TMRx_CH3 /compare register Output control detector OC3N TMRx_CH3N TMRx_CH3 TMRx_CH2 TIxFP1 TMRx_CHx...

  • Page 99: Timebase Unit

    External clock mode 2 After polarity selection, frequency division and filtering, the signal from external trigger interface (ETR) is connected to slave mode controller through trigger input selector to control the work of counter. Internal trigger input The timer is set to work in slave mode, and the clock source is the output signal of other timers.
  • Page 100 Figure 23 Timing Diagram when Division Factor is 1 or 2 in Count-up Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter overrun Update event PSC=2 CK_CNT 0000 0002 0003 0024 0025 0001 0026 Counter register Counter overrun Update event Count-down mode Set to the count-down mode by CNTDIR bit of configuration control register (TMRx_CTRL1).

  • Page 101: Center-Aligned Mode

    Figure 24 Timing Diagram when Division Factor is 1 or 2 in Count-down Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter overrun Update event PSC=2 CK_CNT 0001 0026 0024 0023 0002 0025 0000 Counter register Counter overrun Update event Center-aligned mode Set to the center-aligned mode by CNTDIR bit of configuration control register (TMRx_CTRL1).
  • Page 102 Figure 25 Timing Diagram when Division Factor is 1 or 2 in Center-aligned Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter underrun Counter overrun Update event PSC=2 CK_CNT 0003 0003 0002 0000 0001 0002 0001 Counter register Counter overrun Update event Repeat counter REPCNT There is no repeat counter REPCNT in the basic/general-purpose timer, which means that when the overrun event or underrun event occurs in the...

  • Page 103: Input Capture

    Figure 26 Timing Diagram when Setting REPCNT=2 in Count-up Mode CK_CNT Counter overrun Update event Prescaler PSC The 16-bit programmable prescaler can divide the clock frequency of the counter by any value from 1 to 65536 (controlled by TMRx_PSC register). The clock after frequency division will drive the counter CNT to count.

  • Page 104: Output Compare

    In capture mode, the timing, frequency, period and duty cycle of a waveform can be measured. In the input capture mode, the edge selection is set to rising edge detection. When the rising edge appears on the capture channel, the first capture occurs, at this time, the value of the counter CNT will be latched in the capture register CCx;...
  • Page 105 Set the timing diagram in PWM mode 1 when CCx=5, AUTORLD=7 Figure 27 PWM1 Count-up Mode Timing Diagram AUTORLD 0CxREF Figure 28 PWM1 Count-down Mode Timing Diagram AUTORLD 0CxREF Figure 29 PWM1 Center-aligned Mode Timing Diagram AUTORLD 0CxREF In PWM mode 2, if the value of the counter CNT is less than that of the compare register CCx, the output level will be invalid;...

  • Page 106: Pwm Input Mode

    Set the timing diagram in PWM mode 2 when CCx=5, AUTORLD=7 Figure 30 PWM2 Count-up Mode Timing Diagram AUTORLD 0CxREF Figure 31 PWM2 Count-down Mode Timing Diagram AUTORLD 0CxREF Figure 32 PWM2 Center-aligned Mode Timing Diagram AUTORLD 0CxREF PWM Input Mode PWM input mode is a particular case of input capture.

  • Page 107: Single-Pulse Mode

    In the PWM input mode, the PWM signal enters from TMRx_CH1, and the signal will be divided into two channels, one can measure the cycle and the other can measure the duty cycle. In the configuration, it is only required to set the polarity of one channel, and the other will be automatically configured with the opposite polarity.
  • Page 108 Figure 34 Timing Diagram in Single-pulse Mode AUTORLD DELAY PULSE OCxREF Impact of the Register on Output Waveform The following registers will affect the level of the timer output waveform. For details, please refer to "Register Functional Description". （1） CCxEN and CCxNEN bits in TMRx_CCEN register ...
  • Page 109 Figure 35 Register Structural Relationship Affecting Output Waveform CCxEN/CCxNEN=1 Normal output RMOS=1 Off state/Invalid state (OFF state), CCxEN/CCxNEN=0 output level is controlled by polarity; MOEN=1 output invalid level run mode, run mode CCxEN/CCxNEN=1 Normal output RMOS=0 Output disable, output disabled, CCxEN/CCxNEN=0 output 0 Output...

  • Page 110: Forced Output Mode

    Complementary Output and Dead-time Insertion TMR 1 timer has three groups of complementary ouptut channels. The insertion dead time is used to generate complementary output signals to ensure that the two-way complementary signals of channels will not be valid at the same time. The dead time is set according to the output device connected to the timer and its characteristics The duration of the dead-time can be controlled by configuring DTS bit of...
  • Page 111 The two input TI1 and TI2 can be used as the interface of incremental encoder. The counter is driven by the effective jump of the signals TI1FP1 and TI2FP2 after filtering and edge selection in TI1 and TI2. The count pulse and direction signal are generated according to the input signals of TI1 and TI2 ...

  • Page 112: Slave Mode

    Figure 39 Example of Encoder Interface Mode of IC1FP1 Reversed Phase Counter For example, when TI1 is at low level, and the rising edge of TI2 jumps, the counter will count down. Slave Mode TMR1 timer can synchronize external trigger ...
  • Page 113 Figure 40 Interconnection between TMR1 and Other Timer Master Slave timer timer TRGO TMR15 ITR0 Master mode TS=000 controller TMR3 TRGO ITR2 TMR1 Master mode TS=010 Slave mode controller controller TMR17 TRGO ITR3 Master mode TS=011 controller When the timers are interconnected: ...

  • Page 114: Register Address Mapping

    Figure 41 OCxREF Timing Diagram ETRF OCxREF OCxCEN=0 Set TMR1 to PWM mode, close the external trigger prescaler, and disable the external trigger mode 2; when ETRF input is high, set OCxCEN=1, and the output OCxREF signal is shown in the figure below. Figure 42 OCxREF Timing Diagram ETRF OCxREF...

  • Page 115: Register Functional Description

    Register name Description Offset address TMRx_PSC Prescaler register 0x28 TMRx_AUTORLD Auto reload register 0x2C TMRx_REPCNT Repeat count register 0x30 TMRx_CC1 Channel 1 capture/compare register 0x34 TMRx_CC2 Channel 2 capture/compare register 0x38 TMRx_CC3 Channel 3 capture/compare register 0x3C TMRx_CC4 Channel 4 capture/compare register 0x40 TMRx_BDT Break and dead-time register...
  • Page 116 Field Name Description Counter Direction This bit is read-only when the counter is configured as center-aligned mode or encoder mode. CNTDIR 0: Count up 1: Count down Center Aligned Mode Select) In the center-aligned mode, the counter counts up and down alternately; otherwise, it will only count up or down.
  • Page 117 Field Name Description Capture/compare DMA Select CCDSEL 0: Send DMA request of CCx when CCx event occurs 1: Send DMA request of CCx when an update event occurs Master Mode Signal Select The signals of timers working in master mode can be used for TRGO, which affects the work of timers in slave mode and cascaded with master timer, and specifically affects the configuration of timers in slave mode.
  • Page 118 Field Name Description 011: Encoder mode 3; according to the input level of another signal, the counter counts at the edge of TI1FP1 and TI2FP2. 100: Reset mode; the slave mode timer resets the counter after receiving the rising edge signal of TRGI and generates the signal to update the register.
  • Page 119 Field Name Description 1111：DIV=32，N=8 Sampling frequency=timer clock frequency/DIV; the filter length=N, and a jump is generated by every N events. External Trigger Prescaler Configure The ETR (external trigger input) signal becomes ETRP after frequency division. The signal frequency of ETRP is at most 1/4 of TMR1CLK frequency;...
  • Page 120 Field Name Description 1: Enable Capture/Compare Channel4 Interrupt Enable CC4IEN 0: Disable 1: Enable COM Interrupt Enable COMIEN 0: Disable 1: Enable Trigger interrupt Enable TRGIEN 0: Disable 1: Enable Break interrupt Enable BRKIEN 0: Disable 1: Enable Update DMA Request Enable UDIEN 0: Disable 1: Enable...
  • Page 121 Field Name Description situations: (1) UD=0 on TMRx_CTRL1 register, and when the value of the repeat counter overruns/underruns, an update event will be generated; (2) URSSEL=0 and UD=0 on TMRx_CTRL1 register, configure UEG=1 on TMRx_CEG register to generate update event, and the counter needs to be initialized by software;...
  • Page 122 Field Name Description Update Event Generate 0: Invalid 1: Initialize the counter and generate the update event This bit is set to 1 by software, and cleared by hardware. Note: When an update event is generated, the counter of the prescaler will be cleared, but the prescaler factor remains unchanged.

  • Page 123: Output Compare Mode

    and input mode. The OCxx in the register describes the function of the channel in the output mode, and the ICxx in the register describes the function of the channel in the input mode. Output compare mode: Field Name Description Capture/Compare Channel 1 Select This bit defines the input/output direction and the selected input pin.

  • Page 124: Input Capture Mode

    Field Name Description 10: CC2 channel is input, and IC2 is mapped on TI1 11: CC2 channel is input, and IC2 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is disabled (TMRx_CCEN register CC2EN=0).
  • Page 125 Field Name Description 01: CC2 channel is input, and IC2 is mapped on TI1 10: CC2 channel is input, and IC2 is mapped on TI2 11: CC2 channel is input, and IC2 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is disabled (TMRx_CCEN register CC2EN=0).
  • Page 126 Field Name Description Capture/Compare Channel 3 Select 00: CC3 channel is output 01: CC3 channel is input, and IC3 is mapped on TI3 10: CC3 channel is input, and IC3 is mapped on TI4 CC3SEL 11: CC3 channel is input, and IC3 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is disabled (TMRx_CCEN register CC3EN=0).
  • Page 127 Field Name Description 00: Non-phase-inverting/rising edge: TIxFP1 is not reversed phase (triggered in gated and encoder mode), and is captured at the rising edge of TIxFP1 (reset trigger, capture, external clock and trigger mode). 01: Inverted phase/Falling edge: TIxFP1 is reversed phase (triggered in gated and encoder mode), and is captured at the rising edge of TIxFP1 (reset trigger, capture, external clock and trigger mode).
  • Page 128 Field Name Description Capture/Compare Channel4 Output Polarity CC4POL Refer to CCEN_CC1POL 15:14 Reserved Counter register (TMRx_CNT) Offset address: 0x24 Reset value: 0x0000 Field Name Description 15:0 Counter Value Prescaler register (TMRx_PSC) Offset address: 0x28 Reset value: 0x0000 Field Name Description Prescaler Value 15:0 Clock frequency of counter (CK_CNT)＝f...
  • Page 129 Field Name Description When the output compare preload is disabled (OC1PEN=0 for TMRx_CCM1 register), the written value will immediately affect the output compare results; If the output compare preload is enabled (OC1PEN=1 for TMRx_CCM1 register), the written value will affect the output compare result when an update event is generated.
  • Page 130 Field Name Description Note: Once LOCK level (LOCKCFG bit in TMRx_BDT register) is set to 1, 2 or 3, these bits cannot be modified. Lock Write Protection Mode Configure 00: Without Lock write protection level; the register can be written directly 01: Lock write protection level 1 It cannot be written to DTS, BRKEN, BRKPOL and AOEN bits of TMRx_BDT, and OCxOIS and OCxNOIS bits of TMRx_CTRL2 register.
  • Page 131 Field Name Description DMA Base Address Setup These bits define the base address of DMA in continuous mode (when reading or writing TMRx_DMADDR register), and DBADDR is defined as DBADDR the offset from the address of TMRx_CTRL1 register: 00000：TMRx_CTRL1 00001：TMRx_CTRL2 00010：TMRx_SMCTRL Reserved DMA Burst Transfer Length Setup...

  • Page 132: General-Purpose Timer (Tmr3)

    General-purpose Timer (TMR3) Introduction 14.1 The general-purpose timer takes the time base unit as the core, and has the functions of input capture and output compare, and can be used to measure the pulse width, frequency and duty cycle, and generate the output waveform. It includes a 16-bit auto reload counter (realize count-up, count-down and center-aligned count).

  • Page 133: Structure Block Diagram

    Structure Block Diagram 14.3 Figure 43 General-purpose Timer TMR3 Structure Block Diagram TIxFP3 TMRx_CH4 Channel 1 capture ICxPS OCxREF Output Prescler TMRx_CHx Filter TIxFP4 control /compare register edge detector TMRx_CH3 TMRx_CH2 TIxFP1 ICxPS Filter OCxREF Output Channel 1 capture Prescler TMRx_CHx TIxFP2 edge...

  • Page 134: Timebase Unit

    External clock mode 2 After polarity selection, frequency division and filtering, the signal from external trigger interface (ETR) is connected to slave mode controller through trigger input selector to control the work of counter. Internal trigger input The timer is set to work in slave mode, and the clock source is the output signal of other timers.
  • Page 135 Figure 44 Timing Diagram when Division Factor is 1 or 2 in Count-up Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter overrun Update event PSC=2 CK_CNT 0000 0002 0003 0024 0025 0001 0026 Counter register Counter overrun Update event Count-down mode Set to the count-down mode by CNTDIR bit of configuration control register (TMRx_CTRL1).

  • Page 136: Center-Aligned Mode

    Figure 45 Timing Diagram when Division Factor is 1 or 2 in Count-down Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter overrun Update event PSC=2 CK_CNT 0001 0026 0024 0023 0002 0025 0000 Counter register Counter overrun Update event Center-aligned mode Set to the center-aligned mode by CNTDIR bit of configuration control register (TMRx_CTRL1).

  • Page 137: Input Capture

    Figure 46 Timing Diagram when Division Factor is 1 or 2 in Center-aligned Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter underrun Counter overrun Update event PSC=2 CK_CNT 0003 0003 0002 0000 0001 0002 0001 Counter register Counter overrun Update event Prescaler PSC The prescaler is 16 bits and programmable, and it can divide the clock frequency of the counter to any value between 1 and 65536 (controlled by TMRx_PSC...

  • Page 138: Output Compare

    Input capture application Input capture is used to capture external events, and can give the time flag to indicate the occurrence time of the event and measure the pulse jump edge events (measure the frequency or pulse width), for example, if the selected edge appears on the input pin, the TMRx_CCx register will capture the current value of the counter and the CCxIFLG bit of the state register TMRx_STS will be set to 1;...
  • Page 139 Set the timing diagram in PWM mode 1 when CCx=5, AUTORLD=7 Figure 47 PWM1 Count-up Mode Timing Diagram AUTORLD 0CxREF Figure 48 PWM1 Count-down Mode Timing Diagram AUTORLD 0CxREF Figure 49 PWM1 Center-aligned Mode Timing Diagram AUTORLD 0CxREF www.geehy.com Page 138...
  • Page 140 In PWM mode 2, if the value of the counter CNT is less than that of the compare register CCx, the output level will be invalid; otherwise, it will be valid. Set the timing diagram in PWM mode 2 when CCx=5, AUTORLD=7 Figure 50 PWM2 Count-up Mode Timing Diagram AUTORLD 0CxREF...

  • Page 141: Single-Pulse Mode

    PWM Input Mode PWM input mode is a particular case of input capture. In PWM input mode, as only TI1FP1 and TI1FP2 are connected to the slave mode controller, input can be performed only through the channels TMRx_CH1 and TMRx_CH2, which need to occupy the capture registers of CH1 and CH2. In the PWM input mode, the PWM signal enters from TMRx_CH1, and the signal will be divided into two channels, one can measure the cycle and the other can measure the duty cycle.

  • Page 142: Forced Output Mode

    Figure 54 Timing Diagram in Single-pulse Mode AUTORLD DELAY PULSE OCxREF Forced Output Mode In the forced output mode, the compare result is ignored, and the corresponding level is directly output according to the configuration instruction.  CCxSEL=00 for TMRx_CCMx register, set CCx channel as output ...
  • Page 143 Table 46 Relationship between Count Direction and Encoder Count in both TI1 and Effective edge Count only in TI1 Count only in TI2 Level of relative signal High High High Count Count Rising edge Count up Count up down down TI1FP1 —...
  • Page 144 Figure 56 Example of Encoder Interface Mode of IC1FP1 Reversed Phase Counter For example, when TI1 is at low level, and the rising edge of TI2 jumps, the counter will count down. Slave Mode TMR3 timer can synchronize external trigger ...
  • Page 145 Figure 57 Interconnection of TMR3 and Other Timers Master Slave timer timer TMR1 TRGO ITR0 Master mode TS=000 controller TMR15 TRGO ITR2 TMR3 Master mode TS=010 Slave mode controller controller TMR14 TRGO ITR3 Master mode TS=011 controller When the timers are interconnected: ...

  • Page 146: Register Address Mapping

    Figure 58 OCxREF Timing Diagram ETRF OCxREF OCxCEN=0 Set TMR3 to PWM mode, close the external trigger prescaler, and disable the external trigger mode 2; when ETRF input is high, set OCxCEN=1, and the output OCxREF signal is shown in the figure below. Figure 59 OCxREF Timing Diagram ETRF OCxREF...

  • Page 147: Register Functional Description

    Register name Description Offset address TMRx_PSC Prescaler register 0x28 TMRx_AUTORLD Auto reload register 0x2C TMRx_CC1 Channel 1 capture/compare register 0x34 TMRx_CC2 Channel 2 capture/compare register 0x38 TMRx_CC3 Channel 3 capture/compare register 0x3C TMRx_CC4 Channel 4 capture/compare register 0x40 TMRx_DCTRL DMA control register 0x48 TMRx_DMADDR DMA address register of continuous mode...
  • Page 148 Field Name Description 0: Count up 1: Count down Center Aligned Mode Select) In the center-aligned mode, the counter counts up and down alternately; otherwise, it will only count up or down. Different center-aligned modes affect the timing of setting the output compare interrupt flag bit of the output channel to 1;...
  • Page 149 Field Name Description 111: Comparison mode 4; OC4REF is used to trigger TRGO Timer Input 1 Select 0: TMRx_CH1 pin is connected to TI1 input TI1SEL 1: TMRx_CH1, TMRx_CH2 and TMRx_CH3 pins are connected to TI1 input after exclusive 15:8 Reserved Slave mode control register (TMRx_SMCTRL) Offset address: 0x08...
  • Page 150 Field Name Description External Trigger Filter Configure 0000: Filter disabled, sampling by f 0001：DIV=1，N=2 0010：DIV=1，N=4 0011：DIV=1，N=8 0100：DIV=2，N=6 0101：DIV=2，N=8 0110：DIV=4，N=6 0111：DIV=4，N=8 11:8 ETFCFG 1000：DIV=8，N=6 1001：DIV=8，N=8 1010：DIV=16，N=5 1011：DIV=16，N=6 1100：DIV=16，N=8 1101：DIV=32，N=5 1110：DIV=32，N=6 1111：DIV=32，N=8 Sampling frequency=timer clock frequency/DIV; the filter length=N, and a jump is generated by every N events. External Trigger Prescaler Configure The ETR (external trigger input) signal becomes ETRP after frequency division.
  • Page 151 Field Name Description Update interrupt Enable UIEN 0: Disable 1: Enable Capture/Compare Channel1 Interrupt Enable CC1IEN 0: Disable 1: Enable Capture/Compare Channel2 Interrupt Enable CC2IEN 0: Disable 1: Enable Capture/Compare Channel3 Interrupt Enable CC3IEN 0: Disable 1: Enable Capture/Compare Channel4 Interrupt Enable CC4IEN 0: Disable 1: Enable...
  • Page 152 Field Name Description by software; update events are generated in the following situations: (1) UD=0 on TMRx_CTRL1 register, and when the value of the repeat counter overruns/underruns, an update event will be generated; (2) URSSEL=0 and UD=0 on TMRx_CTRL1 register, configure UEG=1 on TMRx_CEG register to generate update event, and the counter needs to be initialized by software;...
  • Page 153 Control event generation register (TMRx_CEG) Offset address: 0x14 Reset value: 0x0000 Field Name Description Update Event Generate 0: Invalid 1: Initialize the counter and generate the update event This bit is set to 1 by software, and cleared by hardware. Note: When an update event is generated, the counter of the prescaler will be cleared, but the prescaler factor remains unchanged.
  • Page 154 Field Name Description 11: CC1 channel is input, and IC1 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is disabled (TMRx_CCEN register CC1EN=0). Output Compare Channel1 Fast Enable 0: Disable 1: Enable OC1FEN...

  • Page 155: Input Capture Mode

    Field Name Description OC2CEN Output Compare Channel2 Clear Enable Input capture mode: Field Name Description Capture/Compare Channel 1 Select 00: CC1 channel is output 01: CC1 channel is input, and IC1 is mapped on TI1 10: CC1 channel is input, and IC1 is mapped on TI2 CC1SEL 11: CC1 channel is input, and IC1 is mapped on TRC, and only works in internal trigger input...
  • Page 156 Output compare mode: Field Name Description Capture/Compare Channel 1 Select This bit defines the input/output direction and the selected input pin. 00: CC3 channel is output 01: CC3 channel is input, and IC3 is mapped on TI3 CC3SEL 10: CC3 channel is input, and IC3 is mapped on TI4 11: CC3 channel is input, and IC3 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is disabled...
  • Page 157 Field Name Description IC3F Input Capture Channel 3 Filter Configure Capture/Compare Channel 4 Select 00: CC4 channel is output 01: CC4 channel is input, and IC4 is mapped on TI4 10: CC4 channel is input, and IC4 is mapped on TI3 CC4SEL 11: CC4 channel is input, and IC4 is mapped on TRC, and only works in internal trigger input...
  • Page 158 Field Name Description captured signals TI1FP1 and TI2FP1 for the same time. Capture/Compare Channel2 Output Enable CC2EN Refer to CCEN_CC1EN Capture/Compare Channel2 Output Polarity Configure CC2POL Refer to CCEN_CC1POL Reserved Capture/Compare Channel2 Output Polarity Configure CC2NPOL Refer to CCEN_CC1NPOL Capture/Compare Channel3 Output Enable CC3EN Refer to CCEN_CC1EN Capture/Compare Channel3 Output Polarity Configure...
  • Page 159 Field Name Description Auto Reload Value 15:0 AUTORLD When the value of auto reload is empty, the counter will not count. Channel 1 capture/compare register (TMRx_CC1) Offset address: 0x34 Reset value: 0x0000 Field Name Description Capture/Compare Channel 1 Value When the capture/compare channel 1 is configured as input mode: CC1 contains the counter value transmitted by the last input capture channel 1 event.
  • Page 160 Field Name Description These bits define the base address of DMA in continuous mode (when reading or writing TMRx_DMADDR register), and DBADDR is defined as the offset from the address of TMRx_CTRL1 register: 00000：TMRx_CTRL1 00001：TMRx_CTRL2 00010：TMRx_SMCTRL ……. Reserved DMA Burst Transfer Length Setup These bits define the transfer length and transfer times of DMA in continuous mode.

  • Page 161: General-Purpose Timer (Tmr14)

    General-purpose Timer (TMR14) Introduction 15.1 The general-purpose timer takes the time base unit as the core, and has the functions of input capture and output compare, and can be used to measure the pulse width, frequency and duty cycle, and generate the output waveform. It includes a 16-bit auto reload counter (realize count-up, count-down and center-aligned count).

  • Page 162: Functional Description

    Functional Description 15.4 Clock Source Internal clock It is TMRx_CLK from RCM, namely the driving clock of the timer; when the slave mode controller is disabled, the clock source CK_PSC of the prescaler is driven by the internal clock CK_INT. Timebase Unit The time base unit in the general-purpose timer contains three registers ...
  • Page 163 Figure 61 Timing Diagram when Division Factor is 1 or 2 in Count-up Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter overrun Update event PSC=2 CK_CNT 0000 0002 0003 0024 0025 0001 0026 Counter register Counter overrun Update event Count-down mode Set to the count-down mode by CNTDIR bit of configuration control register (TMRx_CTRL1).

  • Page 164: Center-Aligned Mode

    Figure 62 Timing Diagram when Division Factor is 1 or 2 in Count-down Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter overrun Update event PSC=2 CK_CNT 0001 0026 0024 0023 0002 0025 0000 Counter register Counter overrun Update event Center-aligned mode Set to the center-aligned mode by CNTDIR bit of configuration control register (TMRx_CTRL1).
  • Page 165 The figure below is Timing Diagram when Division Factor is 1 or 2 in Center-aligned Mode Figure 63 Timing Diagram when Division Factor is 1 or 2 in Center-aligned Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter underrun Counter overrun Update event PSC=2 CK_CNT...

  • Page 166: Output Compare

    Input capture application Input capture is used to capture external events, and can give the time flag to indicate the occurrence time of the event and measure the pulse jump edge events (measure the frequency or pulse width), for example, if the selected edge appears on the input pin, the TMRx_CCx register will capture the current value of the counter and the CCxIFLG bit of the state register TMRx_STS will be set to 1;...
  • Page 167 Set the timing diagram in PWM mode 1 when CCx=5, AUTORLD=7 Figure 64 PWM1 Count-up Mode Timing Diagram AUTORLD 0CxREF Figure 65 PWM1 Count-down Mode Timing Diagram AUTORLD 0CxREF Figure 66 PWM1 Center-aligned Mode Timing Diagram AUTORLD 0CxREF www.geehy.com Page 166...
  • Page 168 In PWM mode 2, if the value of the counter CNT is less than that of the compare register CCx, the output level will be invalid; otherwise, it will be valid. Set the timing diagram in PWM mode 2 when CCx=5, AUTORLD=7 Figure 67 PWM2 Count-up Mode Timing Diagram AUTORLD 0CxREF...

  • Page 169: Forced Output Mode

    Forced Output Mode In the forced output mode, the compare result is ignored, and the corresponding level is directly output according to the configuration instruction.  CCxSEL=00 for TMRx_CCMx register, set CCx channel as output  OCxMOD=100/101 for TMRx_CCMx register, set to force OCxREF signal to invalid/valid state In this mode, the corresponding interrupt and DMA request will still be generated.
  • Page 170 Field Name Description 1: Update event is disabled Update Request Source Select If interrupt or DMA is enabled, the update event can generate update interrupt or DMA request. Different update request sources can be selected through this bit. URSSEL 0: The counter overruns or underruns Set UEG bit Update generated by slave mode controller 1: The counter overruns or underruns...

  • Page 171: Output Compare Mode

    Field Name Description Capture/Compare Channel1 Interrupt Flag When the capture/compare channel 1 is configured as output: 0: No matching occurred 1: The value of TMRx_CNT matches the value of TMRx_CC1 When the capture/compare channel 1 is configured as input: CC1IFLG RC_W0 0: Input capture did not occur 1: Input capture occurred...

  • Page 172: Input Capture Mode

    Field Name Description 00: CC1 channel is output 01: CC1 channel is input, and IC1 is mapped on TI1 10: CC1 channel is input, and IC1 is mapped on TI2 11: CC1 channel is input, and IC1 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is disabled (TMRx_CCEN register CC1EN=0).
  • Page 173 Field Name Description 0001：DIV=1，N=2 0010：DIV=1，N=4 0011：DIV=1，N=8 0100：DIV=2，N=6 0101：DIV=2，N=8 0110：DIV=4，N=6 0111：DIV=4，N=8 1000：DIV=8，N=6 1001：DIV=8，N=8 1010：DIV=16，N=5 1011：DIV=16，N=6 1100：DIV=16，N=8 1101：DIV=32，N=5 1110：DIV=32，N=6 1111：DIV=32，N=8 Sampling frequency=timer clock frequency/DIV; the filter length=N, indicating that a jump is generated by every N events. 15:8 Reserved Capture/Compare enable register (TMRx_CCEN) Offset address: 0x20 Reset value: 0x0000 Field...
  • Page 174 Field Name Description When CC1 channel is configured as input: Then CC1NPOL and CC1POL control the polarity of the triggered or captured signals TI1FP1 and TI2FP1 for the same time. Reserved 15:4 Table 51 Output Control Bit of Standard OCx Channel CCxEN bit OCx output state Output is disabled (OCx=0, OCx_EN=0)
  • Page 175 Field Name Description register), the written value will affect the output compare result when an update event is generated. Option register (TMRx_OPT) Offset address: 0x50 Reset value: 0x0000 Field Name Description Timer Input 1 Remap Select 00: TMR14 channel 1 is connected to GPIO. Refer to the data manual. 01: TMR14 channel 1 is connected to RTCCLK RMPSEL 10: TMR14 channel 1 is connected to HSECLK/32...

  • Page 176: General-Purpose Timer (Tmr15/16/17)

    General-purpose Timer (TMR15/16/17) Introduction 16.1 The general-purpose timer takes the time base unit as the core, and has the functions of input capture and output compare, and can be used to measure the pulse width, frequency and duty cycle, and generate the output waveform. It includes a 16-bit auto reload counter (realize count-up, count-down and center-aligned count).

  • Page 177: Structure Block Diagram

    Structure Block Diagram 16.3 General-purpose Timer TMR15 Structure Block Diagram Figure 70 General-purpose Timer TMR15 Structure Block Diagram Clock failure event TMRx_BKIN Polarity selection TI1FP1 Filter and TMRx_CH1 IC1PS Channel 1 capture/ Output OC1REF TI1FP2 TMRx_CH1 edge Prescaler OC1N control compare register TMRx_CH1N detector...

  • Page 178: Functional Description

    Functional Description 16.4 Clock Source Selection The general-purpose timer has four clock sources Internal clock It is TMRx_CLK from RCM, namely the driving clock of the timer; when the slave mode controller is disabled, the clock source CK_PSC of the prescaler is driven by the internal clock CK_INT.
  • Page 179 Figure 72 Timing Diagram when Division Factor is 1 or 2 in Count-up Mode CK_PSC CNT_EN PSC=1 CK_CNT Counter register Counter overrun Update event PSC=2 CK_CNT 0000 0002 0003 0024 0025 0001 0026 Counter register Counter overrun Update event Repeat counter REPCNT There is no repeat counter REPCNT in the basic/general-purpose timer, which means that when the overrun event or underrun event occurs in the basic/general-purpose timer, an update event will be generated directly;...
  • Page 180 The figure below shows the Timing Diagram when Setting REPCNT=2 in Count-up Mode Figure 73 Timing Diagram when Setting REPCNT=2 in Count-up Mode CK_CNT Counter overrun Update event Prescaler PSC The prescaler is 16 bits and programmable, and it can divide the clock frequency of the counter to any value between 1 and 65536 (controlled by TMRx_PSC register), and after frequency division, the clock will drive the counter CNT to count.
  • Page 181 Output Compare There are eight modes of output compare: freeze, channel x is valid level when matching, channel x is invalid level when matching, flip, force is invalid, force is valid, PWM1 and PWM2 modes, which are configured by OCxMOD bit in TMRx_CCMx register and can control the waveform of output signal in output compare mode.
  • Page 182 Set the timing diagram in PWM mode 1 when CCx=5, AUTORLD=7 Figure 74 PWM1 Count-up Mode Timing Diagram AUTORLD 0CxREF Figure 75 PWM1 Count-down Mode Timing Diagram AUTORLD 0CxREF Figure 76 PWM1 Center-aligned Mode Timing Diagram AUTORLD 0CxREF www.geehy.com Page 181...
  • Page 183 In PWM mode 2, if the value of the counter CNT is less than that of the compare register CCx, the output level will be invalid; otherwise, it will be valid. Set the timing diagram in PWM mode 2 when CCx=5, AUTORLD=7 Figure 77 PWM2 Count-up Mode Timing Diagram AUTORLD 0CxREF...
  • Page 184 PWM Input Mode (only applicable to TMR15) PWM input mode is a particular case of input capture. In PWM input mode, as only TI1FP1 and TI1FP2 are connected to the slave mode controller, input can be performed only through the channels TMRx_CH1 and TMRx_CH2, which need to occupy the capture registers of CH1 and CH2.
  • Page 185 Figure 81 Timing Diagram in Single-pulse Mode AUTORLD DELAY PULSE OCxREF Impact of the Register on Output Waveform The following registers will affect the level of the timer output waveform. For details, please refer to "Register Functional Description". （1） CCxEN and CCxNEN bits in TMRx_CCEN register ...
  • Page 186 Figure 82 Register Structural Relationship Affecting Output Waveform CCxEN/CCxNEN=1 Normal output RMOS=1 Off state/Invalid state (OFF state), CCxEN/CCxNEN=0 output level is controlled by polarity; output invalid level MOEN=1 run mode run mode CCxEN/CCxNEN=1 Normal output RMOS=0 Output disable, output disabled, CCxEN/CCxNEN=0 output 0 Output...
  • Page 187 Complementary Output and Dead-time Insertion Timers 15/16/17 have three groups of complementary ouptut channels. The insertion dead time is used to generate complementary output signals to ensure that the two-way complementary signals of channels will not be valid at the same time.
  • Page 188 In the gated mode, the enable of the counter depends on the high level of the selected input. When the trigger input is high, the clock of the counter will be started. Once the trigger input becomes low, the counter will stop (but not be reset).

  • Page 189: Tmr15 Register Address Mapping

    TMR15 Register Address Mapping 16.5 In the following table, all registers of TMR15 are mapped to a 16-bit addressable (address) space. Table 52 TMR15 Register Address Mapping Register name Description Offset address TMR15_CTRL1 Control register 1 0x00 TMR15_CTRL2 Control register 2 0x04 TMR15_SMCTRL Slave mode control register...
  • Page 190 Field Name Description The counter overruns/underruns; Set UEG bit; Update generated by slave mode controller. 1: Update event is disabled Update Request Source Select If interrupt or DMA is enabled, the update event can generate update interrupt or DMA request. Different update request sources can be selected through this bit.
  • Page 191 Field Name Description Capture/compare DMA Select 0: Send DMA request of CCx when CCx event occurs CCDSEL 1: Send DMA request of CCx when an update event occurs Master Mode Signal Select The signals of timers working in master mode can be used for TRGO, which affects the work of timers in slave mode and cascaded with master timer, and specifically affects the configuration of timers in slave mode.
  • Page 192 Field Name Description when receiving TRGI low level; when receiving TRGI high level signal again, the timer will continue to work; the counter is not reset during the whole period. 110: Trigger mode, the slave mode timer starts the counter to work after receiving the rising edge signal of TRGI.
  • Page 193 Field Name Description 1: Enable Capture/Compare Channel1 DMA Request Enable CC1DEN 0: Disable 1: Enable Capture/Compare Channel2 DMA Request Enable CC2DEN 0: Disable 1: Enable 13:11 Reserved Trigger DMA Request Enable TRGDEN 0: Disable 1: Enable Reserved State register (TMR15_STS) Offset address: 0x10 Reset value: 0x0000 Field...
  • Page 194 Field Name Description After Trigger event is generated, this bit is set to 1 by hardware and cleared by software. Break Event Interrupt Generate Flag Bit 0: Break event does not occur BRKIFLG RC_W0 1: Break event occurs When break input is valid, this bit is set to 1 by hardware; when break input is invalid, this bit can be cleared by software.

  • Page 195: Output Compare Mode

    Field Name Description 1: Trigger event is generated This bit is set to 1 by software and cleared automatically by hardware. Break Event Generate 0: Invalid 1: Break event is generated This bit is set to 1 by software and cleared automatically by hardware. 15:8 Reserved Capture/Compare mode register (TMR15_CCM1)

  • Page 196: Input Capture Mode

    Field Name Description the value of the capture/registerregister, flap the level of OC1REF 100: The output is forced to be ow Force OC1REF to be at low level 101: The output is forced to be high. Force OC1REF to be at high level 110: PWM mode 1 (set to high when the counter value<output compare value;...
  • Page 197 Field Name Description 1001：DIV=8，N=8 1010：DIV=16，N=5 1011：DIV=16，N=6 1100：DIV=16，N=8 1101：DIV=32，N=5 1110：DIV=32，N=6 1111：DIV=32，N=8 Sampling frequency=timer clock frequency/DIV; the filter length=N, indicating that a jump is generated by every N events. Capture/Compare Channel 2 Select 00: CC2 channel is output 01: CC2 channel is input, and IC2 is mapped on TI1 10: CC2 channel is input, and IC2 is mapped on TI2 CC2SEL 11: CC2 channel is input, and IC2 is mapped on TRC, and only works in...
  • Page 198 Field Name Description 11: Non-phase-inverting/Rising and falling edges: TIxFP1 is not reversed phase (triggered in gated mode, cannot be used in encoder mode), and is captured at the rising edge of TIxFP1 (reset trigger, capture, external clock and trigger mode). Capture/Compare Channel1 Complementary Output Enable CC1NEN 0: Disable...
  • Page 199 Field Name Description Repetition Counter Value When the count value of the repeat counter is reduced to 0, an update event REPCNT will be generated, and the counter will start counting again from the REPCNT value; the new value newly written to this register is valid only when an update event occurs in next cycle.
  • Page 200 Field Name Description 2 or 3, these bits cannot be modified. Lock Write Protection Mode Configure 00: Without Lock write protection level; the register can be written directly 01: Lock write protection level 1 It cannot be written to DTS, BRKEN, BRKPOL and AOEN bits of TMR15_BDT, and OCxOIS and OCxNOIS bits of TMR15_CTRL2 register.
  • Page 201 Reset value: 0x0000 Field Name Description DMA Base Address Setup These bits define the base address of DMA in continuous mode (when reading or writing TMR15_DMA register), and DBADDR is defined as the offset from the address of TMR15_CTRL1 register: DBADDR 00000：TMR15_CTRL1 00001：TMR15_CTRL2...

  • Page 202: Tmr16 And Tmr17 Register Address Mapping

    TMR16 and TMR17 Register Address Mapping 16.7 In the following table, all registers of TMR16 and TMR17 are mapped to a 16-bit addressable (address) space. Table 54 TMR16 and TMR17 Register Address Mapping Register name Description Offset address TMRx_CTRL1 Control register 1 0x00 TMRx_CTRL2 Control register 2...
  • Page 203 Field Name Description Update generated by slave mode controller. 1: Update event is disabled Update Request Source Select If interrupt or DMA is enabled, the update event can generate update interrupt or DMA request. Different update request sources can be selected through this bit.
  • Page 204 Field Name Description 1: It can be updated by setting COMG bit or rising edge on TRGI Capture/compare DMA Select CCDSEL 0: Send DMA request of CCx when CCx event occurs 1: Send DMA request of CCx when an update event occurs Reserved OC1 Output Idle State Configure Only the level state after the dead time of OC1 is affected when MOEN=0...
  • Page 205 Field Name Description 15:10 Reserved State register (TMRx_STS) Offset address: 0x10 Reset value: 0x0000 Field Name Description Update Event Interrupt Generate Flag 0: Update event interrupt does not occur 1: Update event interrupt occurs When the counter value is reloaded or reinitialized, an update event will be generated.
  • Page 206 Field Name Description 15:10 Reserved Control event generation register (TMRx_CEG) Offset address: 0x14 Reset value: 0x0000 Field Name Description Update Event Generate 0: Invalid 1: Initialize the counter and generate the update event This bit is set to 1 by software, and cleared by hardware. Note: When an update event is generated, the counter of the prescaler will be cleared, but the prescaler factor remains unchanged.
  • Page 207 Field Name Description Capture/Compare Channel 1 Select This bit defines the input/output direction and the selected input pin. 00: CC1 channel is output 01: CC1 channel is input, and IC1 is mapped on TI1 CC1SEL 10: CC1 channel is input, and IC1 is mapped on TI2 11: CC1 channel is input, and IC1 is mapped on TRC, and only works in internal trigger input Note: This bit can be written only when the channel is disabled...
  • Page 208 Field Name Description 11：PSC=8 PSC is prescaled factor, which triggers capture once every PSC events. Input Capture Channel 1 Filter Configure 0000: Filter disabled, sampling by f 0001：DIV=1，N=2 0010：DIV=1，N=4 0011：DIV=1，N=8 0100：DIV=2，N=6 0101：DIV=2，N=8 0110：DIV=4，N=6 0111：DIV=4，N=8 IC1F 1000：DIV=8，N=6 1001：DIV=8，N=8 1010：DIV=16，N=5 1011：DIV=16，N=6 1100：DIV=16，N=8 1101：DIV=32，N=5 1110：DIV=32，N=6 1111：DIV=32，N=8...
  • Page 209 Field Name Description trigger, capture, external clock and trigger mode). Capture/Compare Channel1 Complementary Output Enable 0: Disable CC1NEN 1: Enable Complementary output polarity of capture/compare channel 1 (Capture/Compare Channel1 Complementary Output Polarity) 0: OC1N high level is valid CC1NPOL 1: OC1N low level is valid Note: When the protection level is 2 or 3, this bit cannot be modified 15:4 Reserved...
  • Page 210 Field Name Description Capture/Compare Channel 1 Value When the capture/compare channel 1 is configured as input mode: CC1 contains the counter value transmitted by the last input capture channel 1 event. When the capture/compare channel 1 is configured as output mode: CC1 contains the current load capture/compare register value 15:0 Compare the value CC1 of the capture and compare channel 1 with the value...
  • Page 211 Field Name Description output after the dead time Run Mode Off-state Configure Run mode means MOEN=1; disable means CcxEN=0; this bit describes the impact of different values for this bit on the output waveform when RMOS MOEN=1 and CcxEN changes from 0 to 1. 0: OCx/OCxN output is disabled 1: OCx/OCxN first outptus invalid level (the specific level value is affected by the polarity configuration)
  • Page 212 Field Name Description +DBADDR+7 of TMRx_CTRL1 means the address of the data to be written/read, Data transmission will occur to: TMRx_CTRL1 address + seven registers starting from DBADDR. The data transmission will change according to different DMA data length: When the transmission data is set to 16 bits, the data will be transmitted to seven registers When the transmission data is set to 8 bits, the data of the first register is the MSB bit of the first data, the data of the second...

  • Page 213: Basic Timer (Tmr6/Tmr7)

    Basic Timer (TMR6/TMR7) TMR7 is available only on APM32F030xC device Introduction 17.1 The basic timers TMR6/TMR7 have an unsigned 16-bit counter, auto reload register, prescaler and trigger controller. The basic timer provides time reference for general-purpose timer, and can generate DMA request by configuration. Main Characteristics 17.2 （1）...
  • Page 214 When the counter is in count-up mode, the counter will count up from 0; every time a pulse is generated, the counter will increase by 1 and when the value of the counter (TMRx_CNT) is equal to the value of the auto reload (TMRx_AUTORLD), then the counter will start to count again from 0, a count-up overrun event will be generated, and the value of the auto reload (TMRx_AUTORLD) is written in advance.

  • Page 215: Register Address Mapping

    Register Address Mapping 17.5 In the following table, all registers of TMR6/TMR7 are mapped to a 16-bit addressable (address) space. Table 55 TMR6 and TMR7 Register Address Mapping Register name Description Offset address TMRx_CTRL1 Control register 1 0x00 TMRx_DIEN DMA/Interrupt enable register 0x0C TMRx_STS State register...
  • Page 216 Field Name Description 0: Disable 1: Enable Reserved Auto-reload Preload Enable When the buffer is disabled, the program modification TMRx_AUTORLD will immediately modify the values loaded to the counter; when the buffer is ARPEN enabled, the program modification TMRx_AUTORLD will modify the values loaded to the counter in the next update event.
  • Page 217 Field Name Description Update Event Generate 0: Invalid 1: Initialize the counter and generate the update event This bit is set to 1 by software, and cleared by hardware. Note: When an update event is generated, the counter of the prescaler will be cleared, but the prescaler factor remains unchanged.

  • Page 218: Infrared Timer (Irtmr)

    Infrared Timer (IRTMR) Introduction 18.1 IRTMR is an infrared interface for remote control, which can use an infrared LED to realize remote control function. Functional Description 18.2 IRTMR Receive The infrared receiver can be connected to the GPIO of the controller or the input capture channel of the timer through the output of the external IR receiver module to realize data receiving.

  • Page 219: Watchdog Timer (Wdt)

    Watchdog Timer (WDT) Introduction 19.1 The watchdog is used to monitor system failures caused by software errors. There are two watchdog devices on the chip: independent watchdog and window watchdog, which improve the security, and make the time more accurate and the use more flexible.
  • Page 220 Functional Description 19.2.3.1 Key register Write 0xCCCC in the key register to enable the independent watchdog, then the counter starts to count down from the reset value 0xFFF and when the counter counts to 0x000, a reset will be generated. Write 0xAAAA in the key register, and the value of the reload register will be reloaded to the counter to prevent the watchdog from resetting.

  • Page 221: Window Watchdog

    19.2.3.5 Hardware watchdog After the "hardware watchdog" function is enabled, and the system is powered on and reset, the watchdog will run automatically. If 0xAAAA is not written to the key register, reset will be generated after the counter finishes counting. 19.2.3.6 Debug mode The independent watchdog can be configured in debug mode and choose to stop or continue to work.

  • Page 222: Iwdt Register Address Mapping

    program segment is T, and the value of the window register is slightly less than (TR-T), if there is no reload register in the window, it means that the program is faulty, and when the counter counts to 0x3F, it will generate reset. Figure 91 Window Watchdog Timing Diagram Counter Start...

  • Page 223: Iwdt Register Functional Description

    Register name Description Offset address IWDT_PSC Prescaler register 0x04 IWDT_CNTRLD Counter reload register 0x08 IWDT_STS State register 0x0C IWDT_WIN Window register 0x10 IWDT Register Functional Description 19.5 These peripheral registers can be operated by half word (16 bits) or word (32 bits).
  • Page 224 Field Name Description Watchdog Counter Reload Value Setup It supports write protection function and defines the value loaded to the watchdog counter when 0xAAAA is written by IWDT_KEY register; in the process of writing this register, this register can be modified only when 11:0 CNTRLD CNTUFLG=0.

  • Page 225: Wwdt Register Address Mapping

    WWDT Register Address Mapping 19.6 Table 58 WWDT Register Address Mapping Register name Description Offset address WWDT_CTRL Control register 0x00 WWDT_CFG Configuration register 0x04 WWDT_STS State register 0x08 WWDT Register Functional Description 19.7 These peripheral registers can be operated by half word (16 bits) or word (32 bits).
  • Page 226 State register (WWDT_STS) Offset address: 0x08 Reset value: 0x0000 0000 Field Name Description Early Wakeup Interrupt Occur Flag 0: Not occur 1: When the counter value reaches 0x40, it is set to 1 by hardware; if EWIFLG RC_W0 the interrupt is not enabled, the bit will also be set to 1. It can be cleared by writing 0 by software Writing 1 to this bit is invalid.

  • Page 227: Real-Time Clock (Rtc)

    Real-time clock (RTC) Full Name and Abbreviation Description of Terms 20.1 Table 59 Full Name and Abbreviation Description of Terms Full name in English English abbreviation Second Alarm Prescaler Introduction 20.2 It has sub-second, time and date registers with BCD coding, as well as corresponding alarm registers, and can realize timestamp function together with external pins.

  • Page 228: Structure Block Diagram

    Structure Block Diagram 20.4 Figure 92 APM32F030x6x8 RTC Structure Block Diagram Tamper RTC_TAMP1 Tamper TPxFLG sampling detection RTC_TAMP2 controller Timestamp controller RTC_TS TAFLG Timestamp RTC_REFIN Calendar LSECLK RTCCLK Asynchronous Synchronous RTCcalibra Time and date HSECLK/32 prescaler 7 prescaler Subsecond tion register 15bit LSICLK...

  • Page 229: Functional Description

    Functional Description 20.5 I/O Pin Controlled by RTC RTC_OUT, RTC_TS and RTC_TAMP1 in RTC can be mapped to the same pin (PC13). The output selection of RTC_ALARM is configured through RTC_TACFG, and PC13VAL bit of RTC_TACFG register is used to select RTC_ALARM to configure push-pull output or open-drain output.

  • Page 230: Clock Calibration

    The following table shows the priority sequence followed by the output mechanism: Table 61 PC14 Pin Controlled by LSECLK RCM_RTCCTRL Pin configuration RCM_RTCCTRL LSEBCFG bit of PC14EN PC14VAL and function LSEEN bit of register register LSECLK oscilltor No effect No effect LSECLK bypass No effect No effect...
  • Page 231 RTC can realize clock synchronization according to external high-precision clcok and the register RTC_SHIFT. The deviation between RTC clock and external clock is detected mainly by acquiring the timestamps of subsecond time period twice. Since the synchronous prescaled value is used as the reload value of the subsecond counter, and the SFSEC bit of register RTC_SHIFT is used in the subsecond counter, the SFSEC bit can be adjusted to finely tune the RTC clock and increase or decrease several cycles artificially.

  • Page 232: Programmable Alarm

    from the calendar counter. The time system of 24 hours and 12 hours can be selected by TIMEFCFG bit of configuration register RTC_CTRL. RTC updates the shadow register every two RTC_CLK cycles, and sets the flag bit RSFLG. When waking up from shutdown or standby mode, generally the shadow register will not be updated, which requires waiting for up to two RTC_CLK cycles.

  • Page 233: Time Stamp

    Select "seconds" as the time period of the alarm, and only when the synchronous prescaler value is greater than 2, can the alarm operate normally. Timestamp RTC supports timestamp function and the RTC_TS pin works together with the timestamp register. The timestamp polarity is detected through TSETECFG bit of the register RTC_CTRL.

  • Page 234: Register Address Mapping

    There is a 16bit self-decrement reload counter in RTC, and it is used to wake up the device automatically. The clock of this counter is selected by WUCLKSEL bit of the register RTC_CTRL, and by selecting different clocks, the automatic wake-up cycle can be configured from 122μs to 36h.

  • Page 235: Register Functional Description

    Register name Description Offset address RTC_CAL RTC calibration register 0x3C RTC_TACFG RTC tamper and multiplexing configuration register 0x40 RTC_ALRMASS RTC alarm A subsecond register 0x44 Register Functional Description 20.7 RTC time register (RTC_TIME) RTC_TIME is calendar time shadow register, and this register can be written only in initialization mode and is in write protection state.
  • Page 236 Field Name Description Week Day Units Select 000: Disable 001: Monday 15:13 WEEKSEL 111: Sunday Year Ones Unit in BCD Format Setup 19:16 ear Ten's Place Unit in BCD Format Setup 23:20 31:24 Reserved RTC control register (RTC_CTRL) （1） The bits 7, 6 and 4 of this register can be written only in initialization mode.
  • Page 237 Field Name Description 1: Enable Time Stamp Enable TSEN 0: Disable 1: Enable Alarm A Interrupt Enable ALRIEN 0: Disable 1: Enable Reserved Wakeup Timer Interrupt Enable WUTIEN 0: Disable 1: Enable Time Stamp Interrupt Enable TSIEN 0: Disable 1: Enable Summer Time Change Configure The bit will always be 0 in the reading process;...
  • Page 238 Field Name Description Alarm A Write Occur Flag When ALREN=0 for RTC_CTRL, the value of alarm A will change and this bit will be set to 1 by hardware; this bit will be cleared by hardware ALRWFLG in initialization mode. 0: The alarm A can be updated 1: The alarm A cannot be updated Reserved...
  • Page 239 Field Name Description RTC_TP1FLG Detection Occur Flag TP1FLG RC_W0 When a tamper event is detected in RTC_TP1FLG input, this flag is set to 1 by hardware, it can be cleared by writing 0 by software. RTC_TP2FLG Detection Occur Flag TP2FLG RC_W0 When a tamper event is detected in RTC_TP2FLG input, this flag is set to 1 by hardware, it can be cleared by writing 0 by software.
  • Page 240 RTC alarm A register (RTC_ALRMA) This register can be written only when ALRWFLG of RTC_STS is set to 1 or in initialization mode, and it is in write protection state. Offset address: 0x1C Power-on reset value: 0x0000 0000 System reset: 0xXXXX XXXX Field Name Description...
  • Page 241 Field Name Description Sub Second Value Setup SUBSEC is the value of synchronous prescaler counter. It is determined by the following formula: 15:0 SUBSEC Subsecond value=(SPSC-SUBSEC)/(SPSC+1) After one shift operation is performed, SUBSEC may be greater than SPSC. The correct time/date is one second less than RTC_TIME/RTC_DATE.
  • Page 242 Field Name Description SECT Second Ten's Place Unit in BCD Format Setup Reserved 11:8 MINU Minute Ones Unit in BCD Format Setup 14:12 MINT Minute Ten's Place Unit in BCD Format Setup Reserved 19:16 Hour Ones Unit in BCD Format Setup 21:20 Hour Ten's Place Unit in BCD Format Setup Time Format Configure...
  • Page 243 Field Name Description 31:16 Reserved RTC calibration register (RTC_CAL) This register is in write protection state. Offset address: 0x3C Power-on reset value: 0x0000 0000 System reset: 0xXXXX XXXX Field Name Description Reduced Calibration Frequency Reduced calendar frequency: Shield RECALF pulses within 2 RTCCLK pulses (32sec if the output frequency is 32768 Hz) and the calendar frequency RECALF...
  • Page 244 Field Name Description 0: Rising edge 1: Falling edge Tamper Interrupt Enable TPIEN 0: Disable 1: Enable RTC_TAMP2 Input Detection Enable TP2EN 0: Disable 1: Enable RTC_TAMP2 Input Active Level Configure When TPFCSEL!=00, this bit determines that RTC_TAMP2 will trigger a tamper detection event when the input maintains high/low level.
  • Page 245 Field Name Description 17:16 Reserved RTC_ALARM Output Type/PC13 Value Configure When PC13 is used to output RTC_ALARM, this bit determines the output mode of RTC_ALARM: PC13VAL 0: Open-drain output 1: Push-pull output When all RTC multiplexing functions are disabled and PC13EN=1, this bit is used to set PC13 output value.
  • Page 246 Field Name Description 0xC: When comparing with alarm A, SUBSEC[14:12] is not involved, and only SUBSEC[11:0] is involved 0xD: When comparing with alarm A, SUBSEC[14:13] is not involved, and only SUBSEC[12:0] is involved 0xE: When comparing with alarm A, SUBSEC[14] is not involved, and only SUBSEC[13:0] is involved 0xF: When comparing the alarm A, 15 SUBSEC bits all take part in, and the alarm can be activated only when all of them match.

  • Page 247: Universal Synchronous/Asynchronous Transceiver (Usart)

    Universal Synchronous/Asynchronous Transceiver (USART) Full Name and Abbreviation Description of Terms 21.1 Table 64 Full Name and Abbreviation Description of Terms Full name in English English abbreviation Clear to Send Request to Send Most Significant Bit Least Significant Bit Guard Overrun Introduction 21.2...

  • Page 248: Functional Description

    （11） Support timeout detection （12） Programmable baud rate generator, with the baud rate up to 6Mbits/s （13） Automatic baud rate detection （14） Multiprocessor communication:  If the address does not match, it will enter the mute mode  Wake up from mute mode through idle bus detection or address flag detection （15）...

  • Page 249: Frame Format

    When USART enters single-line half-duplex mode:  CLKEN bit of USART_CTRL2 register must be cleared.  RX pin is disabled.  TX pin should be configured as open-drain output and connected with RX pin inside the chip.  Transmitting data and receiving data cannot be carried out at the same time.
  • Page 250 If the check control is enabled, corresponding interrupt will be triggered. Write 1 to PECLR bit of USART_INTFCLR register, and PEFLG flag bit can be cleared. Transmitter When TXEN bit of the register USART_CTRL1 is set, the transmit shift register will output data through TX pin and the corresponding clock pulses will be output through CK pin.
  • Page 251 （3） If USART is in idle state, write to the data register, put the data into the shift register, start transmitting data, and set TXBEFLG bit to 1. （4） When a data transmission is completed and TXBEFLG bit is set, TXCFLG bit will be set to 1;...
  • Page 252 Note: （1） RXEN bit cannot be reset during data receiving period; otherwise, the bytes being received will be lost. （2） In the process when the receiver is receiving a data frame, if overrun error, noise error or frame error is detected, the error flag will be set to 1. （3）...
  • Page 253 received at the same time, an overrun error will be caused. Only after RXEN is reset, can the data be transferred from the shift register to RXDATA register. RXBNEFLG bit will be set to 1 after receiving the byte. This bit needs to be reset before receiving the next data or serving the previous DMA request;...

  • Page 254: Baud Rate Generator

    （4） DTCL: Deviation caused by transmission line Baud Rate Generator The baud rate division factor (USARTDIV) is a 16-digit number consisting of 12-digit integer part and 4-digit decimal part. Its relationship with the system clock: Baud rate=PCLK/16×(USARTDIV) The system clock of USART2/3 is PCLK1, and that of USART1 is PCLK2. USART can be enabled only after the clock control unit enables the system clock.
  • Page 255 When mute mode is enabled, there are two ways to exit the mute mode: （1） WUPMCFG bit is cleared and the bus is idle to exit the mute mode. （2） WUPMCFG bit is set and after receiving the address flag, it can exit the mute mode.

  • Page 256: Synchronous Mode

    Synchronous Mode The synchronous mode supports full duplex synchronous serial communication in master mode, and has one more signal line USART_CK which can output synchronous clock than the asynchronous mode. CLKEN bit of USART_CTRL2 register decides whether to enter the synchronous mode.
  • Page 257 Figure 97 USART Synchronous Transmission Timing Diagram (DBLCFG0=0) DBLCFG0=0(8-bit data） CK(CPOL=0,CPHA=0) CK(CPOL=0,CPHA=1) CK(CPOL=1,CPHA=0) CK(CPOL=1,CPHA=1) Start Stop TX(from master device) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6...
  • Page 258 CTS flow control CTSEN bit of USART_CTRL3 register determines whether CTS flow control is enabled. If CTS flow control is enabled, the transmitter will detect whether the data frame of nCTS pin can be transmitted. If TXBEFLG bit=0 for USART_STS register and nCTS is pulled to low level, the data frame can be transmitted.

  • Page 259: Interrupt Request

    Receive in DMA mode DMARXEN bit of USART_CTRL3 register determines whether to receive by DMA. When receiving by DMA, every time one byte is received, the data in the receive buffer will be transmitted to the designated SRAM area by DMA. Configuration steps of receiving by DMA: （1）...

  • Page 260: Register Address Mapping

    Figure 100 USART Interrupt Mapping RXBNEFLG OVREFLG RXBNEIEN IDLEFLG IDLEIEN PEFLG PEIEN Receive interrupt NEFLG OVREFLG FEFLG ERRIEN CMFLG CMIEN USART interrupt RXTOFLG RXTOIEN TXBEFLG TXBEIEN TXCFLG TXCIEN Transmit interrupt CTSFLG CTSIEN Comparison of USART Supporting Functions Table 68 Comparison of USART Supporting Functions USART mode USART1 USART2...

  • Page 261: Register Functional Description

    Register name Description Offset address USART_CTRL3 Control register 3 0x08 USART_BR Baud rate register 0x0C USART_RXTO Receive timeout register 0x14 USART_REQUEST Request register 0x18 USART_STS Interrupt and state register 0x1C USART_INTFCLR Interrupt flag clear register 0x20 USART_RXDATA Receive data register 0x24 USART_TXDATA Transmit data register...
  • Page 262 Field Name Description Set 1 or clear 0 by software. Parity Error interrupt Enable 0: Disable PEIEN 1: Generate an interrupt when PEFLG is set Set 1 or clear 0 by software. Odd/Even Parity Configure 0: Even parity check 1: Odd parity check Set 1 or clear 0 by software.
  • Page 263 Field Name Description oversampling rate. This bit field can be set only when USART is not enabled. Receiver Timeout Interrupt Enable 0: Disable RXTOIEN 1: Generate an interrupt when RXTOFLG is set Set or cleared by software. Reserved Data Bits Length Configure This bit and DBLCFG0 bit jointly decide the length of data bit.
  • Page 264 Field Name Description 00: 1 stop bit 01: Reserved 10: 2 stop bits 11: Reserved This bit can be set only when USART is not enabled. Reserved Swap TX/RX Pins Function Enable 0: Use according to standard allocation 1: The functions of TX and RX pins can be exchanged for use, and SWAPEN they will work when crossing and interconnecting with other USART.
  • Page 265 Field Name Description USART Device Node Address Low Setup This bit field is used for wake-up detection of 7-bit address flag which is used for multi-computer communication and enters the mute state 27:24 ADDRL or stop mode. This bit can be set only when the receiver is turned off or USAR is not enabled.
  • Page 266 Field Name Description otherwise, the data cannot be transmitted; if CTS signal is pulled to high during data transmission, the data transmission will be stopped after the data transmission is completed; if write operation is performed for the data register when CTS is high, the data will not be transmitted until CTS is valid.
  • Page 267 Field Name Description Integer of USART Baud Rate Divider factor 15:4 The integral part of USART baud rate division factor is determined by these 12 bits. 31:16 Reserved Receive timeout register (USART_RXTO) Offset address: 0x14 Reset value: 0x0000 Field Name Description Receiver Timeout Value Setup This bit field specifies the receive timeout value in baud clock.
  • Page 268 Field Name Description When there is synchronous dislocation, too much noise or break symbol, this bit is set to 1 by hardware; set FECLR and this bit can be cleared. Noise Error Occur Flag 0: No noise NEFLG 1: Noise is detected When there is noise error, this bit is set to 1 by hardware;...
  • Page 269 Field Name Description 13:12 Reserved Auto Baud Rate Detection Error Flag ABRDEFLG This bit is set to 1 by hardware when baud rate detection fails; this bit can be cleared by setting ABRDQ bit. Auto Baud Rate Detection Flag When the automatic baud rate function is turned on or when the ABRDFLG automatic baud rate operation is interrupted, it is set to 1 by hardware;...
  • Page 270 Field Name Description Set this bit and IDLEFLG flag bit of USART_STS register can be cleared. Reserved Transmission Data Complete Flag Clear TXCCLR RC_W1 Set this bit and TXCFLG flag bit of USART_STS register can be cleared. Reserved CTS Flag Clear CTSCLR RC_W1 Set this bit and CTSFLG flag bit of USART_STS register can be...

  • Page 271: Internal Integrated Circuit Interface (I2C)

    Internal Integrated Circuit Interface (I2C) Full Name and Abbreviation Description of Terms 22.1 Table 70 Full Name and Abbreviation Description of Terms Full name in English English abbreviation Serial Data Serial Clock System Management Bus SMBus Clock Serial Clock High SCLH Serial Clock Low SCLL...

  • Page 272: Structure Block Diagram

    （8） Programmable start time and hold time （9） Support DMA function （10） Programmable noise filter （11） SMBus specific function  Hardware PEC  Command receiving and data acknowledgment control  Address resolution protocol  HOST notification protocol  SMBus alarm ...

  • Page 273: Functional Description

    Figure 102 I2C2 Functional Structure Diagram APB bus PCLK Register Data controller Digital Analog Shift register noise noise filter filter I2C2_SDA GPIO Logic Clock controller Master clock Digital Analog generated noise noise filter filter Slave clock I2C2_SCL GPIO receives Logic Functional Description 22.5 I2C Physical Layer...
  • Page 274 （2） An I2C bus only uses two bus lines, namely, a bidirectional serial data line (SDA) and a serial clock line (SCL). The data line is used for data transmission, and the clock line is used for synchronous receiving and transmission of data.
  • Page 275 Figure 105 Master Reads Data from Slave Note: （1） : This data is transferred from master to slave （2） S: Start signal （3） SLAVE ADDRESS: Slave address （4） : This data is transferred from slave to master （5） R/W: Selection bit of transmission direction （6）...
  • Page 276 22.5.3.2 Requirements for I2C clock （1） t < (t )/4 and t <t filters I2C_CLK I2C_CLK HIGH （2） t : SCL low-level time （3） t : SCL high-level time HIGH （4） t : Total lag caused by analog filter and digital filter when I2C is started filters I2C clock configuration Before peripherals are started, it is required to configure SCLH and SCLL bits in...
  • Page 277 Symbol Parameter Standard mode Fast mode Fast mode plus SMBus Unit Rising edge time of SDA 1000 1000 and SCL signals Falling edge time of SDA and SCL signals 22.5.3.3 I2C_TIMING register configuration Table 72 I2C_TIMING Register Configuration =48MHz I2C_CLK Standard mode Fast mode Fast mode plus...
  • Page 278 22.5.4.1 Slave mode Transmitt in slave mode After the master sends the start signal and address, the addressing is successful, the ADDRMFLG bit is cleared, and the transmitter will transmit the data to be transmitted from I2C_TXDATA register to SDA line by internal shift register. Every time the slave sends a byte, it will wait for the master's acknowledge signal (ACK) and repeat this process until the master wants to stop receiving data and returns a non-acknowledge signal (NACK) to the slave.
  • Page 279 Master receiving The I2C interface sends the start signal and sends the address to the SDA line through the internal shift register. The transmission direction is read. After the slave responds, the master enters the receiving mode, receives the data on the SDA line through the internal shift register and sends them to I2C_RXDATA register.
  • Page 280 This peripheral can be supported by SMBus reminder signal. When a device that is used only as the slave wants to initiate communication, it can notify HOST through SMBALERT pin. HOST will handle the interrupt and then access all SMBALERTdevices through the reminder response address (0b0001100). Only the device with the SMBALERT pin pulled down will respond to the reminder response address.
  • Page 281 occurs on SDA, it will be detected as START or STOP signal. Only when I2C is communicating and transmitting data, can bus error occur (after data have been transmitted as the master or the address has matched as the slave). This error will not occur in slave mode address matching phase. When a bus error is detected, BERRFLG flag bit of I2C_STS register will be set to 1 by hardware;...
  • Page 282  IDLECLKTO=1 and the high-level time of SDA and SCL exceeds the time defined by TIMEOUTA[11:0] bit field. （2） SMBus idle timeout is detected  The accumulative time of low extension of master clock reaches the time (t ) defined by TIMEOUTB[11:0] bit field. LOW:MEXT ...

  • Page 283: Register Address Mapping

     Configure and start I2C channel in NVIC  Configure I2C interrupt enable bit Register Address Mapping 22.6 Table 75 I2C Register Address Mapping Register name Description Offset address I2C_CTRL1 Control register 1 0x00 I2C_CTRL2 Control register 2 0x04 I2C_ADDR1 Master address register 1 0x08 I2C_ADDR2...
  • Page 284 Field Name Description Error Interrupt Enable 0: Disable ERRIEN 1: When the position 1 of any of the following state register is enabled, the interrupt will be generated: SMBALTFLG, TTEFLG, PECEFLG, OVRURFLG, ALFLG, and STS1_BERRFLG Digital Noise Filter Configure The digital noise filters of SDA and SCL are configured by this bit field. The length of digital filter is DNFCFG[3:0]*t I2C_CLK 0000: Disable...
  • Page 285 Field Name Description 0: Not supported 1: Supported If ALTEN=0, SMBALERT pin can be used as a GPIO; If SMBus mode is not supported, this bit will be reserved and be forced to 0. PEC Enable 0: Disable PECEN 1: Enable If SMBus mode is not supported, this bit will be reserved and be forced to 0.
  • Page 286 Field Name Description In master mode: 0: Not transfer 1: Transfer It is meaningless to write 0 to this bit. Transmit NACK Enable This bit can be set to 1 and cleared by software; it can be cleared by hardware after the stop bit and NACK are transmitted, the address match event is received or when I2CEN bit is not set.
  • Page 287 Field Name Description Master Address Setup When the address mode is 7 bits, the bit is invalid; when the address ADDR1[0] mode is 10 bits, this bit is the 0 bit of the address. Master Address Setup ADDR1[7:1] The bit[7:1] of master address Master Address Setup When the address mode is 7 bits, the bit is invalid;...
  • Page 288 Reset value: 0x0000 0000 Field Name Description SCL Low Level Time Setup SCLL =(SCLL+1) x t SCLL TIMINGPSC SCLL determines t and t timing. SU:STA SCL High Level Time Setup 15:8 SCLH =(SCLH+1) x t SCLH TIMINGPSC SCLH determines t and t timing.
  • Page 289 Field Name Description slave mode (t LOW:SEXT =(TIMEOUTB+1) x 2048 x t TLOW:EXT I2C_CLK This bit field can be set only when EXCLKTOEN bit is not set. 30:28 Reserved Extended Clock Timeout Enable 0: Disable EXCLKTOEN 1: Enable. A timeout error is detected when the hold time of low SCL reaches t TLOW:EXT State register (I2C_STS)
  • Page 290 Field Name Description I2CEN=0. Transmit Data Complete Flag 0: Transmit data is not completed 1: Transmit data is completed TXCFLG This bit can be set to 1 by hardware when RELOADEN=0, ENDCFG=0 and NUMBYT data have been transmitted; be cleared when START=1 or STOP=1;...
  • Page 291 Field Name Description 1: The bus is busy (in the progress of communication) This bit can be set to 1 by hardware when a start bit is detected; be cleared by hardware when a stop bit is detected; or be cleared when I2CEN=0.
  • Page 292 Field Name Description 31:14 Reserved PEC register (I2C_PEC) Offset address: 0x20 Reset value: 0x0000 0000 Field Name Description PEC Value Setup When PECEN=1, this bit field means the internal PEC value. This bit can be cleared by hardware when I2CEN=0. 31:8 Reserved Receive data register (I2C_RXDATA)

  • Page 293: Serial Peripheral Interface (Spi)

    Serial Peripheral Interface (SPI) Full Name and Abbreviation Description of Terms 23.1 Table 76 Full Name and Abbreviation Description of SPI Terms Full name in English English abbreviation Most Significant Bit Least Significant Bit Master Out Slave In MOSI Master In Slave Out MISO Serial Clock Serial Data...

  • Page 294: Functional Description

    （11） Interrupt can be triggered by master mode fault, overrun and CRC error flag （12） Have DMA transmit and receive buffers （13） Calculation, transmission and verification can be conducted through hardware CRC （14） CRC error flag （15） Two 32-bit embedded RXFIFO and TXFIFO have DMA function Functional Description 23.4 Description of SPI Signal Line...
  • Page 295 Table 78 Four Modes of SPI SPI mode CPHA CPOL Sampling moment Idle SCK clock Odd edge Low level Odd edge High level Even edge Low level Even edge High level Note: （1） To change CPOL and CPHA bits, SPI must be cleared and disabled through SPIEN bit （2）...
  • Page 296  Select the transmission mode by configuring RXOMEN, BMOEN and BMEN bits in SPI_CTRL1 register  Select the data bit width by configuring DSCFG bit in SPI_CTRL2 register  Turn on NSS pulse mode by configuring NSSPEN bit in SPI_CTRL2 register (when configuring this bit, CPHA bit must be set to 1) ...
  • Page 297 the master and the slave are connected through two unidirectional lines MOSI and MISO. During SPI communication, synchronous data transmission is conducted according to SCK clock edge. The data of the master are transmitted to the slave through MOSI pin, and the data of the slave are transmitted to the master through MISO pin.
  • Page 298 Mode Configure Data pin Full duplex mode of slave BMEN=0，RXOMEN=0 MOSI receives; MISO transmits device Unidirectional receiving mode MOSI receives; MISO is not BMEN=0，RXOMEN=1 of slave device used Bidirectional transmitting mode MOSI is not used; MISO BMEN=1，BMOEN=1 of slave device transmits Bidirectional receiving mode of MOSI receives;...
  • Page 299 Figure 110 Connection in Simplex Mode (the master only transmits, while the slave receives) 23.4.5.1 Transmitting and receiving of data In order to prevent overrun when the data frame is short and ensure that SPI can work continuously, all SPI data need to pass through the 32-bit embedded FIFO. Each direction will have its own FIFO, TXFIFO and RXFIFO.

  • Page 300: Nss Pulse Mode

    Note: Check whether the data transmission is completed according to FTLSEL bit and BSYFLG bit, （1） and the clock output will stop when the transmission is completed. （2） In packet mode, special attention should be paid to empty bytes when the data being transmitted are odd.
  • Page 301 (it should be odd, and does not support even number). Enable CRC computing by configuring CRCEN bit in SPI_CTRL1 register; at the same time, reset the CRC register (SPI_RXCRC and SPI_TXCRC). CRC is managed by CPU during transmission To obtain the CRC value of transmission calculation, after the last data is written to the transmit buffer, it is required to set CRCNXT bit of SPI_CTRL1;...

  • Page 302: Spi Interrupt

    DMA function with CRC By the end of communication, if SPI enables both CRC operation and DMA function, transmitting and receiving of CRC bytes will be completed automatically. The CRCNXT bit is not controlled by software. The transmitting DMA channel counter of SPI must be set to the number that does not contain CRC data, but the DMA channel counter must contain the length of one more CRC data when receiving.
  • Page 303  TI frame format error 23.4.11.1 State flag bit There are three flag bits for fully monitoring the state of SPI bus Transmit buffer empty flag TXBEFLG TXBEFLG=1 means that TXFIFO has space to store the transmitted data; TXBEFLG flag bit is connected to TXFIFO bit, and in the process of storing data, if the storage content of TXFIFO is less than or equal to FIFO/2, TXBEFLG flag bit is kept high.
  • Page 304 disabled); MSMCFG is cleared and the device is forced to enter the slave mode. Operation of clearing the MEFLG flag bit: When MEFLG flag bit is set to 1, it is required to read or write SPI_STS register, and then write to SPI_CTRL1 register.

  • Page 305: Register Address Mapping

    Enable Interrupt flag Interrupt event Clearing method control bit Read/Write SPI_STS MEFLG Master mode failure event flag register and then write SPI_CTRL1 register Read SPI_DATA register OVRFLG Overrun error flag and then read SPI_STS ERRIEN register CRCEFLG CRC error flag Write 0 to CRCEFLG bit FREFLG TI mode frame format error flag...
  • Page 306 Field Name Description 1: Configure as master mode Note: This bit cannot be modified during communication Baud Rate Divider Factor Select 000：DIV=2 001：DIV=4 010：DIV=8 011：DIV=16 BRSEL 100：DIV=32 101：DIV=64 110：DIV=128 111：DIV=256 Baud rate=FPCLK/DIV Note: This bit cannot be modified during communication SPI Device Enable 0: Disable SPIEN...
  • Page 307 Field Name Description CRC Calculate Enable 0: CRC check is disabled CRCEN 1: CRC check is enabled CRC check function only applies to full duplex mode; only when SPIEN=0, can this bit be changed. Bidirectional Mode Output Enable 0: Disable (receive-only ode) BMOEN 1: Enable (send-only mode) When BMEN=1, namely in single-line bidirectional mode, this bit determines...
  • Page 308 Field Name Description 0: Disable 1: Enable When an error occurs, ERRIEN bit controls whether to generate the interrupt. Receive Buffer Not Empty Interrupt Enable 0: Disable 1: Allowe RXBNEIEN When RXBNEFLG flag bit is set to 1, an interrupt request will be generated Transmit Buffer Empty Interrupt Enable 0: Disable...
  • Page 309 Field Name Description register is set and the packing mode is enabled. This bit can be written only when SPIEN=0. Disable SPI. Reserved SPI state register (SPI_STS) Offset address: 0x08 Reset value: 0x0002 Field Name Description Receive Buffer Not Empty Flag RXBNEFLG 0: Empty 1: Not empty...
  • Page 310 Field Name Description Note: This bit set 1 or clear 0 by hardware. 15:13 Reserved SPI data register (SPI_DATA) Offset address: 0x0C Reset value: 0x0000 Field Name Description Transmit Receive Data register Store the data to be transmitted or received. When writing this register, the data will be written to the transmit buffer;...
  • Page 311 Field Name Description Note: When BSYFLG bit is set to 1, the value of reading RXCRC register may be wrong. www.geehy.com Page 310...

  • Page 312: Analog/Digital Converter (Adc)

    Analog/Digital Converter (ADC) Introduction 24.1 ADC with 12-bit precision and 18 channels, including 16 external channels and 3 internal channels, and there are single, continuous and intermittent A/D conversion modes for each channel. ADC conversion results can be left-aligned or right-aligned and stored in 16-bit data register. Main Characteristics 24.2 （1）...

  • Page 313: Functional Description

    Functional Description 24.3 ADC Pin and Internal Signal Table 82 ADC Internal Signal Name Instruction Signal type TMRx_TRG Internal information from timer Input Output of internal reference voltage Input REFINT Table 83 ADC Pins Name Instruction Signal type Analog power supply, positive ADC reference Input, analog power supply voltage, V ≥V...
  • Page 314 When CMODESEL bit of register ADC_CFG1 is configured to 1, ADC is set to continuous conversion mode; configure STARTCEN bit of register ADC_CTRL to 1 by software or trigger the event by hardware to enable ADC conversion. After the conversion of each channel, the converted data will be stored in the 16-bit ADC_DATA register, EOCFLG bit will be set to 1, and if EOCIEN bit is set to 1, an interrupt will be generated.
  • Page 315 Trigger source EXTTRGSEL Trigger type TMR15_TRGO Reserved Reserved Reserved External pin When the bit EXTPOLSEL≠"0b00" for the register ADC_CFG1, the external event can trigger conversion on its selected polarity. Table 85 Configuration Trigger Polarity EXTPOLSEL Source Detection of disabled trigger Detection on rising edge Detection on falling edge Detection on both rising edge and falling edge...
  • Page 316 Interrupt event Event flag Enable control Analog watchdog state reset AWDFLG AWDIEN ADC Overrun ADC overrun means when the converted data is not read by DMA or CPU on time, another converted data will take effect. When EOCFLG bit is 1 but another new conversion has been completed, an overrun event will occur, and OVREFLG bit of register ADC_STS will be set to 1;...

  • Page 317: Register Address Mapping

     When DMACFG is set to 1, DMA is in circular mode DMA programming is in circular mode or double-buffer mode In this mode, when ADC conversion is started again and the converted data is valid, a DMA request will be generated Low-power Characteristics 24.3.11.1 Automatic delay conversion mode This mode is used to simplify the software and optimize the application program...
  • Page 318 Field Name Description ADC Ready Flag ADCRDYFLG RC_W1 0: ADC not ready 1: ADC has been ready to start conversion End of Sampling Flag This bit is set to 1 by hardware and cleared by software EOSMPFLG RC_W1 0: Not in the phase of end of sampling 1: Reach the condition for end of sampling phase End of Conversion Flag This bit is set to 1 by hardware and cleared by software...
  • Page 319 Field Name Description Analog Watchdog Interrupt Enable AWDIEN 0: Disable 1: Enable 31:8 Reserved Note: These bits can be rewritten only when STARTCEN=0. ADC control register (ADC_CTRL) Offset address: 0x08 Reset value: 0x0000 0000 Field Name Description ADC Enable This bit is set to 1 by software and cleared by hardware. 0: ADC is disabled ADCEN 1: ADC is enabled...
  • Page 320 Field Name Description DMA Enable DMAEN 0: DMA is disabled 1: DMA is enabled DMA Mode Configure This bit is valid only when DMAEN=1. DMACFG 0: DMA single mode 1: DMA circular mode Scan Sequence Direction Configure SCANSEQDIR 0: Scan forward (from CHSEL0 to CHSEL16) 1: Scan backward (from CHSEL16 to CHSEL0) Data Resolution Configure 00: 12 bits...
  • Page 321 Field Name Description Enable The Watchdog On A Single Channel or on All Channels AWDCHEN 0: Enable analog watchdog on all channels 1: Enable analog watchdog on a single channel Analog Watchdog Enable AWDEN 0: Disable 1: Enable 25:24 Reserved Analog Watchdog Channel Select These bits are used to configure the input channel for the analog watchdog to monitor ADC...
  • Page 322 Field Name Description 31:3 Reserved ADC watchdog threshold register (ADC_AWDT) Offset address: 0x20 Reset value: 0x0FFF 0000 Field Name Description 11:0 AWDLT[11:0] Analog Watchdog Low Threshold 15:12 Reserved 27:16 AWDHT[11:0] Analog Watchdog High Threshold 31:28 Reserved Note: These bits can be rewritten only when STARTCEN=0. ADC channel selection register (ADC_CHSEL) Offset address: 0x28 Reset value: 0x0000 0000...
  • Page 323 Field Name Description 31:23 Reserved Note: This bit can be rewritten only when STARTCEN=0 www.geehy.com Page 322...

  • Page 324: Cyclic Redundancy Check Computing Unit (Crc)

    Cyclic Redundancy Check Computing Unit (CRC) Introduction 25.1 The cyclic redundancy check (CRC) computing unit can get 8/16/32-bit CRC computing result by calculating the input data through a fixed generator polynomial, which is mainly used to detect or verify the correctness and integrity of the data after transmission or saving.

  • Page 325: Register Functional Description

    Register Functional Description 25.4 Data register (CRC_DATA) Offset address: 0x00 Reset value: 0xFFFF FFFF Field Name Description 32bit Data 31:0 DATA Used as input register when writing new data of CRC calculator Return CRC computing results when reading Independent data register (CRC_INDATA) Offset address: 0x04 Reset value: 0x0000 0000 Field...
  • Page 326 Field Name Description Initial CRC Value 31:0 VALUE The CRC initial value is programmable, and this bit is used to set the CRC initial value. www.geehy.com Page 325...

  • Page 327: Chip Electronic Signature

    Chip Electronic Signature The chip electronic signature includes flash capacity information of main memory and 96-bit unique chip ID, which have been written into the system memory area of the chip before leaving the factory, and are read-only and cannot be modified by users.

  • Page 328: Version History

    Version History Table 90 Document Version History Date Version Change History V1.0 June, 2020 (1) Modify the cover and page header (2) Delete 32-bit counter in TMR3 brief introduction February 22, 2021 V1.0 (3) Add DMA channel selection register (4) Modify the clock tree and add RCM_CFG2 register (5) Modify the inconsistency of names (1) Modify the read/write function of "GPIO port set/reset register"...

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