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Geehy SEMICONDUCTOR GW3323 User Manual

Risc-v based 32-bit mcu with bluetooth
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User Manual
GW3323
RISC-V based 32-bit MCU with Bluetooth
Version: V0.2
www.geehy.com
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  • Page 1 User Manual GW3323 RISC-V based 32-bit MCU with Bluetooth Version: V0.2 www.geehy.com Page 1...

  • Page 2: Table Of Contents

    Contents Block Diagram ........................5 System Management ......................6 System Clock ...............................6 Clock Register ............................. 7 Memory Access ....................... 19 Low Power Mode ......................20 1. sleep mode,500uA ..........................20 4.1.1 Configuration of sleep mode ..........................20 Power-off mode (power off, 4uA) ......................20 4.2.1 Configuration of power-down mode .........................20 Interrupts .........................
  • Page 3 10.1 Features ..............................43 10.2 Special Function Registers ........................43 10.3 Independent Power RTC Registers ......................44 UART ..........................50 11.1 Features ..............................50 11.2 User Guide ..............................50 11.2.1 UART Special Function Registers ........................50 HSUART ........................... 53 12.1 Features ..............................53 12.2 User Guide ..............................
  • Page 4 17.1 Feature ..............................76 17.2 Control use ..............................76 Power Management ......................77 18.1 Charging process ............................77 18.2 Charging settings ............................77 18.3 Charging control function .......................... 77 Bluetooth ......................... 78 19.1 Feature ..............................78 19.2 SPP protocol ..............................78 19.2.1 SPP protocol is based on credit flow control mechanism ................78 19.2.2 SPP use and development in SDK ........................

  • Page 5: Block Diagram

    1 Block Diagram Figure 1 GW3323 System Block Diagram Note: Chx indicates the channel number x www.geehy.com Page 5...

  • Page 6: System Management

    2 System Management 2.1 System Clock Figure 2 System Clock Tree For details, see GW3323_clock.pdf. The maximum frequency of this chip is 160MHz, which can be set by set_sys_clk(). www.geehy.com Page 6...

  • Page 7: Clock Register

    Table 1 PLL clock error Theoretical Actual output Value set by Error% PLLCON0 clock(Hz) output clock clock configure set_sys_clk() configure set_sys_clk() DI_LDO_SEL(0x2); 47.99 DI_LDO2_SEL(0x3); DI_EN_XRES(0x0); 59.99 DI_EN_NOTCH(0x0); 120M 119.99 DI_EN_TRIM(0x1); DI_EN_TEST_BUF(0x0); 147M DI_CP_SEL(0x2); DI_CP_OFFSET(0x0); DI_LPF_SEL(0x3); DI_VCO_GAIN(0x4); 160M DI_TRIM_VOL(0x4); DI_EN_DIV2(0x0); DI_EN_LDO(0x1); DI_EN_LDO2(0x1);...
  • Page 8 Name Mode Default Description sdadc clk select 0：addc_clk Sdadc_bqclkx2_sel 1: addc_clkdiv2 XSOC double enable 0：disable XSOC_x2en_a 1：enable Saradc clk select 0x0：rc2m 29:28 Sarclk_sel 0x1：XSOC_div4 27:26 — — — — Timer increase clk asynchronization select 0：选择系统时钟同步的 timer increase clk Tmrck_async_sel 1：选择 timer increase clk Timer increase clk select 0x0: osc32k 24:23...
  • Page 9 Name Mode Default Description 0x5：xosc52m 0x6：pll1out 0x7：rc2m 0x8：rtc_rc2m 0x9：sys_clk 0xa：bt26m 0xb：bt_sx_tsck 0xc：dac_clk Bt13m clk select 0：bt13m clk Bt13m_sel 1：PF0 input Bt52m clk select： 11:10 Bt52m_sel 0:xosc52m 1: invalid Bt26m clock select： Bt26m_sel 0: select bt26m clk 1: invalid Sys pll select Syspll_sel[0]:0 select pll_clk,1 select xosc52m Syspll_sel_a Syspll_sel[1]:0 select pll_clk/xosc52m...
  • Page 10 Name Mode Default Description aec clk enable bit 0: disable 1: enable spf clk enable bit 0: disable 1: enable sdadcm clk enable bit SDADCM 0: disable 1: enable recsrc clk enable bit RECSRC 0: disable 1: enable rtc clk enable bit RTCC 0: disable 1: enable...
  • Page 11 Name Mode Default Description mbist clk enable bit MBIST 0: disable 1: enable port clk enable bit PORT 0: disable 1: enable audec clk enable bit AUDEC 0: disable 1: enable sdadc clk enable bit SDADC 0: disable 1: enable usb clk enable bit 0: disable 1: enable...
  • Page 12 Name Mode Default Description 1: enable Ram3 clk enable bit RAM3 0: disable 1: enable Ram2 clk enable bit RAM2 0: disable 1: enable Ram1 clk enable bit RAM1 0: disable 1: enable Ram0 clk enable bit RAM0 0: disable 1: enable Rom1 clk enable bit ROM1...
  • Page 13 Name Mode Default Description FT clk select Ft_clkpin_sel 0x0:PF5 0x1:PA7 Iic clk select Iicclk_sel 0x0: rc2m 0x1: XSOC_div8 Pll0sdmsel_a XSOC_lpm enable bit XSOC_lpm_gen 0x0: disable 0x1: enable — — — — Aecram div1 select Aecram_div1_sel 0x0:disable 0x1:enable Usb6p5_sel Osc32k select K32_tscsel 0x0:osc32k 0x1:cp_pin...
  • Page 14 Name Mode Default Description 0x1:xosc52m 0x2:dac_clk/xosc52m(depend on iisclk_sel[0]) 0x3:iis_div_clk — — — — Ir rx clk select 0x0:XSOC_32k Irrxclksel 0x1:XSOC_div 0x2:osc32k 0x3:rc32k — — — — DAC clk select 0x3:adda_clk Adda_clksel 0x2:XSOC 0x1:adpll_div_clk 0x0:0 Name Mode Default Description efuse clk enable bit EFUSE 0: disable 1: enable...
  • Page 15 Name Mode Default Description Rom3 clk enable bit ROM3 0: disable 1: enable Rom2 clk enable bit ROM2 0: disable 1: enable aecram clk enable bit AECRAM 0: disable 1: enable 22:17 — — — Tick0 clk enable bit TICK0 0: disable 1: enable piano clk enable bit...
  • Page 16 Name Mode Default Description — — — sbcec clk enable bit SBCEC 0: disable 1: enable iis clk enable bit 0: disable 1: enable Irrx clk enable bit IRRX 0: disable 1: enable src clk enable bit 0: disable 1: enable —...
  • Page 17 Name Mode Default Description rnn clk enable bit 0: disable 1: enable drc pclk enable bit DRC_PCLK 0: disable 1: enable Dacdiv2 clk enable bit DACDIV2SEL 0: disable 1: enable Dac25 clk enable bit DAC_25 0: disable 1: enable dac clk enable bit 0: disable 1: enable adddiv clk enable bit...
  • Page 18 Name Mode Default Description iic clk enable bit 0: disable 1: enable Name Mode Default Description 26:23 piano_div PIANO divide 26:23 cvsd_div CVSD divide 22:19 plc_div divide 18:16 usb_div divide 15:12 sbcec_div SBCEC divide 11:8 iis_div divide src_div divide aec_div divide Name Mode...

  • Page 19: Memory Access

    3 Memory Access Table 2 Memory Access Cache AUDEC SBCENC RDFT Number Channel SRAM0~2 SRAM3~4 BT_RFTS AUBUF AUBUF1 ANCDAC DACDMAO SDADC SPI0 SPI1 CVSD PSRC RDFT AUDEC SBCENC GPDMA HSUT DMA supported peripherals:HSUART, SPI, SD, USB and IIS,SDADC,SDDAC. Note: （1） RDFT refers to Fourier transform. （2）...

  • Page 20: Low Power Mode

    4 Low Power Mode GW3323 supports two low-power modes： 4.1 1. sleep mode,500uA Sleep mode will auto gate system clock, close memory access, close RC2M, but some asyn clock should be disable by software. Sleep mode wake up source as follow. After wakeup, software run continue or enter interruptif enable.
  • Page 21 Reset after wake-up www.geehy.com Page 21...

  • Page 22: Interrupts

    5 Interrupts 5.1 Feature The Bluetooth priority has been set in the library, from high to low: Bluetooth> timers and other hardware interrupts>threading. The print function in the interrupt shall be the printk function, the global variable inside shall be declared volatile, and the interrupt function shall be placed in the isr area;...
  • Page 23 Interrupt Address Description number Icache miss interrupt 0x20 Dcache Miss interrupt BT interrupt BLE interrupt 0x24 BTDM interrupt 0x28 Software interrupt 0x2c Timer0 interrupt 0x30 Timer1 interrupt 0x34 Timer2 interrupt 0x38 IR receiver interrupt 0x3c interrupt 0x40 interrupt Audio buffer 0 interrupt 0x44 Audio buffer 1 interrupt SDADC DMA interrupt...

  • Page 24: Interrupts Special Registers

    Interrupt Address Description number SRC interrupt 0x84 0x88 Port interrupt 0x8c IIS interrupt 0x90 SARADC interrupt RTC and alarm interrupt LVD interrupt 0x94 WDT interrupt IIC interrupt 0x98 BSP interrupt Tick0 interrupt 0x9c Tick1 interrupt Note: （1） The related interrupts can be configured by calling sys_irq_init (int vector, int pr, isr_t isr), and this part is not open to customers.
  • Page 25 Name Mode Default Description GIEM Write 1 enable Global interrupt enable mask 15:8 Unused Unused HPINTEN Write 1 enable High priority interrupt LPINTEN Write 1 enable Low priority interrupt Write 1 enable Global interrupt Name Mode Default Description 31:17 Unused GIEMDIS Write 1 disable Global interrupt enable mask 15:8...
  • Page 26 Name Mode Default Description Interrupt 31 to 0 priority selection 1 bit; {PICPR1, PICPR} 00: low priority interrupt 31:0 IntPR1 01: high priority interrupt 10: high priority 2 interrupt 11: high priority 3 interrupt Name Mode Default Description 31:8 BADR 0x800 Interrupt entry address Name...

  • Page 27: Watchdog

    6 WatchDog 6.1 User Guide configure WDT reset or interrupt Select WDT time out Clear WDT 6.2 WDT Special Function Registers Name Mode Default Description WDT time out pending WDTPND 0: no pending 1: pending 30:28 Unused WDT time select bit write enable 27:24 TMRSEL_WR When write 0xa, bit20~bit22 can be write to TMRSEL, other value...
  • Page 28 WDT clear bit WDTCLR When write 0xa, WDT counter and WDTPND will be clear www.geehy.com Page 28...

  • Page 29: Gpio Management

    7 GPIO Management 7.1 Features Control GPIO input/output direction by using direction register; Internal pull-up/pull-down resistor by using pull-up/pull-down resistor control register; Select suitable output driving current capability; 7.2 GPIO internal block diagram Figure 4 GPIO internal block diagram 7.3 GPIO general control register Name Mode Default...
  • Page 30 Name Mode Default Description 31:8 Unused Clear PAx output data. Write 1 clear output data. Write 0 affect GPIOACLR nothing. Name Mode Default Description 31:8 Unused PAx direction control GPIOADIR 0xFF 0: Output 1: Input Name Mode Default Description 31:8 Unused PAx 10KΩ...
  • Page 31 Name Mode Default Description PAx 200KΩ pull-down resister control. Valid when PAx is used as input GPIOAPD 0: disable 1: enable Name Mode Default Description 31:8 Unused PAx 300Ω pull-up resister control. Valid when PAx is used as input GPIOAPU 0: disable 1: enable Name...

  • Page 32: Gpio Function Mapping

    7.4 GPIO function mapping Name Mode Default Description UART1 RX mapping 0000: no affect 0001: map to G1 31:28 UT1RXMAP 0010: map to G2 0011: map to TX pin by UT1TXMAP select 1111: Clear these bits Others is reserved UART1 TX mapping 0000: no affect 0001: map to G1 27:24...
  • Page 33 Name Mode Default Description 31:12 — — — — UART2 RX mapping 0000: no affect 0001: map to G1 11:8 UT2RXMAP 0010: map to G2 0011: map to TX pin by UT2TXMAP select 1111: Clear these bits Others is reserved UART2 TX mapping 0000: no affect 0001: map to G1...

  • Page 34: External Port Interrupt Wake Up

    Name Mode Default Description 0001: map to G1 1111: Clear these bits Others is reserved Timer3 capture Pin mapping 0000: no affect 0001: map to G1 0010: map to G2 0011: map to G3 TMR3CPTMAP 0100: map to G4 0101: map to G5 0110: map to G6 0111: map to G7 1111: Clear these bits...
  • Page 35 Wakeup circuit 2 Wakeup circuit 3 Wakeup circuit 4 WKO(PB5) Wakeup circuit 5 PORT_INT_FALL Wakeup circuit 6 PORT_INT_RISE Wakeup circuit 7 Name Mode Default Description 31:17 Unused Wake up interrupt enable WKIE 0: disable 1: enable 15:8 Unused Wake up input 7~0 enable WKEN 0: disable 1: enable...
  • Page 36 Name Mode Default Description Unused 15:0 Name Mode Default Description Port interrupt 0~31 enable bit 31:0 PORTINTEN 0: disable 1: enable Name Mode Default Description Port interrupt 0~31 edge select bit 31:0 PORTINTEDG 0: rise edge 1: fall edge www.geehy.com Page 36...

  • Page 37: Dma

    8DMA 8.1 Feature DMA supports such peripherals as HSUART, SPI, SDIO, and USB. (10) DMA cannot transmit data between registers or transfer data between two memory addresses. (11) DMA-SPI only supports transmitting and does not support receiving 8.2 Functional configuration Table 6 Functions DMA receiving DMA transmitting...

  • Page 38: Timer

    The official SDK with the system uses timer0 as tick, with a frequency of 1MHz. The PWM of GW3323 timer is in edge-aligned mode (the pulse counter is in cycle count-up with an initial count value of 0), without center-aligned mode (the pulse counter is in bidirectional counting with an initial count value of 0), and without complementary output mode.

  • Page 39: Timer Clock Select

    9.2 Timer clock select Figure 5 Timer clock block diagram 9.3 Timer0/1/2 Special Function Registers Name Mode Default Description 31:10 Unused Timer overflow pending TPND 0: not overflow 1: overflow Unused Timer overflow interrupt enable 0: disable 1: enable Increase source select INCSRC 0: select TMR_INC 1: select external PIN...

  • Page 40: Timer3/4/5 Special Function Registers

    Name Mode Default Description Timer Enable Bit TMREN 0: Disable 1: Enable Name Mode Default Description 31:16 Unused Timer overflow pending clear bit TPCLR 0: inactive 1: clear pending Unused Name Mode Default Description Timer counter. TMRCNT will increase when timer is enabled. It overflows when 31:0 TMRCNT TMRCNT = TMRPR, TMRCNT will be clear to 0x0000 when...
  • Page 41 Name Mode Default Description Timer overflow interrupt enable 0: disable 1: enable Increase source select INCSRC 0: select TMR_INC 1: select external PIN Timer Capture edge select 00: No Capture CPTEDSEL 01:Capture PIN rising edge 10: Capture PIN falling edge 11: Capture PIN edge Increase clock selection 00: System Clock...
  • Page 42 Name Mode Default Description 31:16 Unused Timer pwm0 duty 15:0 TMRDUTY0 PWM0 low level length is TMRDUTY0+1 PWM 0 high level length is TMRPR-TMRDUTY0 Name Mode Default Description 31:16 Unused Timer pwm1 duty 15:0 TMRDUTY1 PWM1 low level length is TMRDUTY1+1 PWM1 high level length is TMRPR-TMRDUTY1 Name Mode...

  • Page 43: Rtc

    10 RTC 10.1 Features Support 32bit Independent power supply real time counter Support alarm interrupt and second interrupt 10.2 Special Function Registers Name Mode Default Description 31:23 Unused INBOX state INBOX 0: out of box 1: in box VUSB off state VUSBOFF 0: online 1: off state...

  • Page 44: Independent Power Rtc Registers

    Name Mode Default Description 11: System Clock divide 32 Unused Name Mode Default Description 31:19 Unused CWKSLPPND Write 1 will clear RTC wakeup sleep pending CALMPND Write 1 will clear RTC alarm pending 16:0 Unused 10.3 Independent Power RTC Registers Name Mode Default...
  • Page 45 Name Mode Default Description CLK2M in RTC power domain source select bit CLK2MRTCSSEL 0: RTC 2M 1: XOSC 26M divide 8(3.25M) RTC first power up flag PWRUP1ST 0: not first power up 1: first power up External 32K select EXT32KS 0: use RTC internal 32K osc 1: use external 32K osc Touch key between core interface enable bit TKITF_EN...
  • Page 46 Name Mode Default Description SEL VDD pullup enable SELVDDPU 0: disable 1: enable 32K osc select bit 32KSEL 0: 32.768K 1: 32K Reserve,can’t be changed default value. Reserve,can’t be changed default value. Reserve,can’t be changed default value. Name Mode Default Description Unused Touch key long press wakeup enable bit...
  • Page 47 Name Mode Default Description VDDCORE enable bit VCOREEN 0: disable 1: enable VDDIO enable bit VIOEN 0: disable 1: enable BUCK enable bit BUCKEN 0: disable 1: enable Name Mode Default Description Reserve,can’t be changed default value. Reserve,can’t be changed default value. Reserve,can’t be changed default value.
  • Page 48 Name Mode Default Description INBOX wake up pending INBOXP 0: no pending 1: pending VUSB wake up pending VUSBP 0: no pending 1: pending WK pin wake up pending 0: no pending 1: pending When write: RTC 1 second pending clear 0: no affect 1: clear 1s pending RTC1SPC...
  • Page 49 WK pin filter select bit 00:8ms 01:32ms WKPFSEL 10:128ms 11:512ms Name Mode Default Description Unused WK pin 10s reset enable 0xa: disable WKP10SEN Others: enable www.geehy.com Page 49...

  • Page 50: Uart

    11 UART 11.1 Features UART is a serial port capable of asynchronous transmission. The UART can function in full duplex mode. Table 7 I/O ports corresponding to serial channels Channe Channe Channe Channe Channe Channe Channe Channe Channe Channe UART l G1 l G2 l G3...
  • Page 51 Clock source select CLKSRC 0: system clock 1: uart_inc Two Stop Bit enable SB2EN 0: 1-bit Stop Bit 1: 2 bit Stop Bit Transmit Interrupt Enable TXIE 0 = Transmit interrupt disable 1 = Transmit interrupt enable Receive Interrupt Enable RXIE 0: Receiver interrupt disable 1: Receiver interrupt enable...
  • Page 52 UART Data UARTDAT Write this register will load the data to transmitter buffer. Read this register will read the data from the receiver buffer.. www.geehy.com Page 52...

  • Page 53: Hsuart

    12 HSUART 12.1 Features Support full duplex mode Support async clock between UART interface part and control part Support interrupt Support 8/9 bit data mod，but not data parity checking. Support 16 bit baud rate setting. UART TX： Support single byte TX ...

  • Page 54: Tx N Byte With Dma

    Wait for TXPND to change to ‘1’, or wait for interrupt (10) Clear PNDing 12.2.3 TX n byte with DMA Configure GPIO in the correct direction. Configure HSUT0CON CLKSRC bit for high speed interface working source clock Configure HSUT0CON DMA mode ,8bit mode, 1/2 stop bit mode ConfigureHSUT0BAUD baud-rate Configure TX DMA start address HSUT0TXADR Enable UTXEN by setting...

  • Page 55: Dma Rx Timer Mode

    (12) Clear PNDing, and will clear HSUT0FIFOCNT at the same time Reading from SRAM: get start address from HSUT0FIFOADR or program save variable get data count from HSUT0FIFOCNT or program save variable read N byte data from SRAM if not DMA loop buffer mode, clear RXPND will clear HSUT0FIFOCNT if DMA loop buffer mode, write N to SUBRXCNT（HSUT0CPND[16:0]）to dec HSUT0FIFOCNT Reading from HSUT0FIFO...
  • Page 56 Figure 6 DMA High Speed Serial Port Sending Function Table 9 RXPND（ RX Hang-up） Flag Bit Read Value Buffer Mode DMA Mode Notes ------- ------- ------- ------- HSUT0TMRCNT RXPND（ RX Hang-up） RX and WRITE n byte RX 1 byte done enable and TMROV to SRAM finish Table 10 RXOV_set...
  • Page 57 Enter RXPND process first，get HSUT0FIFOCNT，and read data from RXFIFO Enter RXOVPND，get HSUT0FIFOCNT，and read data from RXFIFO。 HSUT0FIFOCNT ！= 0 If RXPND setting by received RXCNT byte data  HSUT0FIFOCNT = 0 If RXPND setting by RXOVPND  Clear RXOVPND It will be also clear RXFIFOCNT and initial RXFIFO_ADR to current RXWR_ADR by ...

  • Page 58: Hsuart Special Function Registers

    12.3 HSUART Special Function Registers Name Mode Default Description 31:18 Unused HS TX interface setting update UPTXCFG 0: N/A 1: update configure from sysclk to hsuartclk domain HS RX interface setting update UPRXCFG 0: N/A 1: update configure from sysclk to hsuartclk domain RX TIMER Overflow flag TMROV 0: RX timer not overflow...
  • Page 59 Name Mode Default Description 31:16 SUBRXCNT* Decrease RXFIFOCNT at RX DMA mode RX timer overflow flagl clear CTMROV 0: N/A 1:Clear flag RX Fail clear CRXFAIL 0: N/A 1: Clear RX fail flag TX pending clear CTXPND 0: N/A 1: Clear TX Pending UART RX Enable Bit URXEN_NS 0: Disable UART RX module...
  • Page 60 Name Mode Default Description 31:16 Unused 15:0 TXCNT HSUART TX DMA byte counter Name Mode Default Description 31:0 HSUTTXADR HSUART TX DMA start address Name Mode Default Description 31:16 Unused 15:0 RXCNT HSUART RX DMA byte counter Name Mode Default Description 31:16 Unused...
  • Page 61 Name Mode Default Description 31:8 Unused RXFIFO read from SRAM done 0: read not finish RXFIFO_DONE 1; read done Auto clear by kick RXFIFO_RD bit RX read pluse 0: N/A RXFIFO_RD 1: read fifo kick start UART RX Data Read this register will read the data from the RXFIFO receiver SRAM buffer Name...

  • Page 62: Spi

    13 SPI 13.1 Features The chip has one SPI. The SPI is connected to the external I/O port by tying a cable and is available to users. Flash SPI is a 2-frequency division of the system clock. The SPI flash start address is 0x1000 0000.
  • Page 63 SPI DMA Mode Operation Flow: Set IO in the correct direction and data width mode. Select RXSEL for DMA direction Configure clock frequency Select one of the four timing modes Enable SPI module by setting SPIEN to ‘1’ Set SPIIE ‘1’ if needed configure SPI0DMAADR；...

  • Page 64: Spi Special Function Registers

    13.3 SPI Special Function Registers Name Mode Default Description 31:17 Unused SPI pending SPIPND 0: not finish SPI rx/tx 1: finish SPI rx/tx 15:14 Unused SPI software hold enable HOLDENSW 0: disable 1: enable SPI hold enable when bt tx HOLDENTX 0: disable 1: enable...
  • Page 65 Name Mode Default Description 31:16 Unused SPI Baud Rate 15:0 SPI0BAUD Baud Rate =Fsys clock / (SPI_BAUD+1) Name Mode Default Description 31:17 Unused SPICPND Write 1 will clear SPI pending 15:0 Unused Name Mode Default Description 31:8 Unused SPI Data SPI0BUF Write this register will load the data to transmitter buffer.

  • Page 66: Iic

    14 IIC 14.1 Features Support IIC one master Support asynchronous clock source from RC2M or XOSC26M Support out data maximum 4 Byte Support in data maximum 4 Byte 14.2 User Guide IIS master mode Operation Flow: Configure IO mapping, SDA set pullup enable ...

  • Page 67: Iic Special Function Registers

    14.3 IIC Special Function Registers Name Mode Default Description DONE IIC DONE flag RX IIC slave ACK status ACKSTATUS 0: RX ACK 1: RX NAK DONE flag clear CLR_DONE 1: clear Kick start 1: Kick start Clear All status CLR_ALL 1: clear 26:10 Rev.
  • Page 68 Name Mode Default Description ADR0_EN IIC TX adr 0 enable CTL0_EN IIC TX ctl 0 enable START0_EN IIC TX start 0 enable RX/TX data counter 0: 0 byte DATA_CNT 1: 1 byte … N: N byte IIC clock configuration : IICCLK = source clk / (preclkdiv+1) SCL = IICCLK / (posdiv+1) Name...

  • Page 69: Adc

    15 ADC 15.1 Features This ADC has the following characteristics: Support 16 channel,10 bit sampling frequency The maximum sample rate is 78k/s; SARADC bit clock maximum is 1MHz ADC has internal 100K pull up resister 15.2 Channel select Code for reference: /***************************************************************************** * Module : ADC Path Selection List...

  • Page 70: Adc_Ctl Special Function Registers

    15.4 ADC_CTL Special Function Registers Name Mode Default Description 31:20 Unused Saradc auto enable analog enable bit ADCAEN 0: disable 1: enable Saradc auto enable analog IO enable bit ADCANGIO 0: Disable 1: Enable Saradc interrupt enable bit ADCIE 0: Disable 1: Enable Saradc enable bit ADCEN...
  • Page 71 Name Mode Default Description Channel 3 internal pullup enable bit CH3PUEN 0: Disable 1: Enable Channel 2 internal pullup enable bit CH2PUEN 0: Disable 1: Enable Channel 1 internal pullup enable bit CH1PUEN 0: Disable 1: Enable Channel 0 internal pullup enable bit CH0PUEN 0: Disable 1: Enable...
  • Page 72 Name Mode Default Description Channel 5 enable bit CH5EN 0: Disable 1: Enable Channel 4 enable bit CH4EN 0: Disable 1: Enable Channel 3 enable bit CH3EN 0: Disable 1: Enable Channel 2 enable bit CH2EN 0: Disable 1: Enable Channel 1 enable bit CH1EN 0: Disable...
  • Page 73 Name Mode Default Description 11: 8 SARADC_CLK Channel 8 setup time 00:0 SARADC_CLK 17:16 CH8ST 01:2 SARADC_CLK 10: 4 SARADC_CLK 11: 8 SARADC_CLK Channel 7 setup time 00:0 SARADC_CLK 15:14 CH7ST 01:2 SARADC_CLK 10: 4 SARADC_CLK 11: 8 SARADC_CLK Channel 6 setup time 00:0 SARADC_CLK 13:12 CH6ST...
  • Page 74 Name Mode Default Description 31:10 Unused SADCDAT SARADC data, channel 0 to channel 15 register www.geehy.com Page 74...

  • Page 75: Dac

    16 DAC 16.1 Feature Output the offset value of DC at up to 780KHz (1.3us) to change the output DAC level; 16.2 Control use my_dac_init() sets the output DAC level for starting DAC_R or DAC_L pin set_bia_voltage_reg_R() sets DAC_R level; set_bia_voltage_reg_L() sets DAC_L level www.geehy.com Page 75...

  • Page 76: Usb

    17.1 Feature The full speed of USB Devise is 12 Mbits/s, D + internal pull-up resistor of USB. 17.2 Control use usb_detect();//this function will detect whether the USV is connected or disconnected usb_bulk_send();//batch transmission of USB data, waiting to be read by the host usb_insert_callback();//callback function for engineering call after usb is inserted usb_ep_config();//functions for configuring input and output ports www.geehy.com...

  • Page 77: Power Management

    Power Management 18.1 Charging process After the vusb pin is connected to 5V voltage, the chip first judges whether the voltage connected to the vusb is high (the vusb voltage should be 0.2v higher than the battery voltage and be greater than 4.5v) (this condition can be configured whether to take effect). If the vusb voltage meets the charging conditions, enter the charging mode.

  • Page 78: Bluetooth

    Bluetooth 19.1 Feature Core specifications: √ BR, √ VEDR, √ LE Power class: Class1(11dbm >= Pmax >=4dbm) BREDR modulation modes: √GFSK, √π/4-DQPSK, √8DPSK BREDR parameters: Image frequency (+2Mhz), VaIue n(3) LE modulation modes: √IM PHY, √2M PHY, ×coded PHY, ×Stable Modulation Index(TX &...

  • Page 79: Spp Use And Development In Sdk

    Figure 7 Flow Control Mechanism of Credit Initialize and inform each other of their RX credt A packet of data A packet of data A packet of data A packet of data TX credit is 0, stop sending Supplementary credit Resume sending Both sides of the serial port will have the count of two credits, i.e.

  • Page 80: Ble Protocol

    19.2.2.2 Instructions for API Two API are opened to inform the other side of SPP to supplement and update credit, i.e. void spp_set_rx_new_credit(uint8_t credit) and int spp_notify_rx_buffer_len(u16 len). The former void spp_set_rx_new_credit(uint8_t credit) is to directly notify the Bluetooth underlying layer to inform the other side to update the credit. The latter int spp_notify_rx_buffer_len(u16 len) is to divide the remaining available length of the incoming buffer by the MTU (maximum transmission unit, namely the maximum length of a packet of data) of the SPP to obtain the minimum number of data packets that can be received...

  • Page 81: Flow Control Mechanism Of Ble Protocol

    Description UUID Properties Notify Characteristic 0xFF14 Notify 19.3.1 Flow control mechanism of BLE protocol MTU exchange is to set the maximum amount of data that can be exchanged in a PDU between the master and slave. Through MTU exchange and confirmation by both parties (Note that this MTU is not negotiable, but only informs the other party.

  • Page 82: Fota Upgrade

    19.3.2.3 Bluetooth transmits the function return value If ble_tx_notify returns 0, it indicates successful transmission; if the transmission is unsuccessful, return the error code, and actually not a single byte is transmitted. So the transmission fails, and the entire data needs to be transmitted again. Decimal 86 means "packet is empty, or the transmission length is greater than the buf size".

  • Page 83: Revision History

    20 Revision history Table 14 Document Revision History Date Revision Change History 2023.5.10 Add charging module, USB, BLE, clock register and other 2023.8.24 instructions; Change the description of other modules. www.geehy.com Page 83...
  • Page 84 Statement This document is formulated and published by Geehy Semiconductor Co., Ltd. (hereinafter referred to as “Geehy”). The contents in this document are protected by laws and regulations of trademark, copyright and software copyright. Geehy reserves the right to make corrections and modifications to this document at any time.
  • Page 85 NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY USERS OR THIRD PARTIES). 8. Scope of Application The information in this document replaces the information provided in all previous versions of the document. © 2023 Geehy Semiconductor Co., Ltd. - All Rights Reserved www.geehy.com Page 85...

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