ICS Advent PCI-DIO48 Series Product Manual page 28

To read the inputs at Port A and the upper nybble of Port C:
30 X=INP(BASEADDR)
40 Y=INP(BASEADDR+2)/16
To set outputs high (1) at Port B and the lower nybble of Port C:
50 OUT BASEADDR+1,&HFF
60 OUT BASEADDR+2,&HF
Enabling/Disabling I/O Buffers
When using the tristate mode (Jumper in the TST position), the method to disable the I/O buffers
involved writing a control word to the Control Register at Base Address +3 and Base Address +7.
This control word was required to have bit D7 (the most significant bit) set. That meant that the
PPI translated it as an "active mode set" and reset the output data latches to "zero" on all output
ports and the output buffers were disabled. However, if the buffers are to be enabled at a later
time, the output latches will be in a "zero" state. For example, if all the outputs were 1's, they will
now be 0's and the output buffers will be disabled. This problem can be resolved as follows.
Two computer I/O bus addresses are available that permit you to enable or disable the I/O buffers
at will, without programming the PPI mode. Buffers for Port 0 bits are enabled/disabled at Base
Address +8 and buffers for Port 1 bits are enabled/disabled at Base Address +9. To enable the
buffers and to set outputs to the desired state, you can write to the Control Register with bit D7
low. If you wish to subsequently disable the buffers, you can write to the Control Register with bit
D7 high. In this way you can enable/disable the output buffers without programming the PPI
mode.
When writing a command byte to these cards while the TST jumper is installed, the PPI output
buffers are disabled. Thus, when you desire to to change the mode, you must first set the new
mode and then enable the buffers. Enabling the buffers can be done at either Base Address +3 (or
+7) or Base Address +8 (or +9).
Manual 00650-529-1
'Read Port A
'Read Port C Hi
'Turn on all Port B bits
'Turn on all bits of Port C
lower nybble
Note
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