Denon DNP-800NE Service Manual page 24

Pin I/O Port Name
42 RESERVED P15/RXD1/IRQ5
43 RESERVED P14/IRQ4
44 RESERVED P13/TXD2/IRQ3
45 S_FLASH_CLK P12/RXD2/IRQ2
46 VCC_USB VCC_USB
47 R E - USB0_DM
ASSIGNABLE
48 R E - USB0_DP
ASSIGNABLE
49 VSS_USB VSS_USB
50 S _ F L A S H _ P56
HOLD
51 S_FLASH_WP P55/IRQ10
52 S_FLASH_SO P54
53 S_FLASH_SI BCLK/P53
54 S_FLASH_CS P52/RXD2
55 M C K _ P51/SCK2
SEL_45/49
56 DAC_CLK_SEL P50/TXD2
57 VSS VSS
58 DAC1_MUTE P83
59 VCC VCC
60 UB PC7/TXD8/IRQ14
61 RESERVED PC6/RXD8/IRQ13
62 A_PW_SHORT PC5
63 VARI_ON/OFF P82/TXD10
64 DIR2_GPO P81/RXD10
65 DIR2_DEMP P80/SCK10
66 DIR2_ERR PC4
67 C_PLD_CLK PC3/TXD5
68 C_PLD_MDO P77/TXD11
69 C_PLD_MDI P76/RXD11
70 C_PLD_CS PC2/RXD5
I/O STBY MODE Function
NORMAL NETWORK
I I I USBB(XMOS) Control Pin, IRQ5
I I I USBB(XMOS) Control Pin, IRQ4
I I I USBB(XMOS) Control Pin, USBB Insert
Detect
O O/L O/L [K(CN) Region Model Only] GD25Q32-
6P, CLK
Power Supply Pin
NC (Open)
NC (Open)
Ground pin
I/O I I [K(CN) Region Model Only]
GD25Q32-7P,HOLD# ( IO3 )
I/O I I [K(CN) Region Model Only]
GD25Q32-3P,WP# ( IO2 )
I/O I I [K(CN) Region Model Only]
GD25Q32-2P,SO ( IO1 )
I/O I I [K(CN) Region Model Only]
GD25Q32-5P,SI ( IO0 )
O O/L O/L [K(CN) Region Model Only]
GD25Q32-1P, CS
O O/L O/L DAC Input MCK Select (49MHz(H) or
45MHz(L))
O O/L O/L DAC Input MCK Select (80MHz(H) or
45MHz/49MHz(L))
Ground Pin
O O/L O/L DAC1 (Fixed Out, Variable Out, H/P
Out) Mute Control Pin
Power Supply Pin.
Emulator Connection Pin
OPEN
I I I Detect DC Protection (Audio B'D
Power Supply Short) (EVOL_CLK =>
A_PW_SHORT)
O O/L O/L Power Off the Variable Out Circuit
(EVOL_DATA => VARI_ON/OFF)
I I I DIR2 (LC89091JA) General Purpose
Signal Input
I I I DIR2 (LC89091JA) De-Emphasis Flag
Input
I I I DIR2 (LC89091JA) S/PDIF Unlock Flag
Input
O O/L O PLD Control Data Clock Output
I I I PLD Control Data Input
O O/L O PLD Control Data Output
O O/L O PLD Control Data Chip Select
Pin I/O Port Name
71 RESERVED P75
72 I O E X P _ I 2 C _ P74
SDA
73 I O E X P _ I 2 C _ PC1
SCL
74 VCC VCC
75 IOEXP_/INT PC0
76 VSS VSS
77 OLED_P_CONT P73
78 OLED_D7 PB7/TXD9
79 OLED_D6 PB6/RXD9
80 OLED_D5 PB5
81 OLED_D4 PB4
82 OLED_D3 PB3
83 OLED_D2 PB2
84 OLED_D1 PB1/TXD4/TXD6
85 EL_CS P72
86 EL_RESET P71
87 OLED_D0 PB0/RXD4/RXD6/IRQ12 O
88 EL_DC PA7
89 EL_RD PA6
90 EL_WR PA5
91 VCC VCC
92 RESERVED PA4/TXD5/IRQ5-DS
93 VSS VSS
94 DIR_DIN PA3/RXD5/IRQ6-DS
95 DIR_DOUT PA2/RXD5
96 DIR_CE PA1/MTIOC0B/IRQ11
97 DIR_CLK PA0
98 DIR_INT P67/IRQ15
99 DIR_RESET P66
100 DIR_NPCM P65
101 DAC2_RESET PE7/IRQ7/AN5
102 RESERVED PE6/IRQ6/AN4
103 VCC VCC
104 RESERVED P70
105 VSS VSS
106 I2C_SDA PE5/IRQ5/AN3
107 I2C_SCL PE4/AN2
24
I/O STBY MODE Function
NORMAL NETWORK
OPEN
I/O I/O I/O I/O Expander I2C SDA
I/O I/O I/O I/O Expander I2C SCL
Power Supply Pin
I I I I/O Expander INT input
Ground pin
O O/L O OLED Power Control Pin
O O/L I Data bus for OLED
O O/L I Data bus for OLED
O O/L I Data bus for OLED
O O/L I Data bus for OLED
O O/L I Data bus for OLED
O O/L I Data bus for OLED
O O/L I Data bus for OLED
O O/L O/L If logic level "L", Enable communication
with OLED.
O O/L O/L OLED RESET Pin. Logic Level
"L"=RESET
O/L I Data bus for OLED
O O/L O/L Data/Commando Switch.
"H"=Data, "L"=Command
O O/L O/L EL Read
O O/L O/L EL Write
Power Supply Pin
O O/L O/L RC-5 Output
Ground Pin
O O/L O/L DIR (PCM9211) Control Pin
I I I DIR (PCM9211) Control Pin
O O/L O/L DIR (PCM9211) Control Pin
O O/L O/L DIR (PCM9211) Control Pin
I I I DIR (PCM9211) Control Pin
O O/L O/L DIR (PCM9211) Control Pin
I I I DIR (PCM9211) Control Pin
O O/L O/L DAC2 (AK4458VN) Reset Pin
I I I I2C SDA Reading Pin
Power Supply Pin
I I I I2C SCL Reading Pin
Ground Pin
I/O I I I2C Data (XMOS[USBB]
, ES9016K2M[DAC1], AK4458VN[DAC2],
CS2000[PLL], NJU72343V[E-VOL])
I/O I I I2C Clock (XMOS[USBB]
, ES9016K2M[DAC1], AK4458VN[DAC2],
CS2000[PLL], NJU72343V[E-VOL])