Denon DNP-800NE Service Manual page 10

SCH02 FPGA
6A
PLD_DAC1_DATA/DSDR.
From
PLD PLD_DAC1_LRCK/DSDL.
PLD_DAC1_PBCK/DBCK.
PLD_DAC1_MCK.
TO A6
FPC500
1.0-16-10PB-2
1 MM PITCH
nCS Vcc
DATA Vcc
Vcc DCLK
GND ASDI
IC502
EPCQ16SA8N
FPC501
04-6244-410-010-846+
0.5MM PITCH
R656
NM
GND LINE POWER+ LINE POWER- LINE ANALOG AUDIO
1 2 3
A1 A2 A3 A4
A
33_VCCIO EMPHASIS AL32_TEST4
B1 B2 B3 B4
B
FS0 DGND AL32_TEST5
C1 C2 C3 C4
C
ASDO_DATA1 AL32_TEST3
D1 D2 D3 D4
FLASH_NCE_NCSO
D
R581 0-1608
PCM_DATA/DSD_DATA_R_IN C16
E1 E2 E3 E4
R582 0-1608
PCM_LRCK/DSD_DATA_L_IN D15
E
R583 0-1608 FS1 DGND 33_VCCIO
D16
PCM_BCK/DSD_DBCK_IN
R585 0-1608
MCK_IN B8
F1 F2 F3 F4
F
G1 G2 G3 G4
G
33_VCCIO
H1 H2 H3 H4
H
ALTERA_DCLK DATA0 FTCK
J1 J2 J3 J4
J
FPGA_RESET_IN NCE
K1 K2 K3 K4
K
33_VCCIO
L1 L2 L3 L4
H14 L
CONF_DONE
H5
NCONFIG
M1 M2 M3 M4
J3
NCE
M
33_VCCIO
N1 N2 N3 N4
N
H2
DATA0
P1 P2 P3 P4
D2
FLASH_NCE_NCSO
P
R1 R2 R3 R4
ALTERA_DCLK H1
R
C1 DGND
ASDO_DATA1
T1 T2 T3 T4
+3.3V_D
T
R595 10K-1608
33_VCCIO FPGA_RES1
L16
CONT4.
R596 10K-1608
NSTATUS F4
IC501
+2V5_FPGA
EP4CE15F17C8N
H3
FTCK
FTDO J4
J5
FTMS
FTDI H4
R722 NM
33_VCCIO TEST1
R720 0-1608
25_VCC NET00279
R630 0-1608
R614 10K-1608
FPGA_VER_CONT. +3.3V_D
B0
DIGITAL AUDIO STBY POWER
4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
/INT_EXT FPGA_RES2 FPGA_RES3 FPGA_RES4 FPGA_VER_CONT
TEST1
B5 B6 B7 B8 B9 B10 B11 B12 B13 B14
MCK_IN
C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
33_VCCIO
33_VCCIO DGND 33_VCCIO DGND 33_VCCIO
D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
12_VCC DGND DGND 12_VCC
E5 E6 E7 E8 E9 E10 E11 E12 E13 E14
DGND DGND DGND DGND 33_VCCIO
F5 F6 F7 F8 F9 F10 F11 F12 F13 F14
NSTATUS 25_VCC DGND 12_VCC DGND 12_VCC 25_VCC
G5 G6 G7 G8 G9 G10 G11 G12 G13 G14
DGND 12_VCC 12_VCC 12_VCC 12_VCC 12_VCC DGND DGND 33_VCCIO
H5 H6 H7 H8 H9 H10 H11 H12 H13 H14
FTDI NCONFIG 12_VCC DGND DGND DGND DGND 12_VCC NET00279 DGND CONF_DONE
J5 J6 J7 J8 J9 J10 J11 J12 J13 J14
FTDO FTMS 12_VCC DGND DGND DGND DGND DGND LEGO_MODE
K5 K6 K7 K8 K9 K10 K11 K12 K13 K14
DGND 12_VCC DGND 12_VCC DGND 33_VCCIO
L5 L6 L7 L8 L9 L10 L11 L12 L13 L14
25_VCC 25_VCC PCM_DSD_MODE
M5 M6 M7 M8 M9 M10 M11 M12 M13 M14
DGND DGND DGND DGND 33_VCCIO
N5 N6 N7 N8 N9 N10 N11 N12 N13 N14
12_VCC DGND DGND 12_VCC
P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
33_VCCIO DGND 33_VCCIO 33_VCCIO DGND 33_VCCIO
R5 R6 R7 R8 R9 R10 R11 R12 R13 R14
DAC_PCM_DATA_L
DAC_PCM_DATA_R DAC_DSD_DATA_L DGND
T5 T6 T7 T8 T9 T10 T11 T12 T13 T14
PCM_MCK/DSD_BCK DAC_PCM_BCK
DAC_WCK_OUT/DSD_R
B1
+3.3V_D
TO 1B
FROM
DGND
B2
POWER BLOCK +2V5_FPGA
TO 2B
TO 0B
+1V2_FPGA
FROM
CPU BLOCK
10
DNP-800NE FPGA
1 5 1 6
A15 A16
33_VCCIO
B15 B16
DGND
C15 C16
PCM_DATA/DSD_DATA_R_IN
D15 D16
PCM_BCK/DSD_DBCK_IN
PCM_LRCK/DSD_DATA_L_IN
E15 E16
A9
DGND DGND
T7 DAC_PCM_BCK PCM_BCK
R584 33-1608
F15 F16
R6 DAC_PCM_DATA_L PCM_DATA_L
R586 33-1608
R5
DAC_PCM_DATA_R PCM_DATA_R
R587 33-1608
R7
DAC_DSD_DATA_L DSDL
R588 33-1608
G15 G16
T6
DAC_WCK_OUT/DSD_R WCK/DSD_R
R589 33-1608
T5
PCM_MCK/DSD_BCK PCM_MCK/DBCK
R590 33-1608
H15 H16
DGND DGND
J15 J16
K15 K16
L15 L16
CONT4.
M15 M16
DGND DGND
N15 N16
P15 P16
R15 R16
DGND
T15 T16
33_VCCIO
BD500
CB05YTYH221-2012
33_VCCIO
25_VCC
BD501
CB05YTYH221-2012
BD502
CB05YTYH221-2012
12_VCC
TO
DAC BLOCK
TO 9A