Marantz SR5011 Service Manual page 61

SLAS764 – MAY 2011
DEVICE INFORMATION
TERMINAL FUNCTIONS, PCM510x
PCM5100 (HDMI U1052)
:
PCM510X (top view)
Table 2. TERMINAL FUNCTIONS, PCM510x
TERMINAL
I/O DESCRIPTION
NAME NO.
CPVDD 1 - Charge pump power supply, 3.3V
CAPP 2 O Charge pump flying capacitor terminal for positive rail
CPGND 3 - Charge pump ground
CAPM 4 O Charge pump flying capacitor terminal for negative rail
VNEG 5 O Negative charge pump rail terminal for decoupling, -3.3V
OUTL 6 O Analog output from DAC left channel
OUTR 7 O Analog output from DAC right channel
AVDD 8 - Analog power supply, 3.3V
AGND 9 - Analog ground
DEMP 10 I De-emphasis control for 44.1kHz sampling rate
FLT 11 I Filter select : Normal latency (Low) / Low latency (High)
SCK 12 I System clock input
BCK 13 I Audio data bit clock input
DIN 14 I Audio data input
PCM5100, PCM5101, PCM5102
LRCK 15 I Audio data word clock input
FMT 16 I Audio format selection : I
SLAS764 – MAY 2011
XSMT 17 I Soft mute control : Soft mute (Low) / soft un-mute (High)
Table 1. Differences Between PCM510x Devices
LDOO 18 - Internal logic supply rail terminal for decoupling
Part Number Dynamic Range
DGND 19 - Digital ground
PCM5102
PCM5101
DVDD 20 - Digital power supply, 3.3V
PCM5100
(1) Failsafe LVCMOS Schmitt trigger input spacer
PCM5100 Block Diagram
DIN (i2s)
Zero
Data
Detector
Clock Halt
Detection
LRCK
BCK
PLL Clock
6
MCK UVP/Reset
Figure 1. PCM510x Functional Block Diagram
(1)
: Off (Low) / On (High)
2
S (Low) / Left justified (High)
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SNR THD
112dB 112dB –93dB
106dB 106dB –92dB
100dB 100dB –90dB
Current LINE OUT
Segment
DAC
Current
Segment
DAC
Advanced Mute Control
PCM510x
CPVDD (3.3V)
AVDD (3.3V)
Power
Supply DVDD (3.3V)
Copyright © 2011, Texas Instruments Incorporated
POR Ch. Pump
GND
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 ゾーン用の 2ch ボリューム搭載
 2 線シリアルバスコントロールは、3.3/5V に対応
用途
BD34704KS2 (INPUT : IC4200)
 AV レシーバ、ホームシアタシステムに最適。
基本アプリケーション回路
PIN No. SYMBOL PIN No. SYMBOL
○製品構造：シリコンモノリシック集積回路 ○耐放射線設計はしておりません。
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1 DA
© 2015 ROHM Co., Ltd. All rights reserved.
2 TSZ22111・14・001 CL
3 VCC
4 DGND
5 VEE1
6 N.C.
7 VEE2
8 OUTFL
9 N.C.
10 OUTFR
11 N.C.
12 OUTSW
13 N.C.
14 OUTC
15 OUTSL
16 OUTSR
17 OUTSBL
18 OUTSBR
19 OUTPL
20 OUTPR
61
SQFP-T80C
Figure 1. 応用回路例
PIN No. SYMBOL
21 GND 61 SBLIN
1/32
22 GND 62 SRIN
23 GND 63 SLIN
24 GND 64 CIN
25 GND 65 SWIN
26 GND 66 FRIN
27 GND 67 FLIN
28 SUBR 68 FRIN3
29 SUBL 69 FLIN3
30 RECR 70 GND
31 RECL 71 ADCR
32 GND 72 ADCL
33 INR12(FRIN2) 73 GND
34 INL12(FLIN2) 74 GND
35 INR11(CIN2) 75 GND
36 INL11(SWIN2) 76 GND
37 INR10(SRIN2) 77 GND
38 INL10(SLIN2) 78 GND
39 GND 79 GND
40 N.C. 80 CHIP
PIN No. SYMBOL
41 INR9(SBRIN2)
Target Specification
2015.2.25 Rev.002
42 INL9(SBLIN2)
43 INR8
44 INL8
45 INR7
46 INL7
47 INR6
48 INL6
49 INR5
50 INL5
51 INR4
52 INL4
53 INR3
54 INL3
55 INR2
56 INL2
57 INR1
58 INL1
59 GND
60 SBRIN