Programmable Logic Device; Serial Line Switch - Vaisala MRG112 Technical Reference

Technical Reference ________________________________________________________________

Programmable Logic Device

Serial Line Switch

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rising edge is synchronized to the GPS time. The duration of the high
state of the pulse is from 1 to 2 milliseconds. The 1PPS signal is
connected via D1 and buffer D2 to the system connector X1.
The programmable logic device (PLD) D1 is used to control the reset
function, the LED lamps, and the serial channel connections in the
unit.
The PLD is factory programmed via programming interface consisting
of signals TDI, TDO, TCK, and TMS.
The inverter gate D3-A is connected as oscillator and it supplies a
150 kHz clock signal for D1.
The serial channel 1 from system connector (TXD1, RXD1) is
connected to the GPS module channel A (TXD1M, RXD1M) via
analog switch A2. The A2 consists of four separate switches, each
switch is controlled by PLD and a switch is closed if corresponding
control input G1, G2, G3 or G4 is at high level.
Switch 1 is used to connect the transmit signal TXD1M via buffer
amplifier A3-A to the serial line TXD1. Switch 2 and amplifier A3-B
are for possible future use.
Switch 3 is used to connect the TXD1 line signal to the line voltage
detector, which consists of transistors V1, V2, and diodes V3, V6. The
detector output at V1 collector is at high level if the line voltage is
below -3 V and the output is connected to the PLD for line switch
control.
Switch 4 is used to connect the receive signal RXD1 to the GPS
module.
After power-up or reset switches 1, 2, 4 are open and switch 3 is
closed to allow the line voltage detector to monitor the TXD1 line.
According to the detector output the PLD logic determines the line
status as "idle" or "externally driven" at 200 ms intervals. The status is
'externally driven' if the line voltage was below -3 V for more than 5%