Sharp TU-45GD1E Service Manual page 72

TU-45GD1E
LC-45GD1E
signal processing of the 4H-comb filter PLA/SECAM system.
8 bit Y/CbCr (ITU_R656) output.
• IC7203 (TVP5150A)
Performs copy control according to analog PAL and SECAM video signals.
• IC3700 (AD9981)
A/D converter with built-in PLL AMP
After controlling level of analog RGB input signal, A/D conversion is performed using the clock generated by PLL to
output signals at TTL level.
Video signal sent to this IC is digitally converted and sent to IC801 [F.P.G.A. (Field Programmable Gate Arrays)].
• IC802 (IXA835WJ)
F.P.G.A. (Field Programmable Gate Arrays) for synchronous processing and signal selector of each digitalized input
signal.
• IC3300 (IXB348WJ)
Performs data conversion for video signal processing, such as I/P conversion, γ correction, and scaling, to fit digitalized
video signal to output resolution. It also controls 2 screen display and OSD display.
Output digital signal is sent to IC3201 (LVDS TRANSMITTER).
• IC3401/3403 (IXB077WJ)
128 Mb (1 M x 32 bits x 4 Banks) Graphic Double Data Synchronous DRAM.
Used to save video signal temporarily for 3D-comb filter and block noise reducer of 3D-YC (IC402) as well as and
progressive format converter (image transformation) and noise reducer of CIV IC (IC3300).
• IC3201 (THC63LVD823)
170 MHz LVDS (Low Voltage Differential Signaling) 24 bit interface chip set for transmission. It is an LSI for serializing
and transmitting RGB signals, HD/VD/blanking signals and pixel clocks.
LVDS is a method for transmitting high-speed digital signals via cables driven by low-amplitude differential signals.
1LINK consists of five pairs of differential signals. The TA, TB, TC, and TD pairs are used for data transmissions, and
the TCLK pair is used for pixel clock transmissions. Seven data bits of TA, TB, TC and TD each (28 in total) are
transmitted per pixel clock.
RGB (24 bit) signal and sync signal (HD, VD and DE) are allocated to these 28 data.
• IC2802 (THC53LVD824)
170 MHz LVDS (Low Voltage Differential Signaling) 24 bit interface chip set for reception from IC3201. LVDS signals
transmitted from IC3201 are sent to HDCP Panellink transmitter IC of IC3103.
• IC3103 (SiI170GB)
HDCP compatible DVI transmitter. It serializes parallel RGB (digital) video signals and transfer to the display side as
TMDS signals at high speed.
• IC7253 (DS90C386)
Together with DS90C385 on PC-CARD circuit, DS90C386 handles 4 pairs of LVDS data streams.
• IC7254 (DS90C385)
Programmable LVDS (Low Voltage Differential Signaling) transmitter for communications to PC-CARD circuit. It
converts 28 bit LVCMOS/LVTTL input parallel data to 4 pairs of LVDS serial data. It also converts the clock signal to
a pair of LVDS data after phase adjustment at transmitter PLL circuit. 28 bit input data is sampled for each clock signal
cycle and transmitted. Clock frequency is 27 MHz and digital video data are sent and received. This IC handles, in the
order of YCbYCr (time division), 8 bit data and 10 types of data for H and V (for retrieving CIVIC DATA).
• IC2501 (MSP3450G)
IC for decoding sound data.
Decodes S-IF and simultaneously acts as a selector of inputted sound data.
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