Table of Contents
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Pin
Port
No.
84 EMU/
OFF
85 TDO
86 TDI
87 /TRST
88 TCK
89 TMS
90 CVSS8 GND
91 CVDD5 CORE CPU system (1.6V)
power supply
92 HPIENA GND
93 DVSS6 GND
94
-
95 CLKENA Oscillation output Cainabl
signal
96 X1
Crystal Connection
97 X2/
Crystal Connection
CLKIN
98 RS
Reset signal input
99 D0
Data base of FLASH ROM
100 D1
101 D2
102 D3
103 D4
104 D5
105 A16
Address bus of FLASH ROM
106 DVSS7 GND
107 A17
Address bus of FLASH ROM
108 A18
109 A19
Address bus of FLASH ROM
110 A20
111 CVSS9 GND
112 DVDD5 I/O system (3.3V) power
supply
113 D6
Data bus of FLASH ROM
114 D7
115 D8
116 D9
117 D10
118 D11
Data bus of FLASH ROM
119 D12
120 STAT
Status signal input
121 D13
Data path of FLASH ROM
122 D14
123 D15
124
-
Descriptions
-
-
-
-
-
-
-
-
I/O
(V)
-
3.3
-
3.3
-
0
-
3.3
-
0
-
3.3
-
3.3
-
0
I
1.6
-
0
-
-
O
3.3
O
0
I
0
I
1
I/O
3.4
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
O
0
-
0
O
3.3
O
0
O
0
O
0
-
0
-
3.3
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I/O
0
I
0.4
I/O
0
I/O
0
I/O
0
-
-
12
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