Table of Contents
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51
-
Pin
Port
No.
52 CVDD3 CORE CPU system (1.6V)
power supply
53 LRCK
AUDIO L/R identifying
M C
signal output
54 CDFS
Serial frame sink signal
input
55
-
56 DVDD3 I/O system (3.3V) power
supply
57 DVSS3 GND
58 REST
Mechanics deck REST SW
SW
input
59 DATA
AUDIO serial data output
M C
60 SO
Serial data output
61
-
62
-
63 /NMI
64 /INT0
65 /INT1
66 BLKCK Subcode block clock pulse
input
67 /INT3
68 CV
CORE CPU system (1.6V)
DD4
power supply
69 SW1
Mechanics deck SW1 input
70 CVSS7 GND
71 MCLK
Clock output (To Servo
DSP)
72 DVSS4 GND
73 MLD
Command load signal
output (To Servo DSP)
74 MDATA Command data output (To
Servo DSP)
75 DVDD4 I/O system (3.3V) power
supply
76 DVSS5 GND
77
CLK
Clock mode setting (L
MD1
fixation)
78
CLK
Clock mode setting (H
MD2
fixation)
79
CLK
Clock mode setting (L
MD3
fixation)
80
-
81 SW2
Mechanics deck SW2 input
82
-
83 EMU0
-
Descriptions
-
-
-
-
-
-
-
-
-
-
-
-
I/O
(V)
-
1.6
O
1.6
I
2.4
-
-
-
3.3
-
0
I
3.3
O
1.6
O
1.2
-
-
-
-
-
3.3
-
3.3
-
3.3
I
0
-
3.3
-
1.6
I
0
-
0
O
3.3
-
0
I
3.3
O
3.3
-
3.3
-
0
I
0
I
3.3
I
-
-
-
I
0
-
-
-
0
11
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