Yamaha P-250 Service Manual page 17

HD6417709SHF200B (X2687A00) CPU (SH3)
PIN
NAME I/O
NO.
I
1 MD1
Mode control
2 MD2 I
3 Vcc(RTC) - Power supply +1.8 V
4 XTAL2 O
Crystal oscillator
5 EXTAL2 I
6 Vss(RTC) - Ground
7 NMI I Non-maskable interrupt request
8 IRQ0/IRL0/PTH0 I
9 IRQ1/IRL1/PTH1 I
10 IRQ2/IRL2/PTH2 I Interrupt request / Port H
11 IRQ3/IRL3/PTH3 I
12 IRQ4/PTH4 I
13 D31/PTB7 I/O
14 D30/PTB6 I/O
15 D29/PTB5 I/O
Data bus / Port B
16 D28/PTB4 I/O
17 D27/PTB3 I/O
18 D26/PTB2 I/O
19 VssQ - Ground
20 D25/PTB1 I/O Data bus / Port B
21 VccQ - Power supply +3.3 V
22 D24/PTB0 I/O Data bus / Port B
23 D23/PTA7 I/O
I/O
24 D22/PTA6
Data bus / Port A
25 D21/PTA5 I/O
26 D20/PTA4 I/O
27 Vss - Ground
28 D19/PTA3 I/O Data bus / Port A
29 Vcc - Power supply +1.8 V
30 D18/PTA2 I/O
31 D17/PTA1 I/O Data bus / Port A
32 D16/PTA0 I/O
33 VssQ - Ground
34 D15 I/O Data bus
35 VccQ - Power supply +3.3 V
36 D14 I/O
37 D13 I/O
38 D12 I/O
39 D11 I/O
40 D10 I/O Data bus
41 D9 I/O
42 D8 I/O
43 D7 I/O
44 D6 I/O
45 VssQ - Ground
46 D5 I/O Data bus
- Power supply +3.3 V
47 VccQ
48 D4 I/O
49 D3 I/O
50 D2 I/O Data bus
51 D1 I/O
52 D0 I/O
53 A0 O
54 A1 O
Address bus
55 A2 O
56 A3 O
57 VssQ - Ground
58 A4 O Address bus
59 VccQ - Power supply +3.3 V
60 A5 O
61 A6 O
62 A7 O
63 A8 O
64 A9 O Address bus
65 A10 O
66 A11 O
67 A12 O
68 A13 O
69 VssQ - Ground
O Address bus
70 A14
VccQ - Power supply +3.3 V
71
72 A15 O
73 A16 O
74 A17 O
75 A18 O Address bus
76 A19 O
77 A20 O
78 A21 O
79 Vss - Ground
80 A22 O Address bus
81 Vcc - Power supply +1.8 V
82 A23 O Address bus
83 VssQ - Ground
84 A24 O Address bus
85 VccQ - Power supply +3.3 V
86 A25 O Address bus
87 BS/PTK4 I/O Bus cycle / Port K
88 RD O Read strobe
89 WE0/DQMLL O Select signal (D7-D0) / D QM (SDRAM)
90 WE1/DQMLU/WE O Select signal (D15-D8) / D QM (SDRAM) / Write enable
91 I/O Select signal (D23-D16) / D QM (SDRAM) / I/O read / Port K
WE2/DQMUL/ICIORD/PTK6
92 I/O Select signal (D31-D24) / D QM (SDRAM) / I/O write / Port K
WE3/DQMUU/ISIOWR/PTK7
O
93 RD/WR Read / Write
AUDSYNC/PTE7 I/O AUD cycle / Port E
94
95 VssQ - Ground
96 CS0/MCS0 O Chip select / Mask ROM chip select
97 VccQ - Power supply +3.3V
98 CS2/PTK0 I/O
99 CS3/PTK1 I/O Chip select / Port K
100 CS4/PTK2 I/O
101 CS5/CE1A/PTK3 I/O Chip select / Chip enable / Port K
102 CS6/CE1B O Chip select / Chip enable
103 CE2A/PTE4 I/O
Chip enable / Port E
104 CE2B/PTE5 I/O
PIN
FUNCTION
NO.
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
NAME I/O
I/O CK enable / Port K
CKE/PTK5
RAS3L/PTJ0 I/O RAS address bus / Port J
PTJ1 I/O Port J
CASL/PTJ2 I/O CAS address bus / Port J
VssQ - Ground
CASU/PTJ3 I/O CAS address bus / Port J
VccQ - Power supply +3.3 V
PTJ4 I/O
Port J
PTJ5 I/O
DACK0/PTD5 I/O
DMA acknowledge / Port D
DACK1/PTD7 I/O
PTE6 I/O
Port E
PTE3 I/O
RAS3U/PTE2 I/O RAS address bus / Port E
PTE1 I/O Port E
TDO/PTE0 I/O Test data / Port E
BACK O Bus acknowledge
BREQ I Bus request
WAIT I Hardware wait request
RESETM I Manual reset
ADTRG/PTH5 I Analog trigger / Port H
IOIS16/PTG7 I Write protect / Port G
ASEMD0/PTG6 I ASE mode / Port G
I/O ASE break acknowledge / Port G
ASEBRKAK/PTG5
PTG4/CKIO2 I/O Port G / Clock output
AUDATA3/PTG3 I/O
AUD data / Port G
AUDATA2/PTG2 I/O
Vss - Ground
AUDATA1/PTG1 I/O AUD data / Port G
Vcc - Power supply +1.8 V
AUDATA0/PTG0 I/O AUD data / Port G
TRST/PTF7/PINT15 I Test reset / Port F / Port interruption
TMS/PTF6/PINT14 I Test mode switch / Port F / Port interruption
TDI/PTF5/PINT13 I Test data / Port F / Port interruption
TCK/PTF4/PINT12 I Test clock / Port F / Port interruption
IRLS3/PTF3/PINT11 I
IRL2/PTF2/PINT10 I
Interrupt request / Port F / Port interruption
IRLS1/PTF1/PINT9 I
IRLS0/PTF0/PINT8 I
MD0 I Mode control
Vcc(PLL1) - Power supply +1.8 V
CAP1 - Capacitor
Vss(PLL1) - Ground
Vss(PLL2) - Ground
CAP2 - Capacitor
VCC(PLL2) - Power supply +1.8 V
I AUD clock / Port H
AUDCK/PTH6
Vss -
Ground
Vss -
Vcc - Power supply +1.8 V
XTAL1 O
Crystal oscillator
EXTAL1 I
STATUS0/PTJ6 I/O
Processor status / Port J
STATUS1/PTJ7 I/O
TCLK/PTH7 I/O Timer clock / Port H
/IRQOUT O Interrupt request output
VssQ - Ground
CKIO I/O System clock input / output
VccQ - Power supply +3.3 V
TXD0/SCPT0 O Data transmission / SCI port
SCK0/SCPT1 I/O Serial clock / SCI port
TXD1/SCPT2 O Data transmission / SCI port
SCK1/SCPT3 I/O Serial clock / SCI port
TXD2/SCPT4 O Data transmission / SCI port
SCK2/SCPT5 I/O Serial clock / SCI port
RTS2/SCPT6 I/O Transmit request / SCI port
RXD0/SCPT0 I
Data reception / SCI port
RXD1/SCPT2 I
Vss - Ground
I Data reception / SCI port
RXD2/SCPT4
Vcc - Power supply +1.8 V
CTS2/IRQ5/SCPT7 I Transmit clear / Interrupt request / SCI port
MCS7/PTC7/PINT7 I/O
MCS6/PTC6/PINT6 I/O
Mask ROM chip select / Port C / Port interruption
MCS5/PTC5/PINT5 I/O
MCS4/PTC4/PINT4 I/O
VssQ - Ground
WAKEUP/PTD3 I/O Standby mode Interrupt request output / Port D
VccQ - Power supply +3.3 V
RESETOUT/PTD2 I/O Reset output / Port D
MCS3/PTC3/PINT3 I/O
MCS2/PTC2/PINT2 I/O
Mask ROM chip select / Port C / Port interruption
MCS1/PTC1/PINT1 I/O
MCS0/PTC0/PINT0 I/O
DRAK0/PTD1 I/O
DMA acknowledge / Port D
DRAK1/PTD0 I/O
DREQ0/PTD4 I
DMA request / Port D
DREQ1/PTD6 I
RESETP I Power on reset
CA I Chip active
MD3 I
MD4 I Mode control
I
MD5
AVss - Analog ground
AN0/PTL0 I
AN1/PTL1 I
AN2/PTL2 I
Analog input / Port L
AN3/PTL3 I
AN4/PTL4 I
AN5/PTL5 I
AVcc - Analog power supply +3.3 V
AN6/DA1/PTL6 I/O
Analog input / Analog output / Port L
AN7/DA0/PTL7 I/O
AVss - Analog ground
P-250
DM: IC014
FUNCTION
17