Philips 5008 Series Service Manual page 45

Chassis q552.5he la
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Pinning information
Ball
Symbol
W4
SDIO_DAT1
W5
SDIO_DAT0
W6
SDIO_CMD
W7
VDD_1V15
W20
VDD_3V3
W21
GPIO_4
W22
GPIO_5
W23
GPIO_6/USB_FAULT
W24
RREF
W25
RXCP_A
W26
RXCN_A
Y1
ETH_MDIO
Y2
ETH_CRS
Y3
ETH_MDC
Y4
ETH_RXER
Y5
ETH_RXD0
Y6
ETH_RXD1
Y7
VDD_1V15
Y8
VDD_3V3
Y9
VSSA
Y10
VDDA_2V5_VDAC
Y11
VSSA
Y12
VDDA_2V5_4
Y13
VDDA_2V5_VADC
Y14
VSSA
Y15
VDDA_1V15
Y16
VSSA
Y17
VDDA_2V5_DCS
Y18
VDD_3V3_SBY
Y19
VDD_3V3_SBY
Y20
VSS
GPIO_0
Y21
Y22
GPIO_1
Y23
GPIO_2
Y24
GPIO_3
Y25
DDC_SDA_A
Y26
DDC_SCL_A
AA1
ETH_TXD0
AA2
ETH_TXCLK
IC Data Sheets
PNX58XXX [11/16]
Pad
Pad type
direc-
tion
I/O
CMOS 3.3 V
I/O
CMOS 3.3 V
I/O
CMOS 3.3 V
PWR supply
PWR supply
I/O
CMOS 3.3 V
I/O
CMOS 3.3 V
I/O
CMOS 3.3 V
I/O
HDMI
I
HDMI
I
HDMI
I/O
CMOS 3.3 V
I
CMOS 3.3 V, PD
O
CMOS 3.3 V
I
CMOS 3.3 V, PD
I
CMOS 3.3 V, PD
I
CMOS 3.3 V, PD
PWR supply
PWR supply
PWR analog ground
PWR supply
PWR analog ground
PWR supply
PWR supply
PWR analog ground
PWR supply
PWR analog ground
PWR supply
PWR supply
PWR supply
PWR ground
I/O
CMOS 3.3 V
I/O
CMOS 3.3 V
I/O
CMOS 3.3 V
I/O
CMOS 3.3 V
I/O
I2C 3 V, 5 VT, OD
I/O
I2C 3 V, 5 VT, OD
O
CMOS 3.3 V
I
CMOS 3.3 V, PD
Figure 8-13 Pin configuration
back to
div. table
Q552.5HE LA
Description
SDIO Data Bit 1
SDIO Data Bit 0
SDIO Command Line
General Purpose I/O bit 4
General Purpose I/O bit 5
General Purpose I/O bit 6
Current Reference for HDMI
HDMI A Receiver Clock Channel Positive
HDMI A Receiver Clock Channel Negative
Ethernet MIIM data input/output
Ethernet MII carrier sense and receive data valid
input (async)
Ethernet MIIM clock to PHY
Ethernet MII receive error
Ethernet receive data bit 0
Ethernet receive data bit 1
Video DAC 2.5 V Analog Supply
2.5 V analog supply
Video ADC 2.5 V Analog Supply
1.15 V analog supply
DCS 2.5 V Analog supply
System controller 3.3 V supply
System controller 3.3 V supply
General Purpose I/O bit 0
General Purpose I/O bit 1
General Purpose I/O bit 2
General Purpose I/O bit 3
2
HDMI A I
C DA - EDID
2
HDMI A I
C Clock - EDID
Ethernet transmit data bit 0
Ethernet MII transmit clock input from PHY
8.
EN 45
19490_312_130413.eps
130413
2013-Sep-20

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