Philips 5008 Series Service Manual page 42

EN 42 8. Q552.5HE LA
Pinning information
Ball Symbol
N1 M0_DQ20
N2 VSS
N3 M0_DQ28
N4 M0_CLK_P
N5 M0_CLK_N
N6 VDD_2V5
N7 VDD_2V5
N9 VDD_1V15
N11 VDD_1V15
N13 VDD_1V15
N15 VDD_1V15
N17 VDD_1V15
N20 VSS
N21 CA_MDI6
N22 CA_MDI7
N23 CA_MCLKI
N24 CA_MISTRT
N25 CA_MIVAL
N26 CA_MDO0
P1 M0_DQ22
P2 M0_DQ17
P3 M0_DQ19
P4 VSS
P5 M0_DQ27
P6 VSS
P7 VSS
P10 VSS
P12 VSS
P14 VSS
P16 VSS
P18 VSS
P20 VDD_3V3
P21 CA_MDI0
P22 CA_MDI1
P23 CA_MDI2
P24 CA_MDI3
P25 CA_MDI4
P26 CA_MDI5
R1 M0_DQS2_N
2013-Sep-20
IC Data Sheets
PNX58XXX [8/16]
Pad Pad type
direc-
tion
I/O DDR2 data
PWR ground
I/O DDR2 data
O DDR2 clk
O DDR2 clk
PWR supply
PWR supply
PWR supply
PWR supply
PWR supply
PWR supply
PWR supply
PWR ground
O CMOS 3.3 V, PD
O CMOS 3.3 V, PD
O CMOS 3.3 V, PD
O CMOS 3.3 V, PD
O CMOS 3.3 V , PD
I CMOS 3.3 V, 5 VT, PD
I/O DDR2 data
I/O DDR2 data
I/O DDR2 data
PWR ground
I/O DDR2 data
PWR ground
PWR ground
PWR ground
PWR ground
PWR ground
PWR ground
PWR ground
PWR supply
O CMOS 3.3 V, PD
O CMOS 3.3 V, PD
O CMOS 3.3 V, PD
O CMOS 3.3 V, PD
O CMOS 3.3 V, PD
O CMOS 3.3 V, PD
I/O DDR2 strobe
Figure 8-10 Pin configuration
back to
div. table
Description
Memory Data bit 20
Memory Data bit 28
Memory Clock Positive
Memory Clock Negative
DDR 2.5 V DLL Supply
DDR 2.5 V DLL Supply
CA Transport Stream Output bit 6
CA Transport Stream Output bit 7
CA Transport Stream Output Clock
CA Transport Stream Output Packet Start
CA Transport Stream Output Packet Valid
CA Transport Stream Input bit 0
Memory Data bit 22
Memory Data bit 17
Memory Data bit 19
Memory Data bit 27
CA Transport Stream Output bit 0
CA Transport Stream Output bit 1
CA Transport Stream Output bit 2
CA Transport Stream Output bit 3
CA Transport Stream Output bit 4
CA Transport Stream Output bit 5
Memory DQ Strobe bit 2 Negative
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