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Pinning information
Ball
Symbol
A
1
V
S
S
A2
M0_VREF_1
A
3
V
S
S
A4
M0_DQ12
A5
VDD_1V8
A6
VDD_1V8
A7
LOUT1_AN
A
8
V
S
S
A9
LOUT1_CN
A
1
0
V
S
S
A11
LOUT1_DN
A
1
2
V
S
S
A13
VSSA_1V15_LVDS_PLL
A14
LOUT2_AN
A
1
5
V
S
S
A16
LOUT2_CN
A
1
7
V
S
S
A18
LOUT2_DN
A
1
9
V
S
S
A
2
0
R
_
B
N
1
A
2
1
W
P
N
0
A22
CA_D6
A23
SCL4
A
2
4
S
C
L
3
A
2
5
S
C
L
2
A
2
6
V
S
S
B
1
V
S
S
B2
M0_DQ9
B3
M0_DQ14
B4
M0_DQ4
B5
VDD_1V8
B6
VDD_1V8
B7
LOUT1_AP
B8
LOUT1_BP
B9
LOUT1_CP
B10
LOUT1_CLKP
B11
LOUT1_DP
B12
LOUT1_EP
IC Data Sheets
PNX58XXX [1/16]
Pad
Pad type
direc-
tion
P
W
R
g
o r
u
n
d
I
analog
P
W
R
g
o r
u
n
d
I/O
DDR2 data
PWR supply
PWR supply
O
LVDS
P
W
R
g
o r
u
n
d
O
LVDS
P
W
R
g
o r
u
n
d
O
LVDS
P
W
R
g
o r
u
n
d
PWR LVDS
O
LVDS
P
W
R
g
o r
u
n
d
O
LVDS
P
W
R
g
o r
u
n
d
O
LVDS
P
W
R
g
o r
u
n
d
I
C
M
O
S
3
3 .
, V
P
D
/ I
O
C
M
O
S
3
3 .
V
I/O
CMOS 3.3 V
I/O
I2C 3 V, 5 VT, OD
/ I
O
2 I
C
3
, V
5
V
, T
O
D
/ I
O
2 I
C
3
, V
5
V
, T
O
D
P
W
R
g
o r
u
n
d
P
W
R
g
o r
u
n
d
I/O
DDR2 data
I/O
DDR2 data
I/O
DDR2 data
PWR supply
PWR supply
O
LVDS
O
LVDS
O
LVDS
O
LVDS
O
LVDS
O
LVDS
Figure 8-3 Pin configuration
back to
div. table
Q552.5HE LA
Description
Memory Voltage Reference Input 1
Memory Data bit 12
LVDS1 Channel A Negative
LVDS1 Channel C Negative
LVDS1 Channel D Negative
Ground Supply for PLL
LVDS2 Channel A Negative
LVDS2 Channel C Negative
LVDS2 Channel D Negative
M
e
m
o
y r
R
e
a
d
y
1
N
a
n
d
F
a l
s
h
W
i r
e t
P
o r
e t
t c
o i
n
CA Data Bus Bit-6 (I/O)
2
I
C-4 Serial Clock Master/Slave DMA
2
I
C-3 Serial Clock Master/Slave DMA
2
I
C-2 Serial Clock Master/Slave DMA
Memory Data bit 9
Memory Data bit 14
Memory Data bit 4
LVDS1 Channel A Positive
LVDS1 Channel B Positive
LVDS1 Channel C Positive
LVDS1 Clock Positive
LVDS1 Channel D Positive
LVDS1 Channel E Positive
8.
EN 35
19490_302_130413.eps
130413
2013-Sep-20
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