Table of Contents
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Calculate MaxRdLatency per channel
TpProcMemReceiveDqsTraining
Set Write Data delay
Write test pattern
Start read sweep
Set Receive DQS delay
Read Test pattern
Compare Test pattern
Update results
Start Find passing window
TpProcMemTransmitDqsTraining
Start write sweep
Set Transmit DQ delay
Write test pattern
Read Test pattern
Compare Test pattern
Update results
Start Find passing window
TpProcMemMaxRdLatencyTraining
Start sweep
Set delay
Write test pattern
Read Test pattern
Compare Test pattern
Online Spare init
Bank Interleave Init
Node Interleave Init
Channel Interleave Init
ECC initialization
Platform Specific Init
Before callout for "AgesaReadSpd"
After callout for "AgesaReadSpd"
Before optional callout "AgesaHookBeforeDramInit"
After optional callout "AgesaHookBeforeDramInit"
Before optional callout "AgesaHookBeforeDQSTraining"
After optional callout "AgesaHookBeforeDQSTraining"
Before optional callout "AgesaHookBeforeDramInit"
After optional callout "AgesaHookBeforeDramInit"
After MemDataInit
Before InitializeMCT
Before LV DDR3
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BIOS Setup
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