Renesas RH850/F1K Series Application Note
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Renesas RH850/F1K Series Application Note

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RH850/F1K Series
Hardware Design Guide
Introduction
This application note is intended to provide RH850/F1K series specific information and recommendations on the device
usage. It should be used in conjunction with the corresponding RH850/F1K series user manual (includes the electrical
characteristics).
Target Device
RH850/F1K Group
RH850/F1K ECO Line
176 pin
144 pin
RH850/F1K ADVANCED line
176 pin
144 pin
100 pin
RH850/F1K PREMIUM Line
176 pin
144 pin
100 pin
R01AN2911EJ0100 Rev. 1.00
Aug 04, 2016
APPLICATION NOTE
R01AN2911EJ0100
Rev. 1.00
Aug 04, 2016
Page 1 of 46

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Summary of Contents for Renesas RH850/F1K Series

  • Page 1 Aug 04, 2016 Introduction This application note is intended to provide RH850/F1K series specific information and recommendations on the device usage. It should be used in conjunction with the corresponding RH850/F1K series user manual (includes the electrical characteristics). Target Device...

  • Page 2: Table Of Contents

    RH850/F1K Series Hardware Design Guide Table of Contents Power Supply........................6 Power Supply Overview of RH850/F1K Group ................. 6 1.1.1 Power Supply Pin Overview of RH850/F1K Group ..............6 1.1.2 Power Supply Pin Configuration of RH850/F1K Group ............6 1.1.3 Power Supply Pin Architecture of RH850/F1K Group ............
  • Page 3 RH850/F1K Series Hardware Design Guide 6.1.3 Combined Debug and Flash Programming Interface Connection of RH850/F1K Group ..39 6.1.4 Debug and Flash Programming Interface Connection of RH850/F1K Group when the internal HSOSC is used as Clock Supply ................40 6.1.5 Debug Considerations when Hot Plug-in is used ..............
  • Page 4 RH850/F1K Series Hardware Design Guide Table of Figures Figure 1 RH850/F1K Power supply architecture ....................7 Figure 2 RH850/F1K Power up/down timing ....................10 Figure 3 Principle capacitor placement at REGVCC for EMI at data flash operation ........11 Figure 4 Minimum external components for RH850/F1K (176pin) for normal operation mode ...... 12 Figure 5 Recommended main oscillator circuit ....................
  • Page 5 RH850/F1K Series Hardware Design Guide Table of Tables Table 1 Power supply pin overview ........................6 Table 2 Power supply architecture RH850/F1K with single supply 5V ............. 7 Table 3 Power supply architecture RH850/F1K with single supply 3.3V ............7 Table 4 Power supply architecture RH850/F1K with mixed supply 5V &...

  • Page 6: Power Supply

    RH850/F1K Series Hardware Design Guide Power Supply Power Supply Overview of RH850/F1K Group 1.1.1 Power Supply Pin Overview of RH850/F1K Group The devices of the RH850/F1K group have the following power supply pins. Table 1 Power supply pin overview Device...

  • Page 7: Figure 1 Rh850/F1K Power Supply Architecture

    RH850/F1K Series Hardware Design Guide RH850/F1K Group REGVCC AWO-Area ISO-Area A0VREF A1VREF EVCC EVCC EVCC Figure 1 RH850/F1K Power supply architecture Table 2 Power supply architecture RH850/F1K with single supply 5V Case 1 – Single Supply 5V Condition REGVCC = 5V...

  • Page 8: Table 4 Power Supply Architecture Rh850/F1K With Mixed Supply 5V & 3.3V

    RH850/F1K Series Hardware Design Guide Table 4 Power supply architecture RH850/F1K with mixed supply 5V & 3.3V Case 3 – Mixed Supply 5V & 3.3V Condition REGVCC = 5V EVCC = 3.3V A0VREF = 5V A1VREF = 5V – Port usable with analog or digital function Port Function –...

  • Page 9: Table 6 Power Supply Architecture Rh850/F1K With Mixed Supply 5V & 3.3V

    RH850/F1K Series Hardware Design Guide Table 6 Power supply architecture RH850/F1K with mixed supply 5V & 3.3V Case 5 – Mixed Supply 5V & 3.3V Condition REGVCC = 3.3V EVCC = 3.3V A0VREF = 5V A1VREF = 5V – Port usable with analog or digital function Port Function –...

  • Page 10: Power Supply Timing Of Rh850/F1K Group

    RH850/F1K Series Hardware Design Guide 1.1.4 Power Supply Timing of RH850/F1K Group The RH850/F1K group has a recommended power supply timing. The voltage slope of the different power supply pins is defined with min. 0.02V/ms and max. 500V/ms. For details on the electrical characteristics, please refer to the corresponding device RH850/F1K hardware user’s manual.

  • Page 11: Principle Capacitor Placement At Regvcc Of Rh850/F1K Group

    RH850/F1K Series Hardware Design Guide Principle Capacitor Placement at REGVCC of RH850/F1K Group When the data flash of the RH850/F1K group will be used in the application it should be considered to add an additional capacitor to the REGVCC pin and to use a close component placement to the supply pin in order to optimize the EMI noise behavior during the program and erase operation of the data flash.

  • Page 12: Minimum External Components

    Hardware Design Guide Minimum External Components The RH850/F1K series requires a certain number of external connections and components for a proper operation in normal operation mode. The components are shown in different categories depending on the device operation and the use case.

  • Page 13: Table 8 Minimum External Components For Rh850/F1K (176Pin)

    RH850/F1K Series Hardware Design Guide Table 8 Minimum external components for RH850/F1K (176pin) Component Value Category Min. Typ. Max. 16MHz 24MHz Typical 32.768kHz Typical 100kΩ Note 1 Typical 1kΩ 4.7kΩ Note 3 Note 3 Note 3 6.6kΩ Required 100kΩ 105kΩ...
  • Page 14 RH850/F1K Series Hardware Design Guide • Recommended component Component that is not required by the device specification, but is provided in order to secure the device operating conditions. The component value depends on the application requirements and must be evaluated with best engineering practice.

  • Page 15: Oscillator

    RH850/F1K Series Hardware Design Guide Oscillator Recommended Oscillator Circuit 3.1.1 Main Oscillator A crystal or ceramic resonator can be connected to the main clock input pins as shown below. internal internal external external MOSC MOSC Figure 5 Recommended main oscillator circuit...

  • Page 16: Sub Oscillator

    RH850/F1K Series Hardware Design Guide 3.1.2 Sub Oscillator A crystal resonator can be connected to the sub clock input pins as shown below. IP0_0 internal external SOSC Figure 6 Recommended sub oscillator circuit General guidance values of the sub oscillator circuit:...

  • Page 17: Device Pins

    Minimum RESET Circuit The RH850/F1K series has an on-chip Power-on Clear (POC) circuit. Therefore, a specific external RESET circuit is not required and the minimum requirement of the RESET circuit is a resistor to EVCC for start-up of the device. The resistor should be dimensioned large enough to allow a RESET signal generated by development tool or flash programmer to control the RESET pin.

  • Page 18: Reset Input Characteristics

    RH850/F1K Series Hardware Design Guide 4.1.2 RESET Input Characteristics The RESET is passed through an internal analog noise filter to prevent erroneous resets due to spikes. The following figure shows the timing when an external reset is performed. It explains the effect of the noise elimination.

  • Page 19: General Purpose I/O

    RH850/F1K Series Hardware Design Guide General Purpose I/O 4.2.1 RESET State of General Purpose I/O During RESET state, all general-purpose I/O pins are in input mode with high-Z behavior except the pin P8_6/_RESETOUT. 4.2.2 JP0_4/_DCUTRST During power-on, RESET the pin JP0_4 should not be driven externally to high-level. Therefore, JP0_4/_DCUTRST has to be connected in all device operation modes to EVSS via a resistor.

  • Page 20: Figure 9 Resetout Pin Behavior At Opbt0[9] = 1

    RH850/F1K Series Hardware Design Guide Data transfer of P8_6 changed to output option byte low level by any RESET P8_6 set to 1 (OPBT0[9]) EVCC/REGVCC RESET Flash operation Flash sequence Flash sequence P8_6 RESETOUT RESETOUT RESETOUT RESETOUT enable enable Execution of...

  • Page 21: Analog Filter Function

    RH850/F1K Series Hardware Design Guide 4.2.4 Analog Filter Function Depending on the alternative port functionality selected, some input signals of the device pins are passed through an analog filter - respectively analog delay stage - to remove noise and glitches from the input signal.

  • Page 22: Behavior During Low Power Mode

    Behavior during Low Power Mode During the low power modes, different states apply for the ports and pins of the RH850/F1K series. The states depend on the chosen low-power mode and may not have the same behavior for ports and pins.

  • Page 23: Recommended Connection Of Unused Pins

    RH850/F1K Series Hardware Design Guide Recommended Connection of unused Pins 4.3.1 Recommended Connection of unused Pins for RH850/F1K Group Table 13 Recommended Connection of unused Pins for RH850/F1K Group Recommended Connection of Unused Pin A0VREF, A1VREF Connect to EVCC A0VSS, A1VSS...
  • Page 24 RH850/F1K Series Hardware Design Guide Recommended Connection of Unused Pin Input state - Leave open (PIBCn_m = 0) - Connect to A0VREF or A0VSS via resistor (PIBCn_m = 1) Output state - Leave open Input state - Leave open (PIBCn_m = 0)

  • Page 25: Pin Assignment Differences

    RH850/F1K Series Hardware Design Guide Pin Assignment Differences The pin assignment of the RH850/F1K (176pin), RH850/F1L (176pin) and the RH850/F1M (176pin) shows some hardware related differences as described in the table below. Table 14 Basic pin assignment differences RH850/F1K-2 (176pin)

  • Page 26: Injected Current

    Hardware Design Guide Injected Current The RH850/F1K series has different electrical characteristics for the injected current depending on the pin group and device pins of the different package variants. For details, please refer to the electrical characteristics of the related RH850/F1K hardware user’s manual.

  • Page 27: A/D-Converter

    RH850/F1K Series Hardware Design Guide A/D-Converter Conversion Time The ADC conversion time consists of a number of timing parameters, which are summed-up to get the conversion timing depending on the application. Total conversion time (single channel) SG setup MPX setup...

  • Page 28: Equivalent Input Circuit

    RH850/F1K Series Hardware Design Guide Equivalent Input Circuit The A/D-converters have different options for the input with track & hold path or direct path only. Please refer to the user’s manual, which A/D-converter is supported by the chosen device. ADCAnIm or ADCAnImS...

  • Page 29: External Circuit On Adc Input

    RH850/F1K Series Hardware Design Guide External Circuit on ADC Input To preserve the accuracy of the A/D-converter, it is recommended that analog input pins have a low impedance. Therefore placing a capacitor at the analog input pin can provide an effective result. This capacitor contributes to noise filtering on the analog input pin.
  • Page 30 RH850/F1K Series Hardware Design Guide As guide line for the calculation of the external capacitor at the analog input pin the formula based on the internal equivalent capacitance and the ADC resolution of the corresponding AD-converter channel can be used: ���������...

  • Page 31: Development And Test Tool Interface

    RH850/F1K Series Hardware Design Guide Development and Test Tool Interface The RH850/F1x series supports the following operation modes that are used for debugging, flash programming and test by using boundary scan. Table 19 Operation mode overview FLMD0 P10_8 (FLMD1) P10_1 (MODE0)

  • Page 32: Development Tool Interface Of Rh850/F1K Group

    RH850/F1K Series Hardware Design Guide Development Tool Interface of RH850/F1K Group The description of the development tool interface in this chapter assumes that the normal operating mode of the MCU is used. When the user boot mode shall be used the configuration of the pins FLMD0, P10_8/FLMD1, P10_1/MODE0, P10_2/MODE1 and P10_6/MODE2 has to be set accordingly.

  • Page 33: Figure 16 Rh850/F1K 4Pin Low-Pin Debug Interface Connection

    RH850/F1K Series Hardware Design Guide  JP0_4: General-purpose I/O  JP0_5: General-purpose I/O  JP0_6: General-purpose I/O E1 Emulator RH850/F1K Group (14pin Connector) EVCC TVDD EVSS 1k to 4.7kΩ Note 1 TDI/LPDIO JP0_0 (DCUTDI/LPDIO, LPDI) TDO/LPDO JP0_1 (DCUTDO/LPDO) TCK/LPDCLK JP0_2 (DCUTCK/LPDCLK)

  • Page 34: Figure 17 Rh850/F1K Nexus, 4Pin Lpd And 1Pin Lpd Debug Interface Connection

    RH850/F1K Series Hardware Design Guide E1 Emulator RH850/F1K Group (14pin Connector) EVCC TVDD EVSS 1k to 4.7kΩ Note 1 Note 3 TDI/LPDIO JP0_0 (DCUTDI/LPDIO, LPDI) TDO/LPDO JP0_1 (DCUTDO/LPDO) TCK/LPDCLK JP0_2 (DCUTCK/LPDCLK) JP0_3 (DCUTMS) TRST JP0_4 (DCUTRST) RDY/LPDCLKOUT JP0_5 (DCURDY/LPDCLKOUT) EVTO...

  • Page 35: Table 21 Debug Interface Signal Connection Of Rh850/F1K

    RH850/F1K Series Hardware Design Guide The debug interface signal connection of the E1 interface is given in the table below: Table 21 Debug interface signal connection of RH850/F1K E1 Interface Connector E1 Interface Signal RH850/F1K Device Pin LPDCLK/(DCUTCK) JP0_2 EVSS...

  • Page 36: Flash Programming Interface Connection Of Rh850/F1K Group

    RH850/F1K Series Hardware Design Guide 6.1.2 Flash Programming Interface Connection of RH850/F1K Group For the programming environment PG-FP5, the following connections are supported: • Single-wire asynchronous flash programming interface • Two-wire asynchronous flash programming interface • Synchronous flash programming interface For the programming environment combination of E1 emulator and RFP, the following connections are supported: •...

  • Page 37: Figure 18 Rh850/F1K Pg-Fp5 Flash Programming Interface Connection

    RH850/F1K Series Hardware Design Guide Flash Programming by PG-FP5 PG-FP5 Flash Programmer (14pin Connector) RH850/F1K Group EVCC EVSS RxD/TxD/SO JP0_0 (RxD/TxD/SI) RxD/SI JP0_1 (TxD/SO) JP0_2 (SCK) JP0_4 FPMD0 FLMD0 FPMD1 P10_8 (FLMD1) 100kΩ 10k to 100kΩ 1k to 10kΩ RESET...

  • Page 38: Figure 19 Rh850/F1K E1 Flash Programming Interface Connection

    RH850/F1K Series Hardware Design Guide Flash Programming by E1 emulator and RFP E1/RFP Flash Programmer (14pin Connector) RH850/F1K Group EVCC TVDD EVSS FPDR JP0_0 (RxD/TxD) FPDT JP0_1 (TxD) JP0_4 FPMD0 FLMD0 FPMD1 P10_8 (FLMD1) 100kΩ 10k to 100kΩ 1k to 10kΩ...

  • Page 39: Combined Debug And Flash Programming Interface Connection Of Rh850/F1K Group

    RH850/F1K Series Hardware Design Guide 6.1.3 Combined Debug and Flash Programming Interface Connection of RH850/F1K Group The following figure describes the combined connections for debugging and flash programming of the RH850/F1K group, supporting  1pin Low-pin debug interface (1pin LPD) ...

  • Page 40: Debug And Flash Programming Interface Connection Of Rh850/F1K Group When The Internal Hsosc Is Used As Clock Supply

    RH850/F1K Series Hardware Design Guide 6.1.4 Debug and Flash Programming Interface Connection of RH850/F1K Group when the internal HSOSC is used as Clock Supply When the devices of the RH850/F1K group are supply only with the internal high-speed oscillator (HSOSC) the following functions are supported ...
  • Page 41 RH850/F1K Series Hardware Design Guide  JP0_0: LPDI input  JP0_1: LPDO output  JP0_2: LPDCLK input  JP0_3: General-purpose I/O  JP0_4: General-purpose I/O  JP0_5: LPDCLKOUT output  JP0_6: General-purpose I/O R01AN2911EJ0100 Rev. 1.00 Page 41 of 46...

  • Page 42: Debug Considerations When Hot Plug-In Is Used

    RH850/F1K Series Hardware Design Guide 6.1.5 Debug Considerations when Hot Plug-in is used When it is planned to use the hot plug-in function for debugging the following topics should be considered. RESET pin When the hot plug-in will be used it is recommended to consider the installation of a capacitor between the reset signal and GND in order to suppress a noise.

  • Page 43: Boundary Scan Mode Interface Of Rh850/F1K Group

    RH850/F1K Series Hardware Design Guide Boundary Scan Mode Interface of RH850/F1K Group The boundary scan test is compliant with IEEE Standard 1149.1 and certain boundary scan instructions are supported. When the boundary scan mode shall be used, several connections have to be done between boundary scan test tool and the device.

  • Page 44: Reference Documents

    RH850/F1K Series Hardware Design Guide Reference Documents Item Document No. Document Title Preliminary User’s Manual Hardware RH850/F1K Group (including R01UH0562EJxxxx electrical characteristics) R01TU0100EDxxxx RH850/F1K Operating Precaution Application note “PCB-Design for Improved EMC” R01AN0733EDxxxx E1/E20 Emulator, Additional Document for User’s Manual (Notes in...

  • Page 45: Abbreviations

    RH850/F1K Series Hardware Design Guide Abbreviations A/D-converter HSOSC internal High-speed Oscillator HWTRG Hardware Trigger MOSC Main Oscillator Multiplexer Scan Group SOSC Sub Oscillator SWTRG Software Trigger R01AN2911EJ0100 Rev. 1.00 Page 45 of 46 Aug 04, 2016...

  • Page 46: Website And Support

    RH850/F1K Series Hardware Design Guide Website and Support Renesas Electronics Website http://www.renesas.com/ All trademarks and registered trademarks are the property of their respective owners. R01AN2911EJ0100 Rev. 1.00 Page 46 of 46 Aug 04, 2016...

  • Page 47: Revision History

    Revision History Description Rev. Date Section Summary 0.10 2015-08-26 Initial version 0.50 2015-12-17 Typing error correction RH850/F1K Group name adjusted Target RH850/F1K-100 ECO removed according to RH850/F1K Hardware user’s manual Device 3.1.1 MOSC value adjusted according to RH850/F1K Hardware user’s manual 4.3.1 Recommended connection of unused pins updated ADC equivalent input circuit values changed to tbd...

  • Page 48: General Precautions In The Handling Of Mpu/Mcu Products

    General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
  • Page 49 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products.

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