20 Khz Oscillator; Head-Drive Amplifier; Detector Gate Amplifier; 40 Khz Input/Amplifier Circuit - HP 428B Operating And Service Manual

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Model 428B
wire that is clamped in the probe jaws. (c) To conduct the
dc feedback current that tends to annul the energizing dc
current from the wire being measured.
4-18. Because the coils are electrically arranged in a
balanced bridge circuit, the 20 kHz signal is balanced at
the output of the bridge (pins 3 and 4); and there is no 20
kHz differential signal at this point. The 40 kHz signal and
the dc feedback current are also nulled out by the
balanced bridge so that these signals do not appear as a
differential voltage across pins 1 and 2. The dc feedback
current is isolated from the 40 kHz amplifier by capacitor
C11. The 40 kHz is kept out of the dc circuitry by RF
choke L6.

4-19. 20 kHz OSCILLATOR.

4-20. The function of the 20 kHz oscillator is to generate a
balanced 20 kHz signal which, after amplification, is used
for driving the probe head in and out of saturation.
4-21. The circuit of the 20 kHz oscillator is shown in
Figure 7-10. The oscillator V7 is operating in push-pull
having a plate circuit tuned to 20 kHz. Transformer
coupling provides positive feedback through resistor R94
and R95 to the oscillator control grids. The control grids of
oscillator V7 supply the drive signal for the push-pull head
drive amplifier V8. The oscillator level is adjusted by
controlling the cathode current of V7.
4-22.
The common cathodes of oscillator V7 supply the
40 kHz signal (2 pulses per 20 kHz cycle) needed for the
synchronous detector gate amplifier V5 and the 40 kHz
phase shifter.

4-23. HEAD-DRIVE AMPLIFIER.

4-24. The head-drive amplifier V8 supplies the balanced
20 kHz signal for the probe head. Drive balance
adjustment R98 controls the current ratio of the two triode
sections, and hence the second harmonic output. The dc
bias voltage for the oscillator and the head-drive amplifier
is obtained from reference tube V11.

4-25. DETECTOR GATE AMPLIFIER.

4-26. The 40 kHz resonant circuit C1, C2, and L5
increases the level of the gate signal and filters out all
signals except 40 kHz. It also allows phase adjustment of
the signal to correspond to the phase of the Synchronous
Detector.
4-27. The operation of the Synchronous Detector requires
a high level 40 kHz signal. The 40 kHz output signal of
the oscillator V7 passes through a tuned circuit and drives
the gate amplifier V5. The output of V5 delivers a 40 kHz
gate signal to the Synchronous Detector.

4-28. 40 kHz INPUT/AMPLIFIER CIRCUIT.

4-29. The 40 kHz output voltage of the probe head is
resonated by a 40 kHz series resonant circuit (L5 and
C1/C2). Resistor R1 broadens the resonance response
by lowering the Q to minimize drift problems. The 40 kHz
11
signal passes through a voltage divider SI B, which
keeps the loop gain constant for all current ranges by
maintaining a constant input level range to stage VI. The
output of the 40 kHz amplifier VI is band-pass coupled to
the 40 detector driver stage V2. The output signal of V2
is isolated from ground by transformer T2, and fed to the
40 synchronous detector.

4-30. SYNCHRONOUS DETECTOR AND FILTER (C24).

4-31. The Synchronous Detector detects the amplitude
and the phase of the 40 kHz signal. Phase detection is
necessary to preserve negative feedback at all times.
Since the probe may be clipped over the wire in either of
two ways the phase of the signal may vary by 1800. If
phase detection were not present this 1800 phase
reversal would cause positive feedback and the
instrument would oscillate. With phase detection the
polarity of the feedback will change also, maintaining the
feedback negative around the system at all times.
4-32. The synchronous detector requires a large 40 kHz
gating signal, having the frequency of the desired signal.
Figure 4-7 shows the synchronous detector drawn as a
bridge circuit.
4-33. On one half-cycle, with A much more positive than
E and with B equally more negative that E, the balanced
circuit ACB conducts hard, and C becomes effectively
equal to point E. Circuit BDA is opened at this time by its
back-biased diodes, and only the signal that appears
across the conducting half of the T2(FC) will charge C24.
4-34. On the next half-cycle BDA conducts, ACB
becomes open, and the signal across FD will charge C24.
If signal F is positive with respect to C on the first
half-cycle, signal F will be positive with respect to D on
the second half-cycle, and the top of C24 will consistently
be charged positive. If the signal at F changes phase by
1800 with respect to the gating signal at T3, the top of
C24 will consistently be charged negative.

Figure 4-7. Detector Bridge.

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