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Chapter 5
Gate Types
The edge or level of the Counter 0 Gate signal determines when a counter/timer operation is
enabled. Using software, you can specify one of the following gate types:
• None – A software command enables any counter/timer operation immediately after
• Logic-high level external gate input – Enables a counter/timer operation when Counter 0
• Falling-edge external gate input – Enables a counter/timer operation when a high-to-low
• Rising-edge external gate input – Enables a counter/timer operation when a low-to-high
Pulse Duty Cycles
Counter/timer output signals from the modules are high-to-low going signals.
The duty cycle (or pulse width) indicates the percentage of the total pulse output period that is
active. In rate generation mode, the duty cycle is fixed at 50% for the DT9812, DT9813, and
DT9814 Series modules.
cycle of 50%.
Figure 22: Example of a Pulse Output SIgnal with a 50% Duty Cycle (High-to-Low Going)
72
execution.
Gate is high, and disables a counter/timer operation when Counter 0 Gate is low. Note
that this gate type is used for event counting and rate generation modes; refer to
for more information about these modes.
transition is detected on the Counter 0 Gate signal. In software, this is called a low-edge
gate type. Note that this gate type is used for edge-to-edge measurement mode; refer to
page 74
for more information about these modes.
transition is detected on the Counter 0 Gate signal. In software, this is called a high-edge
gate type. Note that this gate type is used for edge-to-edge measurement operations; refer
to
page 74
for more information about these modes.
Figure 22
Total Pulse Period
Active Pulse Width
illustrates a high-to-low going output pulse with a duty
high pulse
low pulse
page 73
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