Espressif ESP01 Quick Start Manual page 6

2 . PIN DEFINITIONS
2.3 Strapping Pins
Please refer to ESP01 schematics.
ESP32 has five strapping pins, which can be seen in Chapter
• MTDI
• GPIO0
• GPIO2
• MTDO
• GPIO5
Software can read the value of these five bits from the register "GPIO_STRAPPING".
During the chip's system reset (power-on reset, RTC watchdog reset and brownout reset), the latches of the
strapping pins sample the voltage level as strapping bits of "0" or "1", and hold these bits until the chip is powered
down or shut down. The strapping bits configure the device boot mode, the operating voltage of VDD_SDIO and
other system initial settings.
Each strapping pin is connected with its internal pull-up/pull-down during the chip reset. Consequently, if a strap-
ping pin is unconnected or the connected external circuit is high-impendence, the internal weak pull-up/pull-down
will determine the default input level of the strapping pins.
To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or apply the host
MCU's GPIOs to control the voltage level of these pins when powering on ESP32.
After reset, the strapping pins work as the normal functions pins.
Refer to Table 4 for detailed boot modes' configuration by strapping pins.
Pin Default
MTDI Pull-down
Pin Default
GPIO0 Pull-up
GPIO2 Pull-down
Pin Default
MTDO Pull-up
Pin Default
MTDO Pull-up
GPIO5 Pull-up
Note:
Firmware can configure register bits to change the settings of "Voltage of Internal LDO (VDD_SDIO)" and "Timing of SDIO
Slave" after booting.
Table 4: Strapping Pins
Voltage of Internal LDO (VDD_SDIO)
3.3V
0
SPI Boot
1
Don't-care
Debugging Log on U0TXD During Booting
U0TXD Toggling
1
Timing of SDIO Slave
Falling-edge Input Falling-edge Input
Falling-edge Output Rising-edge Output
0 0
0 1
6 Schematics:
Booting Mode
Rising-edge
Falling-edge Output
1
0
1.8V
1
Download Boot
0
0
U0TXD Silent
0
Input Rising-edge Input
Rising-edge Output
1
1