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• Program working memory (IC101 - IC104): Four pieces of DDR2 (128 MB) accessible with 64-bit, 600MHz
• Memory to store the program (IC303): Flash ROM (32 MB)
• Communication between SY-422A board and PCI Express card: IC704 (PCI Express switch) switches four sets of
2-Gbps lanes to connect the SRIO FPGA IC3 on the SY-422A board to the PCI Express card.
• CPU communication: Communication with the SY-422A board through the connector CN703 is possible.
• PIO (Programmed I/O): LED, test pin, DIP switch
• Power supply: Voltage +12 V supplied from the SY-422A board is converted to other voltages that are supplied to
the CPU, DDR2, PCI Express switch, Ethernet PHY, and other devices.
• Clocks:
- X100: Generates 100MHz clock (for CPU).
- X700: Generates 25MHz clock (for PCI Express).
• Reset circuit: IC1105 generates a reset signal and sends it to each block.
1-4-3.
RC-107 Board
RC-107 board is a relay board that is connected to the connector CN702 on the CPU-453A board, and transmits signals
to the PCI Express socket CN102 on the RC-107 board.
1-4-4.
DIO-95 Board
The DIO-95 board inputs audio and video signals.
Video signal processing (input mode)
The DIO-95 board has 9-channel SDI inputs/outputs operating as 4-channel input, 4-channel monitor input, and 1-
channel HD SDI input to enable 4K processing.
The 4K SDI signals from the connectors (CN201, CN202) are input through the equalizer (IC201 to IC204) to the
baseband FPGA (IC100). Then the SDI signals are decoded in IC100 and the decoded SDI signals are input as parallel
signals to the video encoder (IC1000, IC1200, IC1400, IC1600) in which the parallel signals are compressed to XAVC-
Intra frame data.
In the same way, HD SDI signals from the connector CN301 are input through the equalizer IC302 to the baseband
FPGA (IC100). Then the HD SDI signals are compressed to XAVC-Intra frame data by the video encoder (IC1800).
The compressed signals are input to the backplane FPGA (IC2200) and stored in the DRAM (IC3002, IC3003). Then
the signals are multiplexed sequentially with audio data, video data, and uncompressed meta data, and the multiplexed
signals are transferred through DMA (Direct Memory Access) to the BANK FPGA (IC1) on the DM-154 board with
3.125 Gbps serial transmission. This DMA transfer includes 4K HD independently for each system.
Audio signal processing (input mode)
The DIO-95 board has four AES/EBU connectors (CN3601, CN3602) allowing input for eight channels.
Furthermore, the HD SDI embedded audio signals for 16 channels can be input, and each channel is independently
selectable.
AES/EBU-format digital audio signals and HD SDI embedded audio signals are input to the audio FPGA (IC300) in
which processes (channel selection, gain control, etc.) are performed. The processed signals are input to the backplane
FPGA (IC200) in the same way as video signals.
After the audio signals are stored in the DRAM (IC3002, IC3003), they are multiplexed with video signals and the
multiplexed signals are DMA transferred to the BANK FPGA (IC1) on the DM-154 board with 3.125 Gbps serial
transmission.
Timecode signal processing (input mode)
The timecode signal that is input from the timecode input connector (CN302) is input to the baseband FPGA (IC100)
in which parallel processing is applied to the signal, and then the processed timecode signal is detected by the CPU. The
same timecode signal is output from the timecode output connector (CN302) for cascade processing.
PWS-4400
1-25
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