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4.6.8
FPGA Configuration
The RTM FPGA configuration is loaded at power-up from one of two SPI Flash devices. One
device is writable/upgradeable and the other is non-writable/golden for recovery purposes.
The selection is which device is used is controlled by switch S1 position 1, according to the
following table.
Table 4-8 FPGA Configuration Controls
Switch Setting
S1.1 = Off
S1.1 = On
The configuration Flash devices can be field upgraded using a SPI-controlled Flash programmer
in the FPGA.
4.7
Reset Scheme
The front-blade provides a single reset signal, RTM_RST#, over the zone 3 connectors. This
signal is asserted when a master reset of the front-blade occurs.
RTM_RST# directly resets the RTM FPGA. The BCM8747 devices are reset from a secondary
reset generated by the RTM FPGA. This allows software control of the phy resets in addition to
hardware control using the RTM_RST# signal. After a hardware reset, the phys are held in reset
until released by software.
4.8
Power Management
The front-blade provides two separate power supplies using the Zone 3 connectors:
+3.3 V management power — one pin
+12 V payload power — four pins
The maximum current draw, which is limited by the pin's current handling capability, is 0.8A for
the management power and 3.2A for the payload power.
RTM-ATCA-F125 Installation and Use (6806800K30C)
FPGA Flash
Writable Bank (default)
Non-writable (golden)
Functional Description
47
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