Infinity Classia Series Service Manual page 35

PSW310W subwoofer Classia Series
Philips Semiconductors
8-bit parallel-in/serial-out shift register
FEATURES
• Asynchronous 8-bit parallel load
• Synchronous serial input
• Output capability: standard
• I
category: MSI
CC
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q
Q ) available from the last stage. When the parallel load
7
(PL) input is LOW, parallel data from the D
D inputs are loaded into the register asynchronously.
7
QUICK REFERENCE DATA
= 25 °C; t
GND = 0 V; T
amb
SYMBOL
t / t propagation delay
PHL PLH
CP to Q
PL to Q
D to Q
7
f maximum clock frequency
max
C input capacitance
I
C power dissipation capacitance per
PD
package
Notes
1. C is used to determine the dynamic power dissipation (P
PD
× V
P = C
D PD CC
f = input frequency in MHz
i
f = output frequency in MHz
o
∑ (C × V × f
2
) = sum of outputs
L CC o
C = output load capacitance in pF
L
V = supply voltage in V
CC
2. For HC the condition is V
For HCT the condition is V
ORDERING INFORMATION
See "74HC/HCT/HCU/HCMOS Logic Package Information"
and
7
to
0
= t = 6 ns
r f
PARAMETER
Q
7, 7
Q
7, 7
Q
7, 7
× f + ∑ (C × V × f
2 2
) where:
i L CC o
= GND to V
I CC
− 1.5 V
= GND to V
I CC
When PL is HIGH, data enters the register serially at the
D input and shifts one place to the right
s
→ Q → Q
(Q , etc.) with each positive-going clock
0 1 2
transition. This feature allows parallel-to-serial converter
expansion by tying the Q
succeeding stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
APPLICATIONS
• Parallel-to-serial data conversion
CONDITIONS
C = 15 pF; V = 5 V
L CC
16
15
11
56
3.5
notes 1 and 2 35
in µW):
D
.
34
Product specification
74HC/HCT165
output to the D input of the
7 S
TYPICAL
HC HCT
14 ns
17 ns
11 ns
48 MHz
3.5 pF
35 pF
UNIT