Xilinx Alveo U50 User Manual
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Xilinx Alveo U50 User Manual

Xilinx Alveo U50 User Manual

Data center accelerator card
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Alveo U50 Data Center
Accelerator Card
User Guide
UG1371 (v1.2) December 18, 2019

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Summary of Contents for Xilinx Alveo U50

  • Page 1 Alveo U50 Data Center Accelerator Card User Guide UG1371 (v1.2) December 18, 2019...

  • Page 2: Revision History

    Card Features Removed bullets about HBM2 memory. • Added note about power rails. Board Support Files for the Alveo U50 Card Added link for Xilinx Board Store to introductory paragraph. • Card Power System Updated paragraph with power rail information.

  • Page 3: Table Of Contents

    Design Flows..........................9 Chapter 2: Vivado Design Flow ................10 Board Support Files for the Alveo U50 Card................10 Creating an RTL Project Based on the U50 Board File............11 Creating an MCS File and Programming the Alveo Card............. 12 Chapter 3: Card Installation and Configuration .........
  • Page 4 Other Compliance Statements....................24 Appendix C: Additional Resources and Legal Notices ......28 Xilinx Resources.........................28 Documentation Navigator and Design Hubs.................28 References..........................28 Please Read: Important Legal Notices................... 30 UG1371 (v1.2) December 18, 2019 www.xilinx.com Send Feedback Alveo U50 Accelerator Card User Guide...

  • Page 5: Chapter 1: Introduction

    ® ) Gen3 x16 compliant and Gen4 x8 compatible cards featuring the Xilinx 16 nm UltraScale+™ technology. The Alveo U50 card offers 8 GB of HBM2 to provide high- performance, adaptable acceleration for memory-bound, compute-intensive applications including database, analytics, and machine learning inference.
  • Page 6 The Alveo™ U50 card is available in a passive cooling configuration only and is designed for installation into a data center server where controlled air flow provides direct cooling to the card. The following figure shows the Alveo U50 accelerator card with half-height bracket installed. The card includes the following interfaces: 1.

  • Page 7: Card Features

    • 75W PCIe slot power only Note: The Alveo U50 card has separate power rails for FPGA fabric and HBM memory. Developers must ensure their designs do not draw too much power for each rail. More information can be found in the Known Issues table of the Alveo U50 Data Center Accelerator Card Installation Guide (UG1370).
  • Page 8 GTY x4 40 GbE Xilinx 4x 10 GbE XCU50 UART 4 GB EP GTY x16 Satellite PCIe Controller (Gen3 x16 or SMBus two Gen4 x8) X22939-072919 UG1371 (v1.2) December 18, 2019 www.xilinx.com Send Feedback Alveo U50 Accelerator Card User Guide...

  • Page 9: Design Flows

    Vivado Design Suite User Guide: System-Level Design Entry (UG895). See “Using the Vivado Design Suite Platform Board Flow” in Chapter 2 and Appendix A. Vitis Accelerated Flow in the Vitis Unified Software Platform Documentation (UG1416). Alveo U50 Data Center Accelerator Card Installation Guide (UG1370). UG1371 (v1.2) December 18, 2019 www.xilinx.com Send Feedback...

  • Page 10: Chapter 2: Vivado Design Flow

    Board Support Files for the Alveo U50 Card Prior to creating an RTL project based on the Alveo™ U50 card, update the board support repository to include the Alveo U50 card by following the steps listed below. Board support files can also be downloaded from the Xilinx Board Store.

  • Page 11: Creating An Rtl Project Based On The U50 Board File

    5. Within the Default Part window, select Boards and enter u50 in the search tab. Select the U50 card and click Next as shown in the following figure. This will create a new RTL project based on the Alveo U50 accelerator card. UG1371 (v1.2) December 18, 2019 www.xilinx.com...

  • Page 12: Creating An Mcs File And Programming The Alveo Card

    -force -format mcs -interface spix4 -size 1024 -loadbit "up 0x01002000 <input_file.bit>" -file "<output_file.mcs>" Where: • <input_file.bit> is the filename of the input .bit file • <output_file.mcs> is the MCS output filename UG1371 (v1.2) December 18, 2019 www.xilinx.com Send Feedback Alveo U50 Accelerator Card User Guide...
  • Page 13 PCIe downlink causing the server to reboot during programming. Alternatively, the PCIe link can be manually disabled through software and rescanned after programming is complete. 1. Connect to the Alveo U50 Data Center accelerator card using the Vivado hardware manager through the DMB.

  • Page 14: Chapter 3: Card Installation And Configuration

    Before you pick it up again, touch the antistatic bag and the metal frame of the system at the same time. • Handle the devices carefully to prevent permanent damage. UG1371 (v1.2) December 18, 2019 www.xilinx.com Send Feedback Alveo U50 Accelerator Card User Guide...

  • Page 15: Installing Alveo Data Center Accelerator Cards In Server Chassis

    Chapter 3: Card Installation and Configuration Installing Alveo Data Center Accelerator Cards in Server Chassis For hardware and software installation procedures, see the Alveo U50 Data Center Accelerator Card Installation Guide (UG1370). Because each server or PC vendor's hardware is different, for physical board installation guidance, see the manufacturer’s PCI Express...

  • Page 16: Chapter 4: Card Component Description

    Center accelerator card. UltraScale+ FPGA The Alveo U50 accelerator card is populated with the 16 nm UltraScale+™ XCU50 FPGA. This UltraScale+ HBM device incorporates two 4 GB high-bandwidth memory (HBM) stacks adjacent to the device die. Using SSI technology, the device communicates to the HBM stacks through memory controllers that connect through the silicon interposer at the bottom of the device.

  • Page 17: Maintenance Connector Interface

    File. Maintenance Connector Interface The Alveo U50 accelerator card provides access to the FPGA through the JTAG interface using a debug and maintenance board (DMB) connected to the 30-pin maintenance connector. The connector pinout supports three UART debug interfaces: PMBus, FPGA JTAG, and satellite controller JTAG.

  • Page 18: Sfp-Dd Module Connectors

    • The target for SFP-DD channel length is 4 inches maximum Note: The Alveo U50 card that includes one QSFP interface is production qualified for deployment. The Alveo U50DD ES3 card that supports two SFP-DD interfaces is not recommended for deployment.

  • Page 19: Card Power System

    More information can be found in the Known Issues table of the Alveo U50 Data Center Accelerator Card Installation Guide (UG1370). To monitor, limited power system telemetry is available through the I2C IP. I2C IP is instantiated during the FPGA design process which begins after the Alveo Data Center accelerator card is selected from the Vivado Design Suite Boards tab.
  • Page 20 Chapter 4: Card Component Description TIP: For accelerated flows, you can use xbutil query to monitor power system telemetry. UG1371 (v1.2) December 18, 2019 www.xilinx.com Send Feedback Alveo U50 Accelerator Card User Guide...

  • Page 21: Appendix A: Xilinx Design Constraints (Xdc) File

    The Alveo accelerator card XDC files are available for download from their respective websites along with this user guide. Note: Bitstream constraints are not available for download because they are user-generated. UG1371 (v1.2) December 18, 2019 www.xilinx.com Send Feedback Alveo U50 Accelerator Card User Guide...

  • Page 22: Appendix B: Regulatory And Compliance Information

    This product is designed and tested to conform to the European Union directives and standards described in this section. Safety Compliance The following table shows the safety standards that apply to the Alveo U50 and U50DD cards. Table 7: Safety Standards Safety Standard...

  • Page 23: Ce Directives

    Article 58-2 of Radio Waves Act, Clause 3 (Korea) Regulatory Compliance Markings The following table shows the product certification markings that are provided, when required, with the Alveo U50 and U50DD cards. Table 9: Product Certification Markings Product Certification Markings...

  • Page 24: Compliance Markings

    Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life.
  • Page 25 Interferenzen verursachen. In diesem Fall muss der Benutzer die Interferenz auf eigene Kosten beheben. CAUTION! If the device is changed or modified without permission from Xilinx, the user may void his or her authority to operate the equipment.
  • Page 26 BSMI Class A Notice (Taiwan) Manufacturer Declaration European Community Manufacturer Declaration Xilinx declares that the equipment described in this document is in conformance with the requirements of the European Council Directive listed below: • Low Voltage Directive 2014/35/EU • EMC Directive 2014/30/EU •...
  • Page 27 Fall muss der Benutzer möglicherweise geeignete Maßnahmen ergreifen. Responsible Party Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124 United States of America Phone: (408) 559-7778 UG1371 (v1.2) December 18, 2019 www.xilinx.com Send Feedback Alveo U50 Accelerator Card User Guide...

  • Page 28: Appendix C: Additional Resources And Legal Notices

    • On Windows, select Start → All Programs → Xilinx Design Tools → DocNav. • At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: •...
  • Page 29 Alveo U50 Data Center Accelerator Card Supplemental Documents The following Xilinx document provide supplemental material useful with this guide. • UltraFast Design Methodology Guide for the Vivado Design Suite (UG949) • Vivado Design Suite User Guide: System-Level Design Entry (UG895) •...

  • Page 30: Please Read: Important Legal Notices

    IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for...
  • Page 31 Appendix C: Additional Resources and Legal Notices Copyright © Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

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