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Xilinx Versal ACAP CPM4 Product Manual

Xilinx Versal ACAP CPM4 Product Manual

Cpm mode for pci express
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Versal ACAP CPM Mode for
PCI Express
Product Guide
Vivado Design Suite
PG346 (v3.3) November 16, 2022
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Summary of Contents for Xilinx Versal ACAP CPM4

  • Page 1 Product Guide Vivado Design Suite PG346 (v3.3) November 16, 2022 Xilinx is creating an environment where employees, customers, and partners feel welcome and included. To that end, we’re removing non- inclusive language from our products and related collateral. We’ve launched an internal initiative to remove language that could exclude people or reinforce historical biases, including terms embedded in our software and IPs.

  • Page 2: Table Of Contents

    Customizing and Generating the CIPS IP Core for CPM4..........188 Customizing and Generating the CIPS IP Core for CPM5..........211 Appendix A: GT Selection and Pin Planning for CPM4 ......237 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 3 Guidance for CPM5 Migration from Specifically Identified Engineering Sample Devices..........................251 CPM5 GTYP Locations......................251 Appendix C: Debugging ...................253 Finding Help on Xilinx.com....................253 PCIe Link Debug Enablement....................254 Appendix D: Using the High Speed Debug Port Over PCIe for Design Debug ......................261 Overview...........................261...

  • Page 4: Chapter 1: Overview

    Chapter 1: Overview Chapter 1 Overview Navigating Content by Design Process Xilinx ® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal ® ACAP design process...

  • Page 5: Introduction To The Cpm4

    • The CPM4 DMA features are supported only with CPM4 PCIe Controller 0. For more information about CPM4 DMA features, see the Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 6 Ctrl Integrated PCIe RAM Block attr_*0 attr_*1 attr_dma_* Programming Register Space Program- ming Hard I/F dbg_0_0 dbg_0_1 dbg_1_0 dbg_1_1 ARM(*) CoreSight I/F Module Internal Hard I/F X22665-072320 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 7 AXI4-Stream Layer The AXI4-Stream layer implements Xilinx-specific requirements. In the transmit or outbound direction, the AXI4 layer interfaces the transaction layer with two AXI4-Stream interfaces. In the receive or inbound direction, the transaction layer output is forwarded to two AXI4-Stream interfaces.
  • Page 8 Standards The CPM4 block adheres to the following standards: • PCI Express Base Specification 4.0 Version 1.0, and Errata updates (available at http:/ / pcisig.com/specifications). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 9 ○ • Features that enable high-performance applications include: AXI4-Stream TLP Straddle on Requester Completion Interface ○ Address Translation Services (ATS) and Page Request Interface (PRI) Messaging ○ PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 10 Optional ASPM support for endpoint port types only; ASPM is not supported for other ○ port types. Configuration extend interface ○ AXI4-Stream interfaces address align mode ○ Debug and diagnostics interface ○ PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 11: Introduction To The Cpm5

    DMA Core Integrated PCIe RAM Block attr_*0 attr_*1 attr_dma_* Programming Register Space Program- ming Hard I/F dbg_0_0 dbg_0_1 dbg_1_0 dbg_1_1 ARM(*) CoreSight I/F Module Internal Hard I/F X22665-072320 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 12 AXI4-Stream Layer The AXI4-Stream layer implements Xilinx-specific requirements. In the transmit or outbound direction, the AXI4 layer interfaces the transaction layer with two AXI4-Stream interfaces. In the receive or inbound direction, the transaction layer output is forwarded to two AXI4-Stream interfaces.
  • Page 13 • Cache Coherent Interconnect for Accelerators (CCIX) Base Specification 1.1, and Errata/ECN updates (available at http:/ /www.ccixconsortium.com). • CCIX Transport Specification 1.0 (available at http:/ /www.ccixconsortium.com). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 14 One PCI Express Compliant Virtual Channel, eight Traffic Classes ○ One CCIX Compliant Virtual Channel ○ • Supports multiple Functions and Single-Root IO Virtualization Up to 16 Physical Functions ○ PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 15 Optional ASPM support for endpoint port types only; ASPM is not supported for other ○ port types. Configuration extend interface ○ AXI4-Stream interfaces address align mode ○ Debug and diagnostics interface ○ PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 16: Use Modes

    Endpoint port on the ACAP (on an add-in card) to a root complex or that switch downstream port through a PCI Express connector. The following figure shows a block diagram of the bus mastering Endpoint use case. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 17 Figure 3: Basic PCI Express Bus Mastering Endpoint Use Case CPM PCIe Controller Completer Interfaces Requester Interfaces CONTROL LOGIC Control & Status Registers Initiator Interface Bus Mastering (DMA) Logic Bridge to User Application X22666-071620 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 18 Figure 4: Illustrative Example of Two Function Endpoint Use Case CPM PCIe Controller Arbiter/Demux FUN0 FUN1 Control Control Regs Regs Application Application Function #0 Function #1 X22667-071620 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 19 Figure 5: Illustrative Example of Endpoint with SR-IOV Use Case Host Application Guest OS VF Driver PF Driver PCIe Link CPM PCIe Controller Control Control Regs Regs Application X22668-071620 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 20 -based processor system (PS) containing most of the critical blocks such as CPU, memory controller and other important peripherals. One of the goals of this use case is to minimize ACAP soft logic requirements. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 21 32-bit AXI Master 32-bit AXI Slave 64-bit Slave 32/64 System Controller AXI1 AXI0 128b 128b Interrupts 64/128b 64/128b AXI MM PCIe PCIe 4.0 System System PCIe Reset Clock X22670-121420 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 22: Licensing And Ordering

    Chapter 1: Overview Licensing and Ordering This Xilinx ® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado ® Design Suite under the terms of the Xilinx End User License. For more information about this Versal ®...

  • Page 23: Chapter 2: Tandem Configuration

    100 ms boot time requirement, even though 120 ms is the fundamental goal. Xilinx devices can meet this 120 ms link training requirement by using Tandem Configuration, a solution that splits the programming image into two stages. The first stage quickly configures the PCIe endpoint(s) so the endpoint is ready for link training within 120 ms.

  • Page 24: Enable The Tandem Configuration Solution

    Chapter 2: Tandem Configuration The Dynamic Function eXchange (DFX) feature supported by much of the Xilinx silicon portfolio and Vivado Design Suite allows for the reconfiguration of the modules within an active device. It gives system architects the flexibility to switch a portion of the design in and out depending on the system requirements, removing the need to multiplex multiple functions in a larger device, which saves on part cost, power and improves system up time.
  • Page 25 CPM Basic Configuration customization page. The specific aperture within the PMC slave that must be accessible from the host is the Slave Boot Interface (SBI) which is available at Versal address 0x102100000. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 26 32-bit address transactions. To reach the SBI buffer address, the NOC NMU address remapping capability must be employed, see the following recommended command. set_property CONFIG.REMAPS {M00_AXI {{0xF122_0000 0x1_0122_0000 64K} {0xF210_0000 0x1_0210_0000 64K}}} [get_bd_intf_pins /axi_noc_0/S00_AXI] PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 27 To deliver stage 2 images using PCIe DMA, the DMA BAR must be set to BAR0. The driver will probe BAR0 to find the DMA BAR. If this goes to the PL the transaction will not complete, because the PL is not yet configured. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 28 • tandem1.pdi: This file should be added to the device configuration flash. • tandem2.pdi: This file should be programmed into the device through the PCIe link once it becomes active. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 29 Similarly, the behavior of Tandem PROM or Tandem PCIe file generation can be disabled entirely by using the HD.TANDEM_BITSTREAMS property on the implemented design before .pdi file generation. The following command can be used to do this. set_property HD.TANDEM_BITSTREAMS NONE [current_design] PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 30: Deliver Programming Images To Silicon

    PCIe transactions (typically around 700 Mbytes/s for 64-byte transfers from the host). Xilinx does not provide sample drivers and software for this because either the XDMA or QDMA data paths are typically enabled with this mode and allow for higher transfer rates.

  • Page 31: Tandem Configuration Performance

    1 Mbytes/s). This mode of configuration should only be used when the other three data paths are not available. This includes PCIe Streaming and CCIX modes on either controller. Note: Xilinx provides sample drivers and software to enable stage 2 programming. These drivers can be found at https:/ /github.com/Xilinx/dma_ip_drivers.

  • Page 32: Loading Tandem Pcie For Stage 2

    PCIe since the datapaths are the same. To configure a design for DFX and generate partial bitstreams for reconfigurable modules, refer to Vivado Design Suite User Guide: Dynamic Function eXchange (UG909). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 33 Chapter 2: Tandem Configuration Using the Provided Software and Drivers The open-source, Xilinx provided drivers and user space applications for the MCAP VSEC, QDMA, and XDMA IPs can be found at https:/ /github.com/Xilinx/dma_ip_drivers to be cloned or downloaded. There is also extensive documentation on each of the drivers contained in the repository and linked to external pages.
  • Page 34 $> xvsecctl -b 0x01 -F 0x0 -c 1 -p mode 128b type fixed 0xF2100000 <.pdi file> tr_mode fast [sbi 0xF1220000] PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 35 Figure 12: Tandem CED Block To open an example design, perform the following steps: 1. Launch Vivado. 2. Navigate to the set of example designs for selection. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 36: Known Issues And Limitations

    Upon stage 2 completion, this isolation is released and it is not re-enabled for a dynamic reload of the stage 2 image. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 37 Tandem PROM and impossible for Tandem PCIe. If compliant link training is a fundamental requirement, be sure to use a device with the CPM and enable the Tandem feature within CIPS customization. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 38: Chapter 3: Product Specification

    -40 to 0.78 1000 +110 -2MP -40 to 0.78 1000 781.25 390.625 +110 -2HP -40 to 0.88 1000 781.25 390.625 +110 -1MQ -40 to 0.78 1000 (derated) +125 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 39: Minimum Device Requirements

    L (0.70V) M (0.80V) L (0.70V) M (0.80V) H (0.88V) H (0.88V) Gen1 (2.5 GT/s per lane) Gen2 (5 GT/s per lane) Gen3 (8 GT/s per lane) PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 40: Port Descriptions

    Notes: See Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959) and the Xilinx Power Estimator (XPE), as described in Xilinx Power Estimator User Guide for Versal ACAP (UG1275), for information on requirements for supplying Overdrive voltages.
  • Page 41 When a TLP is transferred pcie1_m_axis_cq_tlast in a single beat, the core sets this signal in the first beat of the transfer. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 42 Non- Posted requests. The setting of pcie(n)_cq_np_req[1:0] does not need to be aligned with the packet transfers on the completer request interface. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 43 DW transfers and zero length transfers, these bits should be This field is valid in the first beat of a packet, that is, when sop and pcie(n)_m_axis_cq_tvalid are both High. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 44 Indicates PASID TLP is valid. 105:86 PASID Indicates PASID TLP prefix. Execute Requested Indicates Execute Requested to the user design. Privileged Mode Requested Indicates Privileged Mode Requested to the user design. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 45 The user application must keep the valid signal asserted during the transfer of a packet. The core paces the data transfer using the pcie(n)_s_axis_cc_tready signal. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 46 The parity bits can be permanently tied to 0 if parity check is not enabled in the core. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 47 The user application must keep the valid signal asserted during the transfer of a packet. The core paces the data transfer using the pcie(n)_s_axis_rq_tready signal. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 48 When PASID_CAP_ON is enabled then pcie(n)_s_axis_rq_tuser [84:62] pins are shared with cfg* ports. The following table provides more information. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 49 When the core is configured as an Endpoint, this error is also reported by the core to the Root Complex to which it is attached, using Advanced Error Reporting (AER). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 50 RC interface of the core. In the Width column, DW denotes the configured data bus width (64, 128, or 256 bits). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 51 The core keeps the valid pcie1_m_axis_rc_tvalid signal asserted during the transfer of a packet. The user application can pace the data transfer using the pcie(n)_m_axis_rc_tready signal. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 52 TLP at byte position 16 only if the previous TLP ended in one of the byte positions 0-15 in the same beat; that is, only if is_eof_0[0] is also set in the same beat. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 53 0 when the interface width is configured as 64 bits. 512-bit Interfaces This section provides the description for ports associated with the user interfaces of the core. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 54 If the user logic deasserts the ready signal when pcie(n)_m_axis_cq_tvalid is High, the core maintains the data on the bus and keeps the valid signal asserted until the user logic has asserted the ready signal. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 55 This count resets on user_reset and deassertion of user_lnk_up. When PASID_CAP_ON is enabled then pcie(n)_m_axis_cq_tuser[228:183] pins are shared with cfg* ports. The following table provides more information. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 56 For the special case of a zero-length memory write transaction defined by the PCI ExpressSpecifications, the byte_en bits are all 0 when the associated 1 Dword payload is being transferred. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 57 Offset of the last Dword of the second TLP ending in this beat. This output is valid when is_eop[1] is asserted. 95:92 is_eop1_ptr[3:0] The output is permanently set to 0 when straddle is disabled. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 58 When the straddle option is enabled, the core ignores the setting of this input, using instead the is_sop/ is_eop signals in the pcie(n)_s_axis_cc_tuser bus to determine the start and end of TLPs. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 59 This field is used by the core only when the straddle option is enabled. When straddle is disabled, the core uses tlast to determine the first beat of an incoming TLP. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 60 Offset of the last Dword of the second TLP ending in this beat. This output is valid when is_eop[1] is asserted. 15:12 is_eop1_ptr[3:0] This field is used by the core only when the straddle option is enabled. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 61 When the straddle option is enabled, the core ignores the setting of this input, using instead the is_sop/ is_eop signals in the s_axis_rq_tuser bus to determine the start and end of TLPs. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 62 The bit is encoded as follows: pcie1_rq_tag_vld1 • 0: No tag is provided on pcie(n)_rq_tag1 in this cycle. • 1: A tag is presented on pcie(n)_rq_tag1. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 63 This output is asserted by the core for one cycle when it has pcie1_rq_seq_num_vld1 placed valid data on pcie(n)_rq_seq_num1[5:0]. When PASID_CAP_ON is enabled then pcie(n)_s_axis_rq_tuser [182:137] pins are shared with cfg* ports. The following tables provides more details. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 64 The core samples this field in the first beat of a packet, when pcie(n)_s_axis_rq_tvalid and pcie(n)_s_axis_rq_tready are both High. When the requester request interface is configured in the Dword-alignment mode, these bits must always be set to 0. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 65 This output is valid when is_eop[0] is asserted. Offset of the last Dword of the second TLP ending in this 35:32 is_eop1_ptr[3:0] beat. This output is valid when is_eop[1] is asserted. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 66 These bits can be set to 0 if parity checking is disabled in the core. PASID TLP Valid 0 Indicates PASID TLP is valid for packet 0. pcie_posted_req_delivered is repurposed to pass PASID TLP VALID0 information from the user design. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 67 This output is used only when the straddle option is disabled. When the straddle option is enabled, the core sets this output permanently to 0. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 68 The 1 bits in this bus for the payload of a TLP are always contiguous. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 69 11: Byte lane 48 This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 70 This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 71 This output is used only when the straddle option is disabled. When the straddle option is enabled, the core sets this output permanently to 0. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 72 Non- Posted requests. The setting of pcie_cq_np_req[1:0] does not need to be aligned with the packet transfers on the completer request interface. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 73 For the special case of a zero-length memory write transaction defined by the PCI Express specifications, the byte_en bits are all 0 when the associated 1 Dword payload is transferred. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 74 High. last_be[12:8] is valid when pcie(n)_m_axis_cq_tvalid and is_eop[2] are both asserted High. last_be[15:12] is valid when pcie(n)_m_axis_cq_tvalid and is_eop[3] are both asserted High. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 75 • 11: Byte lane 96 171:170 is_sop3_ptr[1:0] Location of fourth SOP in the beat: • 00:Reserved • 01: Reserved • 10: Reserved • 11: Byte lane 96 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 76 240:197 reserved These bits are reserved. Odd parity for the 1024-bit transmit data. Bit i provides the 368:241 parity odd parity computed for byte i of pcie(n)_m_axis_cq_tdata. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 77 The pcie0_s_axis_cc_tvalid user application must keep the valid signal asserted during pcie1_s_axis_cc_tvalid the transfer of a packet. The core paces the data transfer using the pcie(n)_s_axis_cc_tready signal. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 78 11: Byte lane 96 Location of second SOP in the beat: • 00:Reserved • is_sop1_ptr[1:0] 01: Byte lane 32 • 10: Byte lane 64 • 11: Byte lane 96 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 79 Offset of the last Dword of the second TLP ending in this beat. This output is valid when is_eop[1] is asserted. This field is used by the core only when the straddle option is enabled. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 80 When the straddle option is enabled, the core ignores the setting of this input, using instead the is_sop/ is_eop signals in the s_axis_rq_tuser bus to determine the start and end of TLPs. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 81 The bit is encoded as follows: pcie1_rq_tag_vld1 • 0: No tag is provided on pcie(n)_rq_tag1 in this cycle. • 1: A tag is presented on pcie(n)_rq_tag1. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 82 This output is asserted by the core for one cycle when it has pcie1_rq_seq_num_vld0 placed valid data on pcie(n)_rq_seq_num0[5:0]. pcie0_rq_seq_num_vld1 This output is asserted by the core for one cycle when it has pcie1_rq_seq_num_vld1 placed valid data on pcie(n)_rq_seq_num1[5:0]. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 83 The core samples this field in the first beat of a packet, when pcie(n)_s_axis_rq_tvalid and pcie(n)_s_axis_rq_tready are both High. When the requester request interface is configured in the Dword-alignment mode, these bits must always be set to 0. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 84 • 11: Byte lane 96 59:58 is_sop3_ptr[1:0] Location of fourth SOP in the beat: • 00:Reserved • 01: Reserved • 10: Reserved • 11: Byte lane 96 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 85 When the core is configured as an Endpoint, this error is also reported by the core to the Root Complex it is attached to, using Advanced Error Reporting (AER). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 86 TLP being transferred. These signals are valid pcie1_m_axis_rc_tuser when pcie(n)_m_axis_rc_tvalid is High. The individual signals in this set are described in the following table. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 87 The 1 bits in this bus for the payload of a TLP are always contiguous. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 88 Use of this signal is optional for the client when the straddle option is not enabled, because a new TLP always starts in the beat following pcie(n)_m_axis_rc_tlast assertion. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 89 All other settings are reserved. This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 90 All other settings are reserved. This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 91 This output is used only when the straddle option is enabled on the RC interface. The output is permanently set to 0 when straddle is disabled. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 92 The table below defines the ports in the Clock and Reset interface of the core. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 93 Byte Enable pcie0_cfg_mgmt_byte_enable Byte enable for write data, where pcie1_cfg_mgmt_byte_enable pcie(n)_cfg_mgmt_byte_enable[0] corresponds to pcie(n)_cfg_mgmt_write_data[7:0], and so on. Read Enable pcie0_cfg_mgmt_read pcie1_cfg_mgmt_read Asserted for a read operation. Active-High. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 94 00b: No receivers detected pcie0_cfg_phy_link_status • pcie1_cfg_phy_link_status 01b: Link training in progress • 10b: Link up, DL initialization in progress • 11b: Link up, DL initialization completed PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 95 011b: 1024 bytes maximum Read Request size • 100b: 2048 bytes maximum Read Request size • 101b: 4096 bytes maximum Read Request size • Other values are reserved PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 96 0, and bits [5:3] capture that of function 1, and so on. The possible power states are: • 000: D0_uninitialized pcie0_cfg_function_power_state • 001: D0_active • 010: D1 • 100: D3_hot • Other values are reserved. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 97 Current power state of the PCI Express link, and is valid when cfg_phy_link_status[1:0] == 11b (DL Initialization is complete). • pcie0_cfg_link_power_state 00: L0 pcie1_cfg_link_power_state • 01: TX L0s • 10: L1 • 11: L2/3 Ready PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 98 10110b - AXI4ST CQ Poisoned Drop (Priority 19) • 10111b - User Signaled Internal Correctable Error (Priority 23) • 11000b - User Signaled Internal Uncorrectable Error (Priority 0) • 11001b - 11111b - Reserved PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 99 Encoding is listed below and valid when cfg_ltssm_state is indicating L0: • pcie0_cfg_tx_pm_state TX_NOT_IN_L0s = 0 pcie1_cfg_tx_pm_state • TX_L0s_ENTRY = 1 • TX_L0s_IDLE = 2 • TX_L0s_FTS = 3 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 100 Link Control register of the RP, bit 1 is reserved. For each bit, a value of 0 indicates an RCB of 64 bytes and a value of 1 indicates 128 bytes. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 101 8 clock cycles or less. The user logic must adjust the value on this output by the number of Non-Posted requests it sent in the previous clock cycles, if any. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 102 The various message types are listed in the previous table. Table 34: Message Type Encoding on Receive Message Interface cfg_msg_received_type[4:0] Message Type ERR_COR ERR_NONFATAL ERR_FATAL Assert_INTA Deassert_ INTA Assert_INTB Deassert_ INTB Assert_INTC Deassert_ INTC PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 103 Cycle 5: bits [7:0] of No-Snoop Latency Cycle 6: bits [15:8] of No-Snoop Latency Cycle 1: Requester ID, Bus Number Unlock Cycle 2: Requester ID, Device/Function Number PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 104 This signal is asserted together with pcie0_cfg_msg_transmit cfg_msg_transmit_type, which supplies the encoded pcie1_cfg_msg_transmit message type and cfg_msg_transmit_data, which supplies optional data associated with the message, until cfg_msg_transmit_done is asserted in response. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 105 The following table defines the ports in the Configuration Flow Control interface of the core. Note: The pcie0* signals map to PCIe Controller 0 and pcie1* signals map to PCIe Controller 1 in the port descriptions below. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 106 Completion Header Credit maintained by the core. The flow control information to bring out on this core is selected by the cfg_fc_sel[2:0] input. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 107 3'b100) is signaled as 8'h80, 12'h800 for header and data credits, respectively. For all other cfg_fc_sel selections, infinite credit is signaled as 8'h00, 12'h000, respectively, for header and data categories. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 108 The Configuration Control interface signals allow a broad range of information exchange between the user application and the core. The user application uses this interface to do the following: PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 109 (for PFs) or the pcie(n)_cfg_vf_power_state (for VFs) outputs of the core. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 110 The core continues to hold the pcie0_cfg_flr_in_process output High until the user sets the corresponding pcie(n)_cfg_flr_done input for the corresponding physical function to indicate the completion of the reset operation. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 111 Function pcie1_cfg_interrupt_pending #0. Each of these inputs is connected to the Interrupt Pending bits of the PCI Status Register of the corresponding Function. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 112 A one-cycle pulse on this output indicates that an pcie0_cfg_msi_fail MSI interrupt message was aborted before transmission on the link. The user logic must retransmit the MSI or MSI-X interrupt in this case. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 113 The SR-IOV core asserts this for 1 cycle when the pcie0_cfg_msi_mask_update MSI Mask Register of any enabled PFs has changed its value. The user can then read the new mask settings from the pcie(n)_cfg_msi_data outputs. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 114 Configuration Interrupt MSI-X Function Mask These outputs reflect the setting of the MSI-X Function pcie0_cfg_msix_mask Mask bits of the MSI-X Control Register of Physical Functions 0 – 3. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 115 1 when asserting pcie(n)_cfg_msix_int_vector. After asserting an interrupt, the user logic must wait for the pcie(n)_cfg_msix_sent or pcie0_cfg_msix_fail indication from the core before asserting a new interrupt. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 116 A one-cycle pulse on this output indicates that an MSI-X pcie0_cfg_msix_fail interrupt message was aborted before transmission on the link. The user logic must retransmit the MSI-X interrupt in this case. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 117 Configuration Interrupt MSI-X VF Mask pcie0_cfg_msix_vf_mask These outputs reflect the setting of the MSI-X Function pcie1_cfg_msix_vf_mask Mask bits of the MSI-X Control Register of Virtual Functions 0 – 251. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 118 Pending Bit to detect and service the interrupt. After each interrupt is serviced, the Pending Bit can be cleared through this interface. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 119 Configuration Extend interface of the core. Note: The pcie0* signals map to PCIe Controller 0 and pcie1* signals map to PCIe Controller 1 in the port descriptions below. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 120 Configuration Extend Function Number The 8-bit function number corresponding to the pcie0_cfg_ext_function_number configuration read or write request. The data is valid pcie1_cfg_ext_function_number when pcie(n)_cfg_ext_read_received or pcie(n)_cfg_ext_write_received is High. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 121 Configuration PASID Interface The Configuration PASID interface is used to determine the enablement of the PASID per function status by the software. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 122: Register Space

    (https:/ /www.pcisig.com/specifications). The Versal ® ACAP CPM Mode for PCIe supports Xilinx proprietary read/write configuration interfaces into this register space, and supports up to four Physical Functions (PFs) and 252 Virtual Functions (VFs). The PCI configuration space consists of the following primary parts.
  • Page 123 • MCAP Interface for Staged Configuration and Dynamic Function eXchange per PCI Express port • PASID Capability • Lane Margining at the Receiver Capability • Physical Layer 16 GT/s Capability • Physical Layer 32GT/s Capability for CPM5 only PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 124: Chapter 4: Designing With The Core

    Note: The following figures are high-level representations of the board layout. Ensure that coupling, termination, and details are correct when laying out a board. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 125 Figure 15: Open System Add-In Card Using 100 MHz Reference Clock PCI Express Add-In Card Device Endpoint 100 MHz with SSC Transceivers PCI Express Clock PCI Express Connector X22725-071620 Related Information Clock and Reset Interface PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 126: Resets

    Non-Posted request) from the user application for forwarding on the link. The two interfaces operate independently. That is, the core can transfer new requests over the completer request interface while receiving a Completion for a previous request. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 127 For messages and Configuration Requests, the address A is taken as 0. The starting lane number S is always 0 when the straddle option is not used, but can be 0 or 32 when straddle is enabled. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 128 The format of the following figure applies when the request TLP being transferred is a memory read/write request, an I/O read/write request, or an Atomic Operation request. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 129 Device/Function Requester ID BAR ID Req Type BAR Aperture X25571-072321 The format of the following figure is used for Vendor-Defined Messages (Type 0 or Type 1) only. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 130 + 12 Attr Msg Code Device/Function Dword Count Requester ID Message Req Type Routing X12216 For all other messages, the descriptor takes the format of the following figure. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 131 Otherwise, when CQ Poisoned packet handling is set to not discard, for transactions with payload, this bit is used to indicate a Poisoned request. This bit is reserved in all other cases. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 132 When 10-bit tags are enabled for the Completer, this field provides the bit [9] of the PCIe tag associated with the request. This bit is reserved in all other cases. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 133 Dword address of the data block being written into user memory is assumed to be (m*16 +3), for n = k*16 - 1 some integer m > 0. Its size is assumed to be n Dwords, for some , where k > 1. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 134 The asserted byte enable bits are always contiguous from the start of the payload, except when payload size is two Dwords or less. For writes of two Dwords or less, the 1s on byte_en are not be contiguous. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 135 0. Thus, the user logic can, in all cases, use the byte_en signals directly to enable the writing of the associated bytes into memory. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 136 In the case of a zero-length memory write, the core transfers a one-Dword payload with the byte_en bits all set to 0 for the payload bytes. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 137 Chapter 4: Designing with the Core Figure 22: Memory Write Transaction on the Completer Request Interface (128-bit Address Aligned Mode) PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 138 A zero-length memory read is sent on the completer request interface with the Dword count field in the descriptor set to 1 and the first and last byte enables set to 0. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 139 1, unless it is already 0. If pcie0_cq_np_req = 2'b00 and two Non-Posted requests are being delivered this ○ cycle, the credit count is decremented twice, unless it has already reached 0. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 140 TLP starting in the beat. The position of the first byte of the descriptor of this TLP is determined as follows: If the previous TLP ended before this beat, the first byte of the descriptor is in byte lane 0. ○ PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 141 32, it can only end at a byte lane in the range 47-127. Thus the offset is_eop1_ptr[4:0] can only take a value in the range 11-31. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 142 The third and fourth request TLPs are transferred completely in Beat 4, as REQ 3 has only a one-Dword payload and REQ 4 has no payload. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 143 The format of the completer completion descriptor is illustrated in the following figure. The individual fields of the completer request descriptor are described in the following table. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 144 Atomic Operations only. For these Completions, the user logic must Address Type copy the AT bits from the corresponding request descriptor into this field. This field must be set to 0 for all other Completions. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 145 PCI Requester ID associated with the request (copied by the user 63:48 Requester ID logic from the request). PCIe Tag associated with the request (copied by the user logic from 71:64 the request). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 146 Root Port mode (Downstream Port): • Must be set to the completer bus number. This is used in conjunction with Completer ID Enable bit in the descriptor. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 147 (as conveyed in bits [6:2] of the Lower Address field of the descriptor) is assumed to be (m*8+1), for some integer m. The size of the data block is assumed to be n Dwords, for some n = k*32+28, k > 0 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 148 The core treats the deassertion of s_axis_cc_tvalid during the packet transfer as an error, and nullifies the corresponding Completion TLP transmitted on the link to avoid data corruption. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 149 = k*16 - 1, for some k > 1 data block is assumed to be n Dwords, for some Figure 27: Transfer of a Normal Completion on the Completer Completion Interface (128-bit Address Aligned Mode) PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 150 The First Byte Enable bits first_be[15:0] in m_axis_cq_tuser. ○ The Last Byte Enable bits last_be[15:0] in m_axis_cq_tuser. ○ The four Dwords of the request descriptor received from the core with the request. ○ PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 151 • is_sop0_ptr[:0]: When is_sop[0] is set, this field must indicate the offset of the first Completion TLP starting in the current beat. Valid settings are 2'b00 (TLP starting at Dword 0) and 2'b10 (TLP starting at Dword 8). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 152 The third and fourth Completion TLPs are transferred completely in Beat 4, as COMPL 3 has only a one-Dword payload and COMPL 4 has no payload. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 153 Figure 29: Transfer of Completion TLPs on the Completer Completion Interface with the Straddle Option Enabled (1024-bit Interface) 1024-Bit Requester Interface This section describes the operation of the user-side Requester interface associated with the 1024-bit AXI4-Stream Interface. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 154 In Straddled case, addr_offset[3:2], first_be[7:4], and last_be[7:4] are used to indicate second TLP information while addr_offset[1:0], first_be[3:0], and last_be[3:0] are used to indicate the first TLP information on that data beat. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 155 PCIe Requester PCIe Request Interface is_sop1_ptr[1:0] Requester Interface is_eop[3:0] is_eop0_ptr[4:0] is_eop1_ptr[4:0] discontinue seq_num0[7:0] AXI4-Stream AXI4-Stream Slave Master seq_num1[7:0] parity[127:0] s_axis_rq_tuser[372:0] pcie_rq_tag[19:0] pcie_rq_tag_vld pcie_rq_seq_num[5:0] pcie_rq_seq_num_vld X16185-052522 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 156 The format of the following figure applies when the request TLP being transferred is a memory read/write request, an I/O read/write request, or an Atomic Operation request. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 157 Req Type Poisoned Request Requester ID Enable / T8 X25573-071821 The format of the following figure is used for Vendor-Defined Messages (Type 0 or Type 1) only. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 158 Requester ID Message Req Type Routing Force ECRC Requester ID Enable Poisoned Request X12211 For all other messages, the descriptor takes the format of the following figure. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 159 Data Poisoning feature of PCI Express. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 160 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 161 When the message is routed by ID (that is, when the Message Routing field is 010 binary), this field must be set to the Destination 15:0 Destination ID ID of the message. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 162 For the purpose of illustration, the size of the n = k*16 - 1, data block being written into user memory is assumed to be n Dwords, for some where k > 1 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 163 The user application must also set the bits in first_be[15:0] to indicate the valid bytes in the first Dword and the bits in last_be[15:0] to indicate the valid bytes in the last Dword of the payload. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 164 Dword, with both first_be[15:0] and last_be[15:0] set to all 0s. The user application must also communicate the offset of the first Dword of the payload of PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 165 In the case of I/O and Configuration write requests, the valid bytes in the one-Dword payload must be indicated using first_be[15:0]. For Atomic Operation requests, all bytes in the first and last Dwords are assumed valid. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 166 If a previous TLP is continuing in this beat, the first byte of this descriptor is in byte lane ○ 32. This is possible only when the previous TLP ends in the current beat, that is when is_eop[0] is also set. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 167 The third and fourth Completion TLPs are transferred completely in Beat 4, as REQ 3 has only a one-Dword payload and REQ 4 has no payload. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 168 Chapter 4: Designing with the Core Figure 38: Transfer of Request TLPs on the Requester Request Interface with the Straddle Option Enabled PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 169 The states of the signals pcie_rq_tag_vld and pcie_rq_tag must be interpreted as follows: • Assertion of pcie_rq_tag_vld0 in any cycle indicates that the core has placed an allocated tag on . PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 170 When the user logic presents Request 4 in clock cycle 4, it must adjust the available credit and available tag count by taking into account Requests 1, 2 and 3, presented PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 171 When the transaction has reached a stage in the internal transmit pipeline of the core where a PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 172 When straddle is not enabled, the core delivers each TLP on this interface as an AXI4- Stream packet. The packet starts with a 96-bit descriptor, followed by data in the case of Completions with a payload. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 173 The format of the requester completion descriptor is illustrated in the following figure. The individual fields of the requester completion descriptor are described in the following table. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 174 When the Completion delivered has an error, only bits [6:0] of the address should be considered valid. This is a byte-level address. For ATS translation requests, this field is reserved and implied to be zero. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 175 Completion Descriptor from the core with a matching tag field and the Request Completed bit set to 1. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 176 The timing diagrams in this section assume that the Completions are not straddled on the interface. The straddle feature is described Straddle Option for RC Interface. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 177 The user logic are optionally use the byte enable outputs byte_en[63:0] within the m_axi_rc_tuser bus to determine the valid bytes in the payload, in the cases of both contiguous and non-contiguous payloads. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 178 , for some k > 1. The timing diagrams in this section assume that the Completions are not straddled on the interface. The straddle feature is described in Straddle Option for RC Interface. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 179 , for some k > 0. The straddle option is not valid for 128-bit address aligned transfers, so the timing diagrams assume that the Completions are not straddled on the interface. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 180 The user application are optionally use the byte enable outputs byte_en[127:0] to determine the valid bytes in the payload. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 181 This straddle option is enabled during core customization in the Vivado ® IDE. The straddle option can be used only with the Dword-aligned mode. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 182 • is_sop3_ptr[1:0]: When is_sop[3] is set, this field indicates the offset of the fourth Completion TLP starting in the current beat. Its only valid setting is 2'b11 (TLP starting at Dword 12). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 183 TLP starting in Beat 1, whose starting position is indicated by is_sop0_ptr, and two TLPs ending, whose ending Dword positions are indicated by is_eop0_ptr and is_eop1_ptr, respectively. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 184 The ending offsets are indicated by is_eop0_ptr, is_eop1_ptr, is_eop2_ptr and is_eop3_ptr, respectively. Thus, all the four SOP and EOP pointers provide valid information in this beat. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 185 The user application must discard the entire packet when it has detected the signal discontinue asserted in the last beat of a packet. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 186 In this case, the Request Completed bit in the completion descriptor is also set. On receiving such a completion from the core, the user logic can discard the corresponding request. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 187 The valid payload byte in AXIS tdata indicated by the byte_en field in the AXIS tuser. For example, if byte_en[63:0]=0x0000_0000_0000_FFFF, then only lower 16 parity bits are valid. If byte_en[63:0] = 0xFFFF_FFFF_FFFF_FFFF, then all 64 parity bits are enabled. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 188: Chapter 5: Design Flow Steps

    Control, Interface and Processing System LogiCORE IP Product Guide (PG352). Configuring the CIPS IP Core 1. In the Vivado IDE, select IP Integrator → Create Block Design from the Flow Navigator, as shown in the following figure. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 189 3. Right-click on the block design canvas and from the context menu select Add IP. 4. Search for cips. 5. Double-click the Control, Interface, and Processing System IP core to customize it. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 190 6. In the Configuration Options pane, leave the settings as default or select appropriate options required for presets and click Next. Note: For information about the option presets, see Control, Interface and Processing System LogiCORE IP Product Guide (PG352). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 191 Chapter 5: Design Flow Steps 7. Click the CPM block to configure the core. The CPM Basic Configuration page displays. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 192 Note: PCIe Port 1 is available only if the lane width of PCIe Port 0 is less than or equal to X8. Note: PCIe Port 1 supports up to X8 when PCIe Port 0 is configured up to X8. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 193 11. If applicable, in the Configuration Options pane, expand CPM, and click PCIE Controller 1 Configuration to customize PCIe Port 1. 12. After configuring the PCIe controller, click OK to return to the Configure screen, as shown below. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 194 15. If the board will boot from serial NOR flash, select the a QSPI or OSPI option in Boot Mode options to enable programming of the flash on the board. Select the appropriate option based on availability to match the board schematic. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 195 Basic Mode Parameters The Basic mode parameters are explained in this section. Basic Tab The following figure shows the initial customization page, used to set the Basic mode parameters. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 196 AXI-ST frame Straddle is supported for CQ, CC, RQ and RC AXI-ST interfaces. Option to select CQ and CC AXI-ST frame straddle together and for RQ and RC interfaces. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 197 • Extended Tag Field: This field indicates the maximum supported size of the Tag field. The options are: • When selected, 8-bit Tag field support (256 tags) • When deselected, 5-bit Tag field support (32 tags) PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 198 No SSC (an asynchronous clock without SRIS support). Related Information Clocking PF IDs Tab The following figure shows the Identity Settings parameters. Figure 48: PF IDs Tab • PF0 ID Initial Values: PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 199 • Vendor ID: Identifies the manufacturer of the device or application. Valid identifiers are assigned by the PCI Special Interest Group to guarantee that each identifier is unique. The default value, 10EEh, is the Vendor ID for Xilinx. Enter a vendor identification number here. FFFFh is reserved.
  • Page 200 • Size: The available Size range depends on the PCIe Device/Port Type and the Type of BAR selected. The following table lists the available BAR size ranges. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 201 • Copy PF0: When set, the Copy PF0 option allows you to set all BARs settings of the remaining PFs to the same values as PF0. Applicable when there are more than one total Physical Function (PF). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 202 MSI-X Internal uses some of the MSI interface signals. • PF0/PF1/PF2/PF3 Multiple Message Capable: Selects the number of MSI vectors to request from the Root Complex. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 203 Capabilities Tab The Capabilities settings for Advanced mode (as shown in the following figure) contains two additional parameters to those for Basic mode and are described below. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 204 • MSI-X AXI4-Stream: In this mode user is expected to drive MSI-X interrupts on the AXI4- Stream interface. You can configure the MSI-X BARs. • None: No MSI-X is supported. The same MSI-X options are applicable when SRIOV capability is selected. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 205 MSI-X Table onto memory space. For a 64-bit Base Address Register, this indicates the lower DWORD. • MSIx Pending Bit Array (PBA) Settings: Defines the MSI-X Pending Bit Array (PBA) structure. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 206 (PF). PFx offset is always fixed. PF0 resides at offset 0, PF1 resides at offset 1, PF2 resides at offset 2, and PF3 resides at offset 3. A total of 252 virtual functions are available. They reside at the function number range 4 to 255. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 207 The SRIOV Base Address Registers (BARs) set the base address register space for the Endpoint configuration. Each BAR (0 through 5) configures the SR-IOV BAR aperture size and SR-IOV control attributes. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 208 • I/O: I/O BARs can only be 32-bit; the Prefetchable option does not apply to I/O BARs. I/O BARs are only enabled for a Legacy PCI Express Endpoint. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 209 • Copy PF0: When set, the Copy PF0 option allows you to set all BAR settings of the remaining PF groups to the same values as PF0 group. Applicable when there are more than one total Physical Function (PF). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 210 • None: No Extended Configuration space required. • Extended Small: PCI Express Extended space available from 0xE00 - 0xFFC. • Extended Large: PCI Express Extended space available from 0x600 - 0xFFC. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 211: Customizing And Generating The Cips Ip Core For Cpm5

    IP core to access the CPM PCIe controllers directly. For extended information about the CIPS IP core, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 212 5. Double-click the Control, Interface, and Processing System IP core to customize it. 6. In the Configuration Options pane, leave the settings as default or select appropriate options required for presets and click Next. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 213 Note: For information about the option presets, see Control, Interface and Processing System LogiCORE IP Product Guide (PG352). 7. Click the CPM block to configure the core. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 214 Chapter 5: Design Flow Steps The CPM Basic Configuration page displays. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 215 Note: PCIe Port 1 is available only if the lane width of PCIe Port 0 is less than or equal to X8. Note: PCIe Port 1 supports up to X8 when PCIe Port 0 is configured up to X8. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 216 Notice that the MIO pin selected in the PCIe reset is automatically connected to the PCIe reset I/O. In the figure below, MIO 38 is connected to the PCIe reset I/O. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 217 To set up the boot device, see the Versal ACAP Technical Reference Manual (AM011). If a serial NOR flash boot device will be used, the correct option must be selected to enable the correct MIOs. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 218 Basic Mode Parameters The Basic mode parameters are explained in this section. Basic Tab The following figure shows the initial customization page, used to set the Basic mode parameters. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 219 Wider lane width cores can train down to smaller lane widths if attached to a smaller lane-width device. • AXI-ST Interface Frequency: Enables you to specify the AXI-ST Interface frequency. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 220 The Capabilities settings are explained in this section as shown in the following figure. Figure 59: Capabilities Tab • Total Physical Functions: Enables you to select the number of physical functions. The number of physical functions supported is 16. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 221 • When this option is deselected, asynchronous clock in SRNS mode is supported. SRNS refers to a separate reference clock with No SSC (an asynchronous clock without SRIS support). PF IDs Tab The following figure shows the Identity Settings parameters. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 222 • Vendor ID: Identifies the manufacturer of the device or application. Valid identifiers are assigned by the PCI Special Interest Group to guarantee that each identifier is unique. The default value, 10EEh, is the Vendor ID for Xilinx. Enter a vendor identification number here. FFFFh is reserved.
  • Page 223 The PF BARs tab, shown in the following figure, sets the base address register space for the Endpoint configuration. Each BAR (0 through 5) configures the BAR Aperture Size and Control attributes of the physical function. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 224 • Size: The available Size range depends on the PCIe Device/Port Type and the Type of BAR selected. The following table lists the available BAR size ranges. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 225 • Copy PF0: When set, the Copy PF0 option allows you to set all BARs settings of the remaining PFs to the same values as PF0. Applicable when there are more than one total Physical Function (PF). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 226 • Enable MSI Per Vector Masking: Enables MSI Per Vector Masking Capability of all the Physical functions enabled. Note: Enabling this option for individual physical functions is not supported. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 227 The following parameters are visible on the Basic page when the Advanced mode is selected. Figure 63: Basic Tab, Advanced Mode • PCIe Link Debug: This enables the link debug option to be activated. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 228 • MSI-X Options: To enable MSI-X capabilities, select Advanced mode and then select the required options on the Capabilities tab. There are four options to choose from: PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 229 • MSI-X AXI4-Stream: In this mode user is expected to drive MSI-X interrupts on the AXI4- Stream interface. You can configure the MSI-X BARs. • None: No MSI-X is supported. The same MSI-X options are applicable when SRIOV capability is selected. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 230 MSI-X PBA. • PBA BAR Indicator: Indicates the Base Address Register in the Configuration Space used to map the function in the MSI-X PBA onto Memory Space. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 231 4096. When ARI is disabled, this field will be set to 1 to support 1 PF plus 7 VF non-ARI SR-IOV configurations only. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 232 The SRIOV Base Address Registers (BARs) set the base address register space for the Endpoint configuration. Each BAR (0 through 5) configures the SR-IOV BAR aperture size and SR-IOV control attributes. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 233 All SR-IOV BAR registers have these options: • Checkbox: Click the checkbox to enable the BAR; deselect the checkbox to disable the BAR. • Type: SR-IOV BARs can be either I/O or Memory. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 234 • Disabling Unused Resources: For best results, disable unused base address registers to conserve system resources. Disable base address register by deselecting unused BARs in the Customize IP dialog box. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 235 • None: No Extended Configuration space required. • Extended Small: PCI Express Extended space available from 0xE00 - 0xFFC. • Extended Large: PCI Express Extended space available from 0x600 - 0xFFC. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 236 Chapter 5: Design Flow Steps Interface Parameters The Interface Parameters tab enables you to enable/disable interfaces that are not required for your application. Figure 69: Interface Parameters Tab PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 237: Appendix A: Gt Selection And Pin Planning For Cpm4

    GT Quad Locations). When selecting GT Quads for the PHY IP based solution with Xilinx PCIe MAC, Xilinx recommends that you use the GT Quads most adjacent to the Xilinx PCIe macro. While this is not required, it improves place, route, and timing for the design.

  • Page 238: Cpm4 Gt Selection

    GT Quad that is in use by the CPM. GT Quads that are used or between GT Quads that are used by the CPM (for either PCIe or HSDP) cannot be shared with PL resources even if GTs within the quad are not in use. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 239 Subsequent lanes use the next available GTs moving vertically up the device as the lane number increments. CPM PCIe controller 1 lane7 connects to the top-most GT in the fourth GT Quad away from the CPM. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 240: Cpm4 Additional Considerations

    CPM4 or PL PCIe implementation. To route the PCIe reset from the CPM4 to the PL for use with a PL PCIe implementation the following option will need to be enabled under PS-PMC in the CIPS IP customization GUI. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 241 CIPS IP. If the CPM4 PCIe controller is enabled, the PCIe reset is used internal to the CPM4 and is not routed to the PL for connectivity to PL PCIe controllers. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 242: Cpm4 Gty Locations

    XCVM1402 Controller 0 GTY_QUAD_X0Y2 GTY_QUAD_X0Y0 GTY_QUAD_X0Y1 GTY_QUAD_X0Y0 GTY_QUAD_X0Y6 GTY_QUAD_X0Y5 XCVC1902, Controller 1 GTY_QUAD_X0Y5 XCVM1502, XCVM1802, GTY_QUAD_X0Y6 GTY_QUAD_X0Y4 GTY_QUAD_X0Y3 XCVC1702, Controller 0 GTY_QUAD_X0Y5 GTY_QUAD_X0Y3 XCVC1802, GTY_QUAD_X0Y4 XCVE1752 GTY_QUAD_X0Y3 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 243: Appendix B: Gt Selection And Pin Planning For Cpm5

    In other cases, such as system-board designs, embedded designs, and cabled interconnect, a local oscillator is typically required. RECOMMENDED: Although the CPM5 can support a variety of reference clock frequencies, Xilinx strongly recommends that designers selecting local oscillators use a 100 MHz reference clock as described in the PCI Express Card Electromechanical Specification unless there is a compelling reason to use a different supported frequency.

  • Page 244: General Guidance For Cpm5

    • Designers intending to migrate their design containing CPM5 from specifically identified engineering sample devices into other devices will require the guidance in all sections. General Guidance for CPM5 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 245 On PCB x4, x8 – Controller 1 [3:0] Controller 0 [0:7] Quad 104, REFCLK Quad 102, REFCLK x4, x4 x4 on PCB, x8 Not Quad 103, REFCLK Required PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 246 Controller 0 [1:0] or Controller 1 [1:0]. Similarly, for x1 board designs, connect to controller lane numbers Controller 0 [0] or Controller 1 [0]. Note that controller lane numbers might not be the same as physical GTYP channel numbers in a quad. Consult the provided placement table. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 247: Guidance For Cpm5 In Specifically Identified Engineering Sample Devices

    The GTYP lane and quad ordering above typically results in lanes crossing for x4 and x2 endpoint configurations. In this scenario Xilinx recommends physically reversing the lanes in the PCB design board traces. This will typically result in a bow-tie in the board PCB traces between the device and the PCIe edge connector.
  • Page 248 VP1502 VSVA2785 ES1 VP1502 VSVA3340 ES1 Versal Premium VP1552 VSVA2785 ES1 VP1702 VSVA3340 ES1 VP1802 LSVC4072 ES1 Versal HBM VH1522 VSVA3697 ES1 VH1542 VSVA3697 ES1 VH1582 VSVA3697 ES1 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 249 Controller 0 [1:0] or Controller 1 [1:0]. Similarly, for x1 board designs, connect to controller lane numbers Controller 0 [0] or Controller 1 [0]. Note that controller lane numbers might not be the same as physical GTYP channel numbers in a quad. Consult the provided placement table. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 250 IP will function. For x4 or narrower link widths, the feasibility of physically implementing lane reversal on the PCB is greater, therefore use this approach instead. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 251: Guidance For Cpm5 Migration From Specifically Identified Engineering Sample Devices

    For designs using x4 or narrower link widths, the lane ordering will be unchanged during migration. REFCLK placements also do not change. Consult the provided placement tables. For additional migration support, contact your Xilinx representative. RESET Considerations RESET placement options do not change.
  • Page 252 GT QUAD for Device Package Controller XCVP1202, XCVP1502, GTY_QUAD_X0Y5 GTY_QUAD_X0Y4 XCVP1552, XCVP1702, Controller 1 GTY_QUAD_X0Y4 XCVP1802, XCVH1522, GTY_QUAD_X0Y5 GTY_QUAD_X0Y3 GTY_QUAD_X0Y2 XCVH1542, Controller 0 GTY_QUAD_X0Y4 GTY_QUAD_X0Y2 XCVH1582, XCVH1782 GTY_QUAD_X0Y3 GTY_QUAD_X0Y2 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 253: Appendix C: Debugging

    Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available.

  • Page 254: Pcie Link Debug Enablement

    Xilinx Community Forums for this LogiCORE™ IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support if you do any of the following: • Implement the solution in devices that are not defined in the documentation.
  • Page 255 Debug Hub IP. To do so: a. Select PS-PMC →  Clock Configuration → Output Clocks → PMC Domain Clocks → PL Fabric Clocks selection enable a 100 MHz or similar output clock. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 256 Appendix C: Debugging b. Select PS-PMC → PL-PS Interfaces, and enable at least one PL reset in Number of PL Resets, and the M_AXI_LPD AXI master. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 257 Appendix C: Debugging 4. Add and configure the Processor System Reset IP. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 258 Appendix C: Debugging 5. Connect the IPs as shown in the following figures. This may need to be customized to fit with existing design connectivity. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 259 4. Select the PCIe Debug core in the Hardware window. You will see three main views that include the PCIe Debug Core Properties, PCIe Link LTSSM State Trace, and the PCIe Link LTSSM State Diagram with transitions. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 260 PCIe_0, and is inserted into the command. report_hw_pcie PCIe_0 This information helps determine where in the PCIe link-up process an issue occurred and can guide further debug of link related issues. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 261: Appendix D: Using The High Speed Debug Port Over Pcie For Design Debug

    PCIe to perform debug over a PCIe link rather than the standard JTAG debug interface. This is referred to as HSDP-over-PCIe and allows for Vivado ILA waveform capture, VIO debug control, and interaction with other Xilinx debug cores using the PCIe link as the communication channel.
  • Page 262 The HSDP-PCIe driver for Linux can be downloaded from GitHub. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 263 NOC to the fabric, which opens the possibility to use NOC NMU remapping to ensure the PCIe BAR size remains small and the device address map does not become fragmented. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 264 NOC. This means that NOC NMU address remapping cannot be employed, and the PCIe BAR must be large enough to reach the HSDP DMA or the master bridge itself must perform address translation. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 265 For CPM4, you can configure up to 6 AXI BARs, each with address translation, which allows for only 6 apertures. The address translation registers are programmed from the slave bridge interface by the Host PC through the master bridge. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 266 Figure 75: Block Diagram for HSDP-over-PCIe Management Mode Debug for CPM4 Figure 76: Address Map for HSDP-over-PCIe Management Mode Debug for CPM4 Figure 77: AXI BARs for HSDP-over-PCIe Management Mode Debug for CPM4 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 267 AXI BARs. The BDF table registers are located in the CPM register space, which are only accessible through the PMC interface by the Host PC from the master bridge. Figure 79: Block Diagram for HSDP-over-PCIe Management Mode Debug for CPM5 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 268: Implementing The Hsdp-Over-Pcie Example Design

    PC. To open the example design, perform the following options: 1. Launch Vivado. 2. Navigate to the set of example designs for selection • From the Quick Start menu, select Open Example Project, or PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 269 (.ltx) file used to specify debug information. Note: You can download or clone the GitHub repository to a local machine from https:/ /github.com/Xilinx/ XilinxCEDStore and set the following parameter so that local example designs are displayed in the Select Project template window.
  • Page 270 • If the debug host is remote, in the Hardware Server Settings window, modify the host name field to the remote server that is running hw_server and the port number field, if using the non-default port. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 271 6. The target device should be in the Hardware window and a probes file can now be specified in the Hardware Device Properties window after opening the hardware target and the debug core data is displayed PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 272 7. If using mgmt mode for debug, a user can connect to the debug host PC through the XSDB application and issue direct AXI reads and writes through the PMC PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 273: Appendix E: Limitations For Cpm4 And Cpm5

    PM D3 sequence is targeted to the EP ECAM space. • Workaround: In the case of PM D3, Xilinx recommends that any valid EP address be used except ECAM space in the pre-read before initiating PM D3 sequence.
  • Page 274 • Workaround: Ensure the software / application ignores the LABS bit as this is an informational bit and does not impact functionality. Note: For any application, Xilinx recommends that you make sure the link is quiesced and no transactions are pending before performing any link rate changes.

  • Page 275: Appendix F: Migrating

    VC1 Resource Control Register: VC Enable bit. pcie0_cfg_vc1_negotiation_pending VC1 Resource Status Register: VC Negotiation Pending bit. pcie0_cfg_pasid_enable[3:0] Per Function PASID Enable. pcie0_cfg_pasid_exec_permission_enable[3:0] Per Function PASID Exec Permission Enable. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 276 Now part of the register table. cfg_rev_id_pf0 Now part of the register table. cfg_rev_id_pf1 Now part of the register table. cfg_rev_id_pf2 Now part of the register table. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 277 (user logic). The pcie(n)_user_clk signal can have a frequency of 62.5, 125, or 250 MHz depending on the configured link speed and width. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 278 Physical Layer 16.0 GT/s Extended Capability Physical Layer 16.0 GT/s Extended Capability structure has been added for link speed of 16.0 GT/s with which Gen4 equalization status can be read. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 279: Migrating To Cpm5

    Versal CPM4. • TPH capability is not supported. Attributes A complete list of Versal attributes is available in the Versal ACAP Register Reference (AM012). Migrating to CPM5 PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 280 Please refer to port list for details. pcie0_cfg_wrreq_func_num[15:0] Please refer to port list for details. pcie0_cfg_wrreq_out_value[3:0] Please refer to port list for details. pcie0_cfg_perfunc_out[23:0] Please refer to port list for details. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 281 Now part of the register table. cfg_subsys_id_pf0 Now part of the register table. cfg_subsys_id_pf1 Now part of the register table. cfg_subsys_id_pf2 Now part of the register table. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 282 62.5, 125, or 250 MHz depending on the configured link speed and width. Reset Fundamental reset for the PCIe controller is driven by the I/O inside the PS which should be configured in CIPS. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 283 Link extension device (retimers) is supported to inter operate with CPM5 PCIe block for link speed of 16.0 GT/s and above. Flow Control Informational Select All combinations of cfg_fc_sel values are supported relative to UltraScale+, refer port description for more details. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...
  • Page 284 Equalization, form factor driver insertion loss adjustment, TX preset selection is not supported for Versal ACAP CPM5. • TPH capability is not supported. Attributes A complete list of Versal attributes is available in the Versal ACAP Register Reference (AM012). PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 285: Appendix G: Additional Resources And Legal Notices

    • On Windows, select Start → All Programs → Xilinx Design Tools → DocNav. • At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: •...

  • Page 286: Revision History

    Updated. 06/17/2022 Version 3.1 1024-bit Interfaces Added new section. 1024-Bit Completer Interface Added new section. 1024-Bit Requester Interface Added new section. Migrating to CPM5 Added new section. PG346 (v3.3) November 16, 2022 www.xilinx.com Send Feedback CPM Mode for PCI Express...

  • Page 287: Please Read: Important Legal Notices

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any PG346 (v3.3) November 16, 2022...
  • Page 288 IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for...

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