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Abov A96G166 User Manual

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16 MHz 8-bit MCU, 16 KB Flash Memory, 12-bit ADC,

Introduction

This user's manual targets application developers who use A96G166/A96A166/A96S166 for their
specific needs. It provides complete information of how to use A96G166/A96A166/A96S166 device.
Standard
functions
A96G166/A96A166/A96S166 are introduced in each chapter, while instruction set is in Appendix.
A96G166/A96A166/A96S166 is based on M8051 core, and provides standard features of 8051 such
as 8-bit ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-
bit data bus and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost-effective solutions:
16Kbytes of FLASH, 256bytes of IRAM, 512bytes of XRAM, general purpose I/O, basic interval timer,
watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 16-bit PWM output,
watch timer, buzzer driving port, USART, I2C, CRC, 12-bit A/D converter, on-chip POR, LVR, LVI, on-
chip oscillator and clock circuitry.
As a field proven best seller, A96G166/A96A166/A96S166 has been sold more than 3 billion units up
to now, and introduces rich features such as excellent noise immunity, code optimization, cost
effectiveness, and so on.

Reference document

A96G166/A96A166/A96S166 programming tools and manuals released by ABOV: They are
available at ABOV website, www.abovsemi.com.
SDK-51 User's guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel's 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentor website,
A96G166/A96A166/A96S166
3 Timers, USART, I2C, High Current Port
and
blocks
including
https://www.mentor.com/products/ip/peripheral/microcontroller/
Global Top Smart MCU Innovator
www.abovsemi.com
User's Manual
User's Manual Version 1.13
corresponding
register
information
of

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Summary of Contents for Abov A96G166

  • Page 1: Introduction

    USART, I2C, CRC, 12-bit A/D converter, on-chip POR, LVR, LVI, on- chip oscillator and clock circuitry. As a field proven best seller, A96G166/A96A166/A96S166 has been sold more than 3 billion units up to now, and introduces rich features such as excellent noise immunity, code optimization, cost effectiveness, and so on.

  • Page 2: Table Of Contents

    A96G166/A96A166/A96S166 User’s manual Contents Introduction.............................. 1 Reference document ..........................1 Description ........................... 12 Device overview ........................12 A96G166/A96A166/A96S166 block diagram ..............14 Pinouts and pin description ......................15 Pinouts ..........................15 Pin description........................20 Port structures ..........................24 Memory organization ........................26 Program memory ........................
  • Page 3 A96G166/A96A166/A96S166 User’s manual Contents Saving/restore general purpose registers ................61 6.10 Interrupt timing ........................62 6.11 Interrupt register overview ....................63 6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) ........... 63 6.11.2 Interrupt Priority Register (IP and IP1) ..............63 6.11.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1) ........
  • Page 4 Contents A96G166/A96A166/A96S166 User’s manual 12.1 Buzzer driver block diagram ..................... 115 12.2 Register map ........................116 12.3 Register description ......................116 12-bit ADC ..........................117 13.1 Conversion timing ......................117 13.2 Block diagram ........................118 13.3 ADC operation........................119 13.4 Register map ........................120 13.5 Register description ......................
  • Page 5 A96G166/A96A166/A96S166 User’s manual Contents 16.2 Register map ........................163 16.3 Register description ......................164 16.1 Polynomial ......................... 166 Power down operation ....................... 167 17.1 Peripheral operation in IDLE/ STOP mode ............... 167 17.2 IDLE mode ........................168 17.3 STOP mode ........................169 17.4 Released operation of STOP mode ..................
  • Page 6 Contents A96G166/A96A166/A96S166 User’s manual 20.19 Main oscillation stabilization characteristics ..............217 20.20 Sub-oscillation characteristics ................... 217 20.21 Operating voltage range ....................218 20.22 Recommended circuit and layout..................218 20.23 Typical characteristics ....................... 219 Package information ........................222 21.1 16 SOPN package information ..................222 21.2 20 TSSOP package information ..................
  • Page 7 Figure 4 A96A166 20SOP Pin Assignment ................... 16 Figure 5. A96S166 20TSSOP Pin Assignment ..................17 Figure 6. A96G166 20 QFN Pin Assignment ..................18 Figure 7. A96G166 28SOP Pin Assignment ..................19 Figure 8. A96G166 32 LQFP Pin Assignment ..................19 Figure 9.
  • Page 8 List of figures A96G166/A96A166/A96S166 User’s manual Figure 49. 16-bit Timer/Counter Mode of Timer 2 ................106 Figure 50. 16-bit Timer/Counter Mode Operation Example ..............107 Figure 51. 16-bit Capture Mode of Timer 2 ..................108 Figure 52. 16-bit Capture Mode Operation Example ................109 Figure 53.
  • Page 9 Figure 140. Start and Stop Condition ....................234 Figure 141. Acknowledge on Serial Bus ..................... 235 Figure 142. Clock Synchronization during Wait Procedure ..............235 Figure 143. Connection of Transmission .................... 236 Figure 144. A96G166/A96A166/A96S166 Device Numbering Nomenclature ........238...
  • Page 10 A96G166/A96A166/A96S166 User’s manual List of tables Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts ......... 12 Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts (continued) ....13 Table 2. Normal Pin Description ......................20 Table 2. Normal Pin Description (continued)..................21 Table 2.
  • Page 11 Table 62. Main Oscillation Stabilization Characteristics ..............217 Table 63. Sub Oscillation Stabilization Characteristics ............... 217 Table 64. Pins for Flash Programming ....................230 Table 65. OCD Features ........................232 Table 66. A96G166/A96A166/A96S166 Device Ordering Information ..........237 Table 67. Instruction Table ........................239...

  • Page 12: Description

    1. Description A96G166/A96A166/A96S166 User’s manual 1 Description A96G166/A96A166/A96S166 is an advanced CMOS 8-bit microcontroller with 16Kbytes of FLASH. This is a powerful microcontroller which provides a highly flexible and cost-effective solution to many embedded control applications. Device overview In this section, features of A96G166/A96A166/A96S166 and peripheral counts are introduced.

  • Page 13: Table 1. A96G166/A96A166/A96S166 Device Features And Peripheral Counts (Continued)

    A96G166/A96A166/A96S166 User’s manual 1. Description Table 1. A96G166/A96A166/A96S166 Device Features and Peripheral Counts (continued) Peripherals Description General Purpose I/O (GPIO)  Normal I/O: Max 30 ports  High sink current port: LED 8 x COM Reset Power Reset release level: 1.32V reset ...

  • Page 14: A96G166/A96A166/A96S166 Block Diagram

    1. Description A96G166/A96A166/A96S166 User’s manual A96G166/A96A166/A96S166 block diagram In this section, A96G166/A96A166/A96S166 device with peripherals are described in a block diagram. Flash 16KB CORE XRAM M8051 512B IRAM 256B General purpose I/O In-system programming 30 ports normal I/O Power control...

  • Page 15: Pinouts And Pin Description

    A96G166/A96A166/A96S166 User’s manual 2. Pinouts and pin description 2 Pinouts and pin description In this chapter, A96G166/A96A166/A96S166 device pinouts and pin descriptions are introduced. Pinouts P00/AN0/DSDA P37/XOUT P36/XIN P01/AN1/DSCL A96G166AE P32/(T0O)/(PWM0O)/RESETB P06/AN6/EINT4/(T2O)/(PWM2O) (16SOPN) P26/EC0 P12/AN9/EINT11/T1O/PWM1O/LED0 P25/SCL/(RXD1) P13/AN10/EINT12/T2O/PWM2O/LED1 P24/SDA/(TXD1) P14/AN11/RXD0 P22/EINT9/XCK1/LED6...

  • Page 16: Figure 3. A96G166 20Tssop/20Sop Pin Assignment

    The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P04-P06, P14-P17, P20, P23, P26 and P33-P34 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 20-pin package is used. Figure 3. A96G166 20TSSOP/20SOP Pin Assignment P00/AN0/DSDA P37/XOUT...

  • Page 17: Figure 5. A96S166 20Tssop Pin Assignment

    A96G166/A96A166/A96S166 User’s manual 2. Pinouts and pin description P00/AN0/DSDA P37/XOUT P36/XIN P01/AN1/DSCL P02/AN2/EINT0 P35/RESETB/EINT10/T0O/PWM0O P32/(T0O)/(PWM0O) A96S166FR P03/AN3/EINT1/(T1O)/(PWM1O) (20TSSOP) P31/(EC0)/RXD1/(SCL) P10/AN7/EINT5/PWM1OB P30/(EC2)/TXD1/(SDA) P11/AN8/EINT6/EC1/BUZO P25/SCL/(RXD1) P12/AN9/EINT11/T1O/PWM1O/LED0 P24/SDA/(TXD1) P13/AN10/EINT12/T2O/PWM2O/LED1 P22/EINT9/XCK1/LED6 P21/EINT8/SS1/LED5 NOTES: The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P04-P06, P14-P17, P20, P23, P26 and P33-P34 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 20-pin package is used.

  • Page 18: Figure 6. A96G166 20 Qfn Pin Assignment

    The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P04-P06, P17, P20-P22 and P26 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 24-pin package is used. Figure 6. A96G166 20 QFN Pin Assignment...

  • Page 19: Figure 7. A96G166 28Sop Pin Assignment

    The P04-P06 and P26 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 28-pin package is used. Figure 7. A96G166 28SOP Pin Assignment A96G166KN (32-LQFP) NOTE: The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. Figure 8. A96G166 32 LQFP Pin Assignment...

  • Page 20: Pin Description

    2. Pinouts and pin description A96G166/A96A166/A96S166 User’s manual Pin description Table 2. Normal Pin Description Pin no. PIN name Description Remark LQFP TSSOP SOPN P00* IOUS Port 0 bit 0 Input/output (19) ADC input ch-0 DSDA OCD debugger data Pull-up...

  • Page 21: Table 2. Normal Pin Description (Continued)

    A96G166/A96A166/A96S166 User’s manual 2. Pinouts and pin description Table 2. Normal Pin Description (continued) Pin no. PIN name I/O(1) Description Remark LQFP TSSOP SOPN P12* IOUS Port 1 bit 2 Input/output (13) ADC input ch-9 EINT11 External interrupt input ch-11...

  • Page 22: Table 2. Normal Pin Description (Continued)

    The P04–P06, P14-P17, P20, P23, P26 and P33-P34 are not in the 20-pin package. The P02-P05, P10-P11, P16-P17, P20-P21, P23, P30-P31 and P33-P35 are not in the 16-pin package. The P32/RESETB (A96G166) pin is configured as one of the P32 and RESETB pin by the “CONFIGURE OPTION.” (P35/RESETB : A96S166) If the P00/AN0/DSDA and P01/AN1/DSCL pins are connected to the programmer during power-on reset, the pins are automatically configured as In-system programming pins.
  • Page 23 A96G166/A96A166/A96S166 User’s manual 2. Pinouts and pin description The P00/AN0/DSDA and P01/AN1/DSCL pins are configured as inputs with internal pull-up resistor only during the reset or power-on reset. The P36/XIN, P37/XOUT, P33/SXOUT, and P34/SXIN pins are configured as a function pin by software control.

  • Page 24: Port Structures

    3. Port structures A96G166/A96A166/A96S166 User’s manual 3 Port structures In this chapter, two port structures are introduced in Figure 9 and Figure 10 regarding general purpose I/O port and external interrupt I/O port respectively. Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V)

  • Page 25: Figure 10. External Interrupt I/O Port

    A96G166/A96A166/A96S166 User’s manual 3. Port structures LevelShift (1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE DIRECTION REGISTER SUB-FUNC DIRECTION R(400Ω) EXTERNAL INTERRUPT POLARITY INTERRUPT ENABLE EDGE FLAG CLEAR PORTx INPUT...

  • Page 26: Memory Organization

    External data memory (XRAM) is 512bytes. Program memory A 16-bit program counter is capable of addressing up to 64Kbytes, and A96G166/A96A166/A96S166 has just 16Kbytes program memory space. Figure 11 shows a map of the lower part of the program memory.

  • Page 27: Data Memory

    A96G166/A96A166/A96S166 User’s manual 4. Memory organization NOTE: The 16Kbytes includes the Interrupt Vector Region Figure 11. Program Memory Map Data memory Internal data memory space is divided into three blocks, which are generally referred to as lower 128bytes, upper 128bytes, and SFR space. Internal data memory addresses are always one byte wide, which implies an address space of 256bytes.

  • Page 28: Figure 12. Data Memory Map

    4. Memory organization A96G166/A96A166/A96S166 User’s manual Figure 12. Data Memory Map 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60...

  • Page 29: External Data Memory

    A96G166/A96A166/A96S166 User’s manual 4. Memory organization External data memory A96G166/A96A166/A96S166 has 512bytes of XRAM and XSFR. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. 107FH Extended Special Function Registers...

  • Page 30: Sfr Map

    4. Memory organization A96G166/A96A166/A96S166 User’s manual SFR map 4.4.1 SFR map summary Table 3. SFR Map Summary ― Reserved M8051 compatible 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 0F8H – – – U0BAUD U0DATA – – 0F0H U1CTRL1 U1CTRL2 U1CTRL3 –...

  • Page 31: Table 4. Xsfr Map Summary

    A96G166/A96A166/A96S166 User’s manual 4. Memory organization Table 4. XSFR Map Summary 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 1078H – CRC_ADDR CRC_ADDR CRC_ADDR CRC_ADDR CRC_ADDR CRC_ADDR – _START_H _START_M _START_L _END_H _END_M _END_L 1070H CRC_CON – CRC_H CRC_L CRC_MNT CRC_MNT –...

  • Page 32: Sfr Map

    4. Memory organization A96G166/A96A166/A96S166 User’s manual 4.4.2 SFR map Table 5. SFR Map Address Function Symbol @Reset P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1...

  • Page 33: Table 5. Sfr Map (Continued)

    A96G166/A96A166/A96S166 User’s manual 4. Memory organization Table 5. SFR Map (continued) Address Function Symbol @Reset P0 Direction Register P0IO Extended Operation Register – – – – External Interrupt Polarity 2 Register EIPOL2 External Interrupt Polarity 0 Low Register EIPOL0L External Interrupt Polarity 0 High Register...

  • Page 34: Table 5. Sfr Map (Continued)

    4. Memory organization A96G166/A96A166/A96S166 User’s manual Table 5. SFR Map (continued) Address Function Symbol @Reset External Interrupt Flag 0 Register EIFLAG0 Timer 2 Control Low Register T2CRL – – Timer 2 Control High Register T2CRH – – – – Timer 2 A Data Low Register...

  • Page 35: Table 5. Sfr Map (Continued)

    A96G166/A96A166/A96S166 User’s manual 4. Memory organization Table 5. SFR Map (continued) Address Function Symbol @Reset B Register USART1 Control Register 1 U1CTRL1 USART1 Control Register 2 U1CTRL2 USART1 Control Register 3 U1CTRL3 – USART1 Baud Rate Generation Register U1BAUD USART1 Data Register...

  • Page 36: Table 6. Xsfr Map

    4. Memory organization A96G166/A96A166/A96S166 User’s manual Table 6. XSFR Map Address Function Symbol @Reset 1010H Watch Dog Timer Clear Register WDTC 1011H Watch Dog Timer Status Register WDTSR 1012H Watch Dog Timer Count H Register WDTCNTH 1013H Watch Dog Timer Count L Register...

  • Page 37: Compiler Compatible Sfr

    A96G166/A96A166/A96S166 User’s manual 4. Memory organization 4.4.3 Compiler compatible SFR ACC (Accumulator Register): E0H Initial value: 00H Accumulator B (B Register): F0H Initial value: 00H B Register SP (Stack Pointer): 81H Initial value: 07H Stack Pointer DPL (Data Pointer Register Low): 82H...
  • Page 38 4. Memory organization A96G166/A96A166/A96S166 User’s manual DPH1 (Data Pointer Register High 1): 85H DPH1 Initial value: 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register): D0H Initial value: 00H Carry Flag Auxiliary Carry Flag General Purpose User-Definable Flag...

  • Page 39: 5 I/O Ports

    5. I/O ports 5 I/O ports A96G166/A96A166/A96S166 has ten groups of I/O ports (P0 to P2). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. P0 includes a function that can generate interrupt signals according to state of a pin.

  • Page 40: Register Map

    5. I/O ports A96G166/A96A166/A96S166 User’s manual 5.1.7 Register Map Table 7. Port Register Map Name Address Direction Default Description P0 Data Register P0IO P0 Direction Register P0PU P0 Pull-up Resistor Selection Register P0OD P0 Open-drain Selection Register P0DB P0 De-bounce Enable Register...

  • Page 41: P0 Port

    A96G166/A96A166/A96S166 User’s manual 5. I/O ports P0 port 5.2.1 P0 port description P0 is an 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open- drain selection register (P0OD).
  • Page 42 5. I/O ports A96G166/A96A166/A96S166 User’s manual P0OD (P0 Open-drain Selection Register): 91H – P06OD P05OD P04OD P03OD P02OD P01OD P00OD – Initial value: 00H P0OD[6:0] Configure Open-drain of P0 Port Push-pull output Open-drain output P0DB (P0 De-bounce Enable Register): DEH...
  • Page 43 A96G166/A96A166/A96S166 User’s manual 5. I/O ports P0FSRH (Port 0 Function Selection High Register): D3H – – – – P0FSRH3 P0FSRH2 P0FSRH1 P0FSRH0 – – – – Initial value: 00H P0FSRH[3:2] P06 Function Select P0FSRH3 P0FSRH2 Description I/O Port (EINT4 function possible when...

  • Page 44: P1 Port

    5. I/O ports A96G166/A96A166/A96S166 User’s manual P1 port 5.3.1 P1 port description P1 is an 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P1DB), P1 pull-up resistor selection register (P1PU), andP1 open- drain selection register (P1OD).
  • Page 45 A96G166/A96A166/A96S166 User’s manual 5. I/O ports P1OD (P1 Open-drain Selection Register): 92H P17OD P16OD P15OD P14OD P13OD P12OD P11OD P10OD Initial value: 00H P1OD[7:0] Configure Open-drain of P1 Port Push-pull output Open-drain output P12DB (P1/P2 De-bounce Enable Register): DFH P23DB...
  • Page 46 5. I/O ports A96G166/A96A166/A96S166 User’s manual P1FSRH (Port 1 Function Selection High Register): D5H P1FSRH7 P1FSRH6 P1FSRH5 P1FSRH4 P1FSRH3 P1FSRH2 P1FSRH1 P1FSRH0 Initial value: 00H P1FSRH[7:6] P17 Function Select P1FSRH7 P1FSRH6 Description I/O Port (EC2 function possible when input) SS0 Function...
  • Page 47 A96G166/A96A166/A96S166 User’s manual 5. I/O ports P1FSRL (Port 1 Function Selection Low Register): D4H P1FSRL7 P1FSRL6 P1FSRL5 P1FSRL4 P1FSRL3 P1FSRL2 P1FSRL1 P1FSRL0 Initial value: 00H P1FSRL[7:6] P13 Function Select P1FSRL7 P1FSRL6 Description I/O Port (EINT12 function possible when input) T2O/PWM2O Function...

  • Page 48: P2 Port

    5. I/O ports A96G166/A96A166/A96S166 User’s manual P2 port 5.4.1 P2 port description P2 is an 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) andP2 open-drain selection register (P2OD).Refer to the port function selection registers for the P2 function selection.
  • Page 49 A96G166/A96A166/A96S166 User’s manual 5. I/O ports P2FSRL (Port 2 Function Selection Low Register): D6H P2FSRL5 P2FSRL4 P2FSRL3 P2FSRL2 P2FSRL1 P2FSRL0 Initial value: 00H P2FSRL5 P23 Function Select I/O Port (EINTA function possible when input) LED7 Function P2FSRL[4:3] P22 Function Select...

  • Page 50: P3 Port

    5. I/O ports A96G166/A96A166/A96S166 User’s manual P3 port 5.5.1 P3 port description P3 is an 8-bit I/O port. P3 control registers consist of P3 data register (P3), P3 direction register (P3IO) and P3 pull-up resistor selection register (P3PU). Refer to the port function selection registers for the P3 function selection.
  • Page 51 A96G166/A96A166/A96S166 User’s manual 5. I/O ports P3FSRH (Port 3 Function Selection High Register): 9BH P3FSRH2 P3FSRH1 P3FSRH0 Initial value: 00H P3FSRH2 P37 Function select I/O Port XOUT Function P3FSRH1 P36 Function Select I/O Port XIN Function P3FSRH0 P35 Function select...

  • Page 52: Interrupt Controller

    6. Interrupt controller A96G166/A96A166/A96S166 User’s manual 6 Interrupt controller A96G166/A96A166/A96S166 supports up to 21 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. In addition, they have four levels of priority assigned to themselves.

  • Page 53: Figure 15. Interrupt Group Priority Level

    A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller Interrupt Highest Lowest Group 0 (Bit0) Interrupt 0 Interrupt 6 Interrupt 12 Interrupt 18 Highest 1 (Bit1) Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 2 (Bit2) Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20...

  • Page 54: External Interrupt

    6. Interrupt controller A96G166/A96A166/A96S166 User’s manual External interrupt EINT0, EINT1, EINT2, EINT3, EINT4, EINT5, EINT6, EINT7, EINT8, EINT9, EINTA, EINT10, EINT11 and EINT12 pins receive various interrupt requests depending on the external interrupt polarity register (EIPOL) as shown in Figure 16. Each external interrupt source has enable/disable bits.

  • Page 55: Block Diagram

    A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller Block diagram EIPOL1 EI FLAG1.4 FLAG10 EINT10 EI FLAG1.5 Priority High FLAG11 EINT11 EI FLAG1.6 FLAG12 EINT12 EIPOL0H/L EI FLAG0.0 FLAG0 EINT0 EI FLAG0.1 FLAG1 EINT1 EI FLAG0.2 FLAG2 EINT2 EI FLAG0.3 FLAG3 EINT3 EI FLAG0.4...

  • Page 56: Interrupt Vector Table

    A96G166/A96A166/A96S166 User’s manual Interrupt vector table Interrupt controller of A96G166/A96A166/A96S166 supports 21 interrupt sources as shown in Table 8. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.

  • Page 57: Interrupt Sequence

    A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller And it remains ‘1’ until CPU accepts interrupt. If the interrupt is served, the interrupt request flag will be cleared automatically. Interrupt sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction.

  • Page 58: Figure 18. Interrupt Sequence Flow

    6. Interrupt controller A96G166/A96A166/A96S166 User’s manual IE.EA Flag 0 Program Counter low Byte SP  SP + 1 M (SP)  (PCL) Saves PC value in order to continue process again after executing ISR Program Counter high Byte SP  SP + 1 M (SP) ...

  • Page 59: Effective Timing After Controlling Interrupt Bit

    A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller Effective timing after controlling interrupt bit Case A in Figure 19 shows the effective time after controlling the Interrupt Enable Registers (IE, IE1, IE2, and IE3). Interrupt Enable Register command After executing IE set/clear, enable register is effective.

  • Page 60: Multi-Interrupt

    6. Interrupt controller A96G166/A96A166/A96S166 User’s manual Multi-interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software.

  • Page 61: Interrupt Enable Accept Timing

    A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller Interrupt enable accept timing System Max. 4 Machine Cycle 4 Machine Cycle Clock Interrupt goes Interrupt Interrupt Processing active latched Interrupt Routine : LCALL & LJMP Figure 22. Interrupt Response Timing Diagram Interrupt service routine address...

  • Page 62: Interrupt Timing

    6. Interrupt controller A96G166/A96A166/A96S166 User’s manual 6.10 Interrupt timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-bit interrupt Vector INT_VEC PROGA NOTE: Variable x and n of a command cycle CLPx imply the followings: x ➔...

  • Page 63: Interrupt Register Overview

    A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller 6.11 Interrupt register overview 6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits. Total 21 peripherals are able to control interrupt.

  • Page 64: Register Map

    6. Interrupt controller A96G166/A96A166/A96S166 User’s manual 6.11.5 Register map Table 9. Interrupt Register Map Name Address Direction Default Description Interrupt Enable Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Priority Register Interrupt Priority Register 1...

  • Page 65: Interrupt Register Description

    A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller 6.11.6 Interrupt register description IE (Interrupt Enable Register): A8H – INT5E – – INT2E INT1E INT0E – – – Initial value: 00H Enable or Disable All Interrupt bits All Interrupt disable All Interrupt enable...
  • Page 66 6. Interrupt controller A96G166/A96A166/A96S166 User’s manual IE2 (Interrupt Enable Register 2): AAH –- – – INT17E INT15E INT14E INT13E INT12E – – – Initial value: 00H INT17E Enable or Disable External Interrupt 7 ~ A (EINT7 ~ EINTA) Disable Enable...
  • Page 67 A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller IP1 (Interrupt Priority Register 1): F8H – – IP15 IP14 IP13 IP12 IP11 IP10 – – Initial value: 00H IP[5:0], IP1[5:0] Select Interrupt Group Priority IP1x Description level 0 (lowest) level 1 level 2...
  • Page 68 6. Interrupt controller A96G166/A96A166/A96S166 User’s manual EIPOL0H (External Interrupt Polarity 0High Register): A5H – POL6 POL5 POL4 – – Initial value: 00H EIPOL0H[7:0] External interrupt (EINT6, EINT5, EINT4) polarity selection POLn[1:0] Description No interrupt at any edge Interrupt on rising edge...
  • Page 69 A96G166/A96A166/A96S166 User’s manual 6. Interrupt controller EIPOL2 (External Interrupt Polarity 2 Register): A3H POLA POL9 POL8 POL7 Initial value: 00H EIPOL2[7:0] External interrupt (EINTA, EINT9, EINT8, EINT7) polarity selection POLn[1:0] Description No interrupt at any edge Interrupt on rising edge...

  • Page 70: Clock Generator

    7. Clock generator A96G166/A96A166/A96S166 User’s manual 7 Clock generator As shown in Figure 26, a clock generator produces basic clock pulses which provide a system clock for CPU and peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock can operate easily by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively.

  • Page 71: Clock Generator Block Diagram

    A96G166/A96A166/A96S166 User’s manual 7. Clock generator Clock generator block diagram In this section, a clock generator of A96G166/A96A166/A96S166 is described in a block diagram. Main OSC XOUT STOP Mode IRCS[2:0] XCLKE System SCLK Clock Gen. (Core, System, Clock Per ipheral)

  • Page 72: Register Description

    7. Clock generator A96G166/A96A166/A96S166 User’s manual Register description SCCR (System and Clock Control Register): 8AH – – – – – – SCLK1 SCLK0 – – – – – – Initial value: 00H SCLK [1:0] System Clock Selection Bit SCLK1 SCLK0...
  • Page 73 A96G166/A96A166/A96S166 User’s manual 7. Clock generator XTFLSR (Main Crystal OSC Filter Selection Register): 1038H NFSEL1 NFSEL0 MX_FIL_DIS MX_ISEL1 MX_ISEL0 SUB_FIL_DIS SUB_ISEL1 SUB_ISEL0 Initial value: 00H NFSEL[1:0] Noise Filter Selective Option NFSEL1 NFSEL0 Description 18ns (Default, 12MHz) 22ns (12MHz) 26ns (8MHz)

  • Page 74: Basic Interval Timer

    On exiting Stop mode, BIT gives a stable clock generation time  As a timer, BIT generates a timer interrupt.  BIT block diagram In this section, basic interval timer of A96G166/A96A166/A96S166 is described in a block diagram. 1/4096 8-bit up-counter 1/1024 1/128...

  • Page 75: Bit Register Description

    A96G166/A96A166/A96S166 User’s manual 8. Basic Interval Timer BIT register description BITCNT (Basic Interval Timer Counter Register): 8CH BITCNT7 BITCNT6 BITCNT5 BITCNT4 BITCNT3 BITCNT2 BITCNT1 BITCNT0 Initial value: 00H BITCNT[7:0] BIT Counter BITCR (Basic Interval Timer Control Register): 8BH BITIFR BITCK2...

  • Page 76: Watchdog Timer

    9. Watchdog timer A96G166/A96A166/A96S166 User’s manual 9 Watchdog timer Watchdog timer rapidly detects malfunction of the CPU such as endless looping caused by noise, and returns the CPU to the normal state. The watchdog timer signal for malfunction detection can be used for either a CPU reset or an interrupt request.

  • Page 77: Setting Window Open Period Of Watchdog Timer

    A96G166/A96A166/A96S166 User’s manual 9. Watchdog timer Setting window open period of watchdog timer 1. WDT window open period is selected as 50%. Counting Overflow Start time Window close(50%) Window open(50%) Counter clear & Start again, Watchdog reset is occurred, if “96H” is written to WDTC.

  • Page 78: Wdt Block Diagram

    9. Watchdog timer A96G166/A96A166/A96S166 User’s manual Table 12. Setting of window open period Setting of window open period Window close period Window open period 50%, WINDOW[1:0]=00b & WDTPDON = 1 75%, WINDOW[1:0]=01b & WDTPDON = 1 100%, WINDOW[1:0]=10b & WDTPDON = 1 WDTCNT = “0000H”...

  • Page 79: Register Description

    A96G166/A96A166/A96S166 User’s manual 9. Watchdog timer Register description WDTCNTH (Watch Dog Timer Counter High Register): 1012H WDTCNTH 7 WDTCNTH 6 WDTCNTH 5 WDTCNTH 4 WDTCNTH 3 WDTCNTH 2 WDTCNTH 1 WDTCNTH 0 Initial value: 00H WDTCNTH[7:0] WDT Counter High WDTCNTL (Watch Dog Timer Counter Low Register): 1013H...
  • Page 80 9. Watchdog timer A96G166/A96A166/A96S166 User’s manual WDTCR (Watch Dog Timer Control Register): 8DH WDTEN WDTRTI WDTPDON WINDOW1 WINDOW0 WDOVF2 WDOVF1 WDOVF0 Initial value: 07H WDTEN Control WDT Operation Disable (WDTRC Stop) Enable WDTRTI 3/4 Interval interrupt Disable (WDT overflow reset used)

  • Page 81: 10 Watch Timer

    WT clear, set interval value at write time, and read 7-bit WT counter value at read time. 10.1 WT block diagram In this section, the WT of A96G166/A96A166/A96S166 is described in a block diagram. S UB Match Clear...

  • Page 82: Register Map

    10. Watch timer A96G166/A96A166/A96S166 User’s manual 10.2 Register map Table 14. Watch Timer Register Map Name Address Direction Default Description WTCNT Watch Timer Counter Register WTDR Watch Timer Data Register WTCR Watch Timer Control Register 10.3 Watch timer register description WTCNT (Watch Timer Counter Register: Read Case): 89H –...
  • Page 83 A96G166/A96A166/A96S166 User’s manual 10. Watch timer WTCR (Watch Timer Control Register): 96H – – WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – – Initial value: 00H WTEN Control Watch Timer Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write WTIFR ‘0’...

  • Page 84: Timer 0/1/2

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual 11 Timer 0/1/2 11.1 Timer 0 An 8-bit timer 0 consists of a multiplexer, a timer 0 counter register, a timer 0 data register, a timer 0 capture data register and a timer 0 control register (T0CNT, T0DR, T0CDR, T0CR).

  • Page 85: Figure 31. 8-Bit Timer/Counter Mode For Timer 0

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 ADDRESS : B2H T0CR T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC INITIAL VALUE: 0000_0000B Match signal Clear fx/2 T0CC fx/4 8-bit Timer 0 Counter fx/8 INT_ACK T0CNT(8Bit) fx/32 Clear fx/128 Match fx/512 To interrupt...

  • Page 86: 8-Bit Pwm Mode

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual 11.1.2 8-bit PWM mode Timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O function by P3FSRH[0] or P3FSRL[4] bits.

  • Page 87: Figure 34. Pwm Output Waveforms In Pwm Mode For Timer 0

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 PWM Mode(T0MS = 01b) Set T0EN Timer 0 clock T0CNT T0DR T0 Overflow Interrupt 1. T0DR = 4AH T0PWM T0 Match Interrupt 2. T0DR = 00H T0PWM T0 Match Interrupt 3. T0DR = FFH...

  • Page 88: 8-Bit Capture Mode

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual 11.1.3 8-bit capture mode Timer 0 capture mode is set by configuring T0MS[1:0] as ‘1x’. Clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode has, and the interrupt occurs when T0CNT equals to T0DR.

  • Page 89: Figure 36. Input Capture Mode Operation For Timer 0

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 Figure 36. Input Capture Mode Operation for Timer 0 Figure 37. Express Timer Overflow in Capture Mode...

  • Page 90: Timer 0 Block Diagram

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual 11.1.4 Timer 0 block diagram fx/2 fx/4 8-bit Timer 0 Counter Match signa l fx/8 Clear INT_ACK T0CNT (8Bit) fx/32 T0CC Clear fx/128 Clear fx/512 Match To interrupt T0EN T0IFR block fx/2048 Comparator T0DR (8Bit)

  • Page 91: Register Description

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 11.1.6 Register description T0CNT (Timer 0 Counter Register): B3H T0CNT7 T0CNT6 T0CNT5 T0CNT4 T0CNT3 T0CNT2 T0CNT1 T0CNT0 Initial value: 00H T0CNT[7:0] T0 Counter T0DR (Timer 0 Data Register): B4H T0DR7 T0DR6 T0DR5 T0DR4 T0DR3...

  • Page 92: Timer 1

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual 11.2 Timer 1 A 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low and timer 1 control register high/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL).

  • Page 93: 16-Bit Timer/Counter Mode

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 11.2.1 16-bit timer/counter mode 16-bit timer/counter mode is selected by control registers, and the 16-bit timer/counter has counter registers and data registers as shown in Figure 39. The counter register is increased by internal or external clock input.

  • Page 94: Figure 40. 16-Bit Timer/Counter Mode Operation Example

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual Figure 40. 16-bit Timer/Counter Mode Operation Example...

  • Page 95: 16-Bit Capture Mode

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 11.2.2 16-bit capture mode It uses an internal/external clock as a clock source. Basically, the 16-bit timer 1 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T1CNTH/T1CNTL is equal to T1ADRH/T1ADRL.

  • Page 96: Figure 42. 16-Bit Capture Mode Operation Example

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual T1BDRH/L Load T1CNTH/L Value Count Pulse Period Up-count TIME EINT11 PIN Interrupt Request Interrupt Interval Period (FLAG11) Figure 42. 16-bit Capture Mode Operation Example Figure 43. Express Timer Overflow 16-bit Capture Mode...

  • Page 97: 16-Bit Ppg Mode

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 11.2.3 16-bit PPG mode TIMER 1 has a PPG (Programmable Pulse Generation) function. In PPG mode, T1O/PWM1O pin outputs up to 16-bit resolution PWM output. For this function, T1O/PWM1O pin must be configured as a PWM output by setting P0FSRH[3:2] or P1FSRL[1:0] or P1FSRL[5:4] to ‘01’.

  • Page 98: Figure 45. 16-Bit Ppg Mode Operation Example

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock Counter T1ADRH/L T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L PWM1O B Match A Match 2. T1BDRH/L >= T1ADRH/L...

  • Page 99: 16-Bit Complementary Pwm Mode (Dead Time)

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 11.2.4 16-bit complementary PWM mode (dead time) The timer 1 has a complementary PWM function. The complementary PWM output function operates when T1BEN is set. In PPG mode, PWM1O/PWM1OB pin outputs up to 16-bit resolution complementary PWM output.

  • Page 100: Figure 47. 16-Bit Complementary Pwm Mode Timing Chart For Timer 1

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock T1_Counter ···· ···· ···· TZ_Counter T1ADRH/L T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L, T1CDRH/L(2), T1DDRH/L(5), PWM1O B Match...

  • Page 101: 16-Bit Timer 1 Block Diagram

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 11.2.5 16-bit timer 1 block diagram In this section, a 16-bit timer 1 is described in a block diagram. 16-bit A Data Register 16-bit D Data Register T1ADRH/T1ADRL T1DDRH/T1DDRL Reload Reload Buffer Register A...

  • Page 102: Register Map

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual 11.2.6 Register map Table 18. TIMER 1 Register Map Name Address Direction Default Description T1CRL Timer 1 Control Low Register T1CRH Timer 1 Control High Register T1ADRL Timer 1 A Data Low Register T1ADRH...
  • Page 103 A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 T1BDRL (Timer 1 B Data Low Register): BEH T1BDRL7 T1BDRL6 T1BDRL5 T1BDRL4 T1BDRL3 T1BDRL2 T1BDRL1 T1BDRL0 Initial value: FFH T1BDRL[7:0] T1 B Data Low Byte T1CDRH (Timer 1 C data High Register): DAH T1CDRH7...
  • Page 104 11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual T1CRH (Timer 1 Control High Register): BBH – – T1EN T1BEN T1MS1 T1MS0 T1PE T1CC – – Initial value: 00H T1EN Control Timer 1 Timer 1 disable Timer 1 enable (Counter clear and start)

  • Page 105: Timer 2

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 11.3 Timer 2 A 16-bit timer 2 consists of a multiplexer, timer 2 A data high/low register, timer 2 B data high/low register and timer 2 control high/low register (T2ADRH, T2ADRL, T2BDRH, T2BDRL, T2CRH, and T2CRL).

  • Page 106: 16-Bit Timer/Counter Mode

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual 11.3.1 16-bit timer/counter mode 16-bit timer/counter mode is selected by control registers, and the 16-bit timer/counter has counter registers and data registers as shown in Figure 49. The counter register is increased by internal or timer 1 A match clock input.

  • Page 107: Figure 50. 16-Bit Timer/Counter Mode Operation Example

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 Figure 50. 16-bit Timer/Counter Mode Operation Example...

  • Page 108: 16-Bit Capture Mode

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual 11.3.2 16-bit capture mode Timer 2 capture mode is set by configuring T2MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 2 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T2CNTH/T2CNTL is equal to T2ADRH/T2ADRL.

  • Page 109: Figure 52. 16-Bit Capture Mode Operation Example

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 Figure 52. 16-bit Capture Mode Operation Example Figure 53. Express Timer Overflow in Capture Mode...

  • Page 110: 16-Bit Ppg Mode

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual 11.3.3 16-bit PPG mode TIMER 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, T2O/PWM2O pin outputs up to 16-bit resolution PWM output. For this function, T2O/PWM2O pin must be configured as a PWM output by setting P1FSRL[7:6] or P0FSRH[3:2] to ‘01’.

  • Page 111: Figure 55. 16-Bit Ppg Mode Operation Example

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 Repeat Mode(T2MS = 11b) and "Start High"(T2POL = 0b). Clear and Start Set T2EN Timer 2 clock Counter T2ADRH/L T2 Interrupt 1. T2BDRH/L(5) < T2ADRH/L PWM2O B Match A Match 2. T2BDRH/L >= T2ADRH/L...

  • Page 112: 16-Bit Timer 2 Block Diagram

    11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual 11.3.4 16-bit timer 2 block diagram In this section, a 16-bit timer 2 is described in a block diagram. 16-bit A Data Re gister T2ADRH/T2ADRL A Match Reload T2CC T2ECE T2ECS T2CK[2:0] T2EN INT_ACK...

  • Page 113: Register Description

    A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2 11.3.6 Register description T2ADRH (Timer 2 A data High Register): C5H T2ADRH7 T2ADRH6 T2ADRH5 T2ADRH4 T2ADRH3 T2ADRH2 T2ADRH1 T2ADRH0 Initial value: FFH T2ADRH[7:0] T2 A Data High Byte T2ADRL (Timer 2 A Data Low Register): C4H...
  • Page 114 11. Timer 0/1/2 A96G166/A96A166/A96S166 User’s manual T2CRL (Timer 2ControlLow Register): C2H T2CK2 T2CK1 T2CK0 T2IFR T2ECS T2POL T2ECE T2CNTR Initial value: 00H T2CK[2:0] Select Timer 2 clock source. fx is main system clock frequency T2CK2 T2CK1 T2CK0 Description Fx2048 fx/512...

  • Page 115: 12 Buzzer Driver

    12. Buzzer driver 12 Buzzer driver A buzzer of A96G166/A96A166/A96S166 consists of 8-bit counter, a buzzer data register (BUZDR), and a buzzer control register (BUZCR). It outputs square wave (61.035Hz to 125.0kHz @ 8MHz) through P11/AN8/EINT6/EC1/BUZO pin, and its buzzer data register (BUZDR) controls the buzzer frequency (refer to the following expression).

  • Page 116: Register Map

    12. Buzzer driver A96G166/A96A166/A96S166 User’s manual 12.2 Register map Table 22. Buzzer Driver Register Map Name Address Direction Default Description BUZDR Buzzer Data Register BUZCR Buzzer Control Register 12.3 Register description BUZDR (Buzzer Data Register): 8FH BUZDR7 BUZDR6 BUZDR5 BUZDR4...

  • Page 117: 13 12-Bit Adc

    13. 12-bit ADC 13 12-bit ADC Analog-to-digital converter (ADC) of A96G166/A96A166/A96S166 allows conversion of an analog input signal to corresponding 12-bit digital value. This A/D module has eight analog inputs. Output of the multiplexer becomes input into the converter which generates the result through successive approximation.

  • Page 118: Block Diagram

    13. 12-bit ADC A96G166/A96A166/A96S166 User’s manual 13.2 Block diagram In this section, the 12-bit ADC is described in a block diagram, and an analog input pin and a power pin with capacitors respectively are introduced. TRIG[2:0] ADSEL[3:0] (Select one input pin...

  • Page 119: Adc Operation

    A96G166/A96A166/A96S166 User’s manual 13. 12-bit ADC 13.3 ADC operation In this section, control registers and align bits are introduced in Figure 60, and ADC operation flow sequence is introduced in Figure 61. Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8...

  • Page 120: Register Map

    13. 12-bit ADC A96G166/A96A166/A96S166 User’s manual 13.4 Register map Table 23. ADC Register Map Name Address Direction Default Description ADCDRH A/D Converter Data High Register ADCDRL A/D Converter Data Low Register ADCCRH A/D Converter Control High Register ADCCRL A/D Converter Control Low Register 13.5...
  • Page 121 A96G166/A96A166/A96S166 User’s manual 13. 12-bit ADC ADCCRH (A/D Converter High Register): 9DH ADCIFR IREF TRIG2 TRIG1 TRIG0 ALIGN CKSEL1 CKSEL0 Initial value: 01H When ADC interrupt occurs, this bit becomes ‘1’. For clearing bit, ADCIFR write ‘0’ to this bit or auto clear by INT_ACK signal. Writing “1” has no effect.
  • Page 122 13. 12-bit ADC A96G166/A96A166/A96S166 User’s manual ADCCRL (A/D Converter Counter Low Register): 9CH STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value: 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable...

  • Page 123: 14 I2C

    A96G166/A96A166/A96S166 User’s manual 14. I2C 14 I2C I2C is one of industrial standard serial communication protocols, which uses 2 bus lines such as Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL are open-drain outputs, each line needs a pull-up resistor respectively.

  • Page 124: Bit Transfer

    14. I2C A96G166/A96A166/A96S166 User’s manual 14.2 Bit transfer Data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions are START(S), repeated START (Sr) and STOP (P) condition where data line changes when clock line is high.

  • Page 125: Data Transfer

    A96G166/A96A166/A96S166 User’s manual 14. I2C 14.4 Data transfer Every byte on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first.

  • Page 126: Synchronization/ Arbitration

    14. I2C A96G166/A96A166/A96S166 User’s manual Data Output by Transmitter Data Output by Receiver SCL from MASTER Clock pulse for ACK Figure 66. Acknowledge on the I2C-Bus 14.6 Synchronization/ arbitration Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line.

  • Page 127: Block Operation

    A96G166/A96A166/A96S166 User’s manual 14. I2C Arbitration Process Device 1 loses Device1 outputs not adapted Arbitration High Device1 Data Out Device2 Data Out SDA on BUS SCL on BUS Figure 68. Arbitration Procedure of Two Masters 14.7 Block operation The I2C block as peripheral design is independently operating with main CPU operation. The operation of I2C block does a byte unit of I2C frame.

  • Page 128: I2C Block Initialization Process

    14. I2C A96G166/A96A166/A96S166 User’s manual NOTE: When an I2C interrupt is generated by I2C block, IIF flag in I2CMR register is set and it is cleared by writing any value to I2CSR. When I2C interrupt occurs, the SCL line is hold LOW for reading/writing I2CDR register and control I2CMR until writing any value to I2CSR.

  • Page 129: I2C Interrupt Service

    A96G166/A96A166/A96S166 User’s manual 14. I2C Finally be ready to get I2C data from I2C bus system as a slave device by configuring the I2C interrupt enable bit, the I2C block enable bit, and the ACK enable bit of the I2CMR register.

  • Page 130: Master Transmitter

    14. I2C A96G166/A96A166/A96S166 User’s manual 14.7.3 Master transmitter Main software prepares to write/read data to/from the Slave I2C device. The software has to be ready to get number of data with internal RAM or sending data on internal RAM according to I2C bus protocol type of the Slave device.
  • Page 131 A96G166/A96A166/A96S166 User’s manual 14. I2C Master Read ( without sub address of Slave device ) I2CMR = IICEN+INTEN; // start generate I2CDR = Slave Address + Read mode; // load target Salve Address I2CMR |= SRT; // generate start condition...

  • Page 132: Slave Receiver

    14. I2C A96G166/A96A166/A96S166 User’s manual 14.7.4 Slave receiver When both the IIC and the INTEN of the I2CMR are enabled, the I2C block monitors I2C bus lines for the start condition and the self-address with I2CSAD. To have both signals of start signal and getting self-address, the I2C block generates I2C interrupts with the status bits (SSEL, BUSY RXACK, SLAVE mode, and so on) after sending an ACK signal.

  • Page 133: Register Map

    A96G166/A96A166/A96S166 User’s manual 14. I2C 14.8 Register Map Table 24. I C Register Map Name Address Direction Default Description I2CMR I2C Mode Control Register I2CSR I2C Status Register I2CSCLLR SCL Low Period Register I2CSCLHR SCL High Period Register I2CSDAHR SDA Hold Time Register...

  • Page 134: I2C Register Description

    14. I2C A96G166/A96A166/A96S166 User’s manual 14.9 I2C register description I2CMR (I2C Mode Control Register): E1H IICEN RESET INTEN ACKEN MASTER STOP START Initial value: 00H This is interrupt flag bit. No interrupt is generated or interrupt is cleared An interrupt is generated...
  • Page 135 A96G166/A96A166/A96S166 User’s manual 14. I2C I2CSR (I2C Status Register): E2H GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK Initial value: 00H GCALL This bit has different meaning depending on whether I2C is master NOTE1 or slave. When I2C is a master, this bit represents whether it received AACK (Address ACK) from slave.
  • Page 136 14. I2C A96G166/A96A166/A96S166 User’s manual I2CSCLLR (SCL Low Period Register): E3H SCLL7 SCLL6 SCLL5 SCLL4 SCLL3 SCLL2 SCLL1 SCLL0 Initial value: 3FH SCLL[7:0] This register defines the LOW period of SCL when I2C operates in master mode. The base clock is SCLK, the system clock, and the period is calculated by the formula : t ×...
  • Page 137 A96G166/A96A166/A96S166 User’s manual 14. I2C I2CSAR (I2C Slave Address Register): E9H SLA7 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 GCALLEN Initial value: 00H SLA[7:1] These bits configure the slave address of this I2C module when I2C operates in slave mode. GCALLEN This bit decides whether I2C allows general call address or not when I2C operates in slave mode.

  • Page 138: Usart 0/1

    15 USART 0/1 Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. A96G166/A96A166/A96S166 has two USART function blocks, USART0 and USART1 are absolutely same functionally. Main features of the USART0/1 are listed below: Full Duplex Operation (Independent Serial Receive and Transmit Registers) ...

  • Page 139: Block Diagram

    A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 The Receiver supports the same frame formats as the transmitter. It can detect Frame Error, Data OverRun and Parity Errors. 15.1 Block diagram UBAUD SCLK Baud Rate Generator Master Clock Sync Logic XCKn Control...

  • Page 140: Clock Generation

    15. USART 0/1 A96G166/A96A166/A96S166 User’s manual 15.2 Clock generation The Clock generation logic generates a base clock signal for the transmitter and the receiver. The USART supports four modes of clock operation such as Normal Asynchronous mode, Double Speed Asynchronous mode, Master Synchronous mode, and Slave Synchronous mode.

  • Page 141: External Clock (Xck)

    A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 15.3 External clock (XCK) External clocking is used by the synchronous or SPI slave modes of operation. External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must then pass through an edge detector before it can be used by the Transmitter and Receiver.

  • Page 142: Data Format

    15. USART 0/1 A96G166/A96A166/A96S166 User’s manual 15.5 Data format A serial frame is defined to consist of one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. USART2 supports all 30 combinations of the followings as a valid frame format.

  • Page 143: Parity Bit

    A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 15.6 Parity bit Parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive-or is inverted. The parity bit is located between St + bits and first stop bit of a serial frame.

  • Page 144: Transmitter Flag And Interrupt

    15. USART 0/1 A96G166/A96A166/A96S166 User’s manual 15.7.2 Transmitter flag and interrupt USART transmitter has 2 flags which indicate its state. One is USART Data Register Empty (UDRE) and the other is Transmit Complete (TXC). Both flags can be used as interrupt sources.

  • Page 145: Receiving Rx Data

    A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 15.8.1 Receiving Rx data When USART is in synchronous or asynchronous operation mode, the Receiver starts data reception when it detects a valid start bit (LOW) on RXDn pin. Each bit after start bit is sampled at pre-defined baud-rate (asynchronous) or sampling edge of XCKn (synchronous), and shifted into the receive shift register until the first stop bit of a frame is received.

  • Page 146: Parity Checker

    15. USART 0/1 A96G166/A96A166/A96S166 User’s manual The Parity Error (PE) flag indicates that the frame in the receive buffer had a Parity Error when received. If Parity Check function is not enabled (UPM[1] = 0), the PE bit is always read “0”.

  • Page 147: Figure 75. Sampling Of Data And Parity Bit

    A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 If more than 2 samples have logical low level, it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame. And the data recovery can begin.

  • Page 148: Spi Mode

    15. USART 0/1 A96G166/A96A166/A96S166 User’s manual 15.9 SPI mode The USARTn can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. Full duplex, three-wire synchronous data transfer  Master or Slave operation ...

  • Page 149: Figure 77. Spi Clock Formats When Ucpha = 0

    A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 XCKn (UCPOL=0) XCKn (UCPOL=1) SAMPLE MOSIn MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 77. SPI Clock Formats when UCPHA = 0 When UCPHA=0, the slave begins to drive its MISOn output with the first data bit value when SSn goes to active low.

  • Page 150: Figure 78. Spi Clock Formats When Ucpha = 1

    15. USART 0/1 A96G166/A96A166/A96S166 User’s manual (UCPOL=0) (UCPOL=1) SAMPLE MOSI2 MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO2 /SS2 OUT (MASTER) /SS2 IN (SLAVE) Figure 78. SPI Clock Formats when UCPHA = 1 When UCPHA=1, the slave begins to drive its MISOn output when SSn goes active low, but the data is not defined until the first XCKn edge.

  • Page 151: Receiver Time Out (Rto)

    A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 15.10 Receiver time out (RTO) This USART system supports the time out function. This function is occur the interrupts when stop bit are not in RX line during URTOC setting value. RTO count stops in RXD signal live state and RTO clear and start is executed by stop bit recognition.

  • Page 152: Register Map

    15. USART 0/1 A96G166/A96A166/A96S166 User’s manual 15.11 Register map Table 28. USART Register Map Name Address Direction Default Description UnCTRL1 CBH/F1H USART Control 1 Register UnCTRL2 CCH/F2H USART Control 2 Register UnCTRL3 CDH/F3H USART Control 3 Register UnCTRL4 1018H/1019H USART Control 4 Register...

  • Page 153: Register Description

    A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 15.12 Register description UnCTRL1 (USART Control 1 Register) CBH/F1H USIZE1 USIZE0 UMSEL1 UMSEL0 UPM1 UPM0 USIZE2 UCPOL UDORD UCPHA Initial value: 00 UMSEL[1:0] Selects operation mode of USART UMSEL1 UMSEL0 Operating Mode Asynchronous Mode (Normal UART)
  • Page 154 15. USART 0/1 A96G166/A96A166/A96S166 User’s manual UCTRL2 (USART Control 2 Register) CCH/F2H UDRIE TXCIE RXCIE WAKEIE USARTEN Initial value: 00 UDRIE Interrupt enable bit for USART Data Register Empty. Interrupt from UDRE is inhibited (use polling) When UDRE is set, request an interrupt TXCIE Interrupt enable bit for Transmit Complete.
  • Page 155 A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 UnCTRL3 (USART Control 3 Register) CDH/F3H MASTER LOOPS DISXCK SPISS USBS Initial value: 00 MASTER Selects master or slave in SPI or Synchronous mode operation and controls the direction of XCK pin. Slave mode operation and XCK is input pin.
  • Page 156 15. USART 0/1 A96G166/A96A166/A96S166 User’s manual UnCTRL4 (USART Control 4 Register) 1018H/1019H RTOEN RTO_FLAG FPCREN AOVSEN AOVSSEL Initial value: 00 RTOEN Enable receiver time out. Disable Enable RTO_FLAG This bit is set when RTO count overflows. This flag can generate an RTO interrupt.
  • Page 157 A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 UnSTAT (USART Status Register) CFH/F7H UDRE WAKE SOFTRST Initial value: 80 UDRE The UDRE flag indicates if the transmit buffer (UDATA) is ready to be loaded with new data. If UDRE is ‘1’, it means the transmit buffer is empty and can hold one or two new data.
  • Page 158 15. USART 0/1 A96G166/A96A166/A96S166 User’s manual UnBAUD (USART Baud-Rate Generation Register) FCH/F5H UBAUD7 UBAUD6 UBAUD5 UBAUD4 UBAUD3 UBAUD2 UBAUD1 UBAUD0 Initial value: FF UBAUD [7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to generate XCK clock in synchronous or SPI mode.
  • Page 159 A96G166/A96A166/A96S166 User’s manual 15. USART 0/1 RTOCHn (Receiver Time-out Counter High Register) 101BH/101EH RTOCH7 RTOCH6 RTOCH5 RTOCH4 RTOCH3 RTOCH2 RTOCH1 RTOCH0 Initial value: 00 RTOCLn (Receiver Time-out Counter Low Register) 101CH/101FH RTOCL7 RTOCL6 RTOCL5 RTOCL4 RTOCL3 RTOCL2 RTOCL1 RTOCL0 Initial value: 00...

  • Page 160: Baud Rate Settings (Example)

    15. USART 0/1 A96G166/A96A166/A96S166 User’s manual 15.13 Baud rate settings (example) Table 29. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies fOSC=1.00MHz fOSC=1.8432MHz fOSC=2.00MHz Baud U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 rate UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD...

  • Page 161: 0% Error Baud Rate

    15. USART 0/1 15.14 0% error baud rate USART system of A96G166/A96A166/A96S166 supports floating point counter logic for 0% error of baud rate. By using 8-bit floating point counter logic, cumulative error to below the decimal point can be removed.

  • Page 162: 16 Crc

    16. CRC A96G166/A96A166/A96S166 User’s manual 16 CRC Using the CRC, it can be monitor the memory of the specified area. This is a one-time operation, and reset is required for continuous operation. In CRC MNT mode, when the CRC read is finished, CRC_FLAG occurs.

  • Page 163: Register Map

    A96G166/A96A166/A96S166 User’s manual 16. CRC 16.2 Register map Table 31. CRC Register Map Name Address Direction Default Description CRC_CON 1070H CRC Control Register CRC_H 1072H CRC High Register CRC_L 1073H CRC Low Register CRC_MNT_H 1074H CRC Monitor High Register CRC_MNT_L...

  • Page 164: Register Description

    16. CRC A96G166/A96A166/A96S166 User’s manual 16.3 Register description CRC_CON (CRC Control Register): 1070H CRC_FLAG CRC_INTEN CRC_ CRC_EN CRC_FAIL CRC_TYPE 2 CRC_TYPE 1 CRC_TYPE 0 RESETEN Initial value: 00H CRC flag. The flag is cleared only by writing a ‘0’ to the bit. So, the CRC_FLAG flag should be cleared by software.
  • Page 165 A96G166/A96A166/A96S166 User’s manual 16. CRC CRC_MNT_L (CRC Monitor Low Register): 1075H CRC_MNT[7] CRC_MNT[6] CRC_MNT[5] CRC_MNT[4] CRC_MNT[3] CRC_MNT[2] CRC_MNT[1] CRC_MNT[0] Initial value: 00H CRC_MNT CRC compare register, when performing a validate [15:0] CRC_ADDR_START_H (CRC Start Address High Register): 1079H CRC_ADDR_ START[16]...

  • Page 166: Polynomial

    16. CRC A96G166/A96A166/A96S166 User’s manual CRC_ADDR_END_L (CRC END Address Low Register): 107EH CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ CRC_ADDR_ END[7] END[6] END[5] END[4] END[3] END[2] END[1] END[0] Initial value: 00H CRC_ADDR_ CRC end address END[16:0] 16.1 Polynomial CRC16, Polynomial representations Normal : 0x8C81 ...

  • Page 167: 17 Power Down Operation

    A96G166/A96A166/A96S166 User’s manual 17. Power down operation 17 Power down operation A96G166/A96A166/A96S166 has two power-down modes to minimize the power consumption of the device. power down mode, power consumption reduced considerably. A96G166/A96A166/A96S166 provides three kinds of power saving functions such as Main-IDLE mode, Sub-IDLE mode and STOP mode.

  • Page 168: Idle Mode

    17. Power down operation A96G166/A96A166/A96S166 User’s manual Table 32. Peripheral Operation Status during Power-down Mode (continued) Peripheral IDLE mode STOP mode Address Data Bus Retains. Retains. Release Method By RESET By RESET All Interrupts Timer Interrupt (EC0, EC1) External Interrupt...

  • Page 169: Stop Mode

    A96G166/A96A166/A96S166 User’s manual 17. Power down operation 17.3 STOP mode Power control register is set to ‘03H’ to enter into STOP mode. In STOP mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock.

  • Page 170: Released Operation Of Stop Mode

    17. Power down operation A96G166/A96A166/A96S166 User’s manual 17.4 Released operation of STOP mode After STOP mode is released, operation begins according to content of related interrupt register just before STOP mode starts (refer to Figure 84). If the global interrupt Enable Flag (IE.EA)is set to `1`, the STOP mode is released by a certain interrupt of which interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine.

  • Page 171: Register Map

    A96G166/A96A166/A96S166 User’s manual 17. Power down operation 17.5 Register map Table 33. Power-down Operation Register Map Name Address Direction Default Description PCON Power Control Register 17.6 Register description PCON (Power Control Register): 87H PCON7 – – – PCON3 PCON2 PCON1 PCON0 –...

  • Page 172: 18 Reset

    Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers A96G166/A96A166/A96S166 has five types of reset sources as shown in the followings: External RESETB  Power ON RESET (POR)  WDT Overflow Reset (In the case of WDTEN = `1`) ...

  • Page 173: Power On Reset

    A96G166/A96A166/A96S166 User’s manual 18. Reset 18.2 Power on reset When rising device power, POR (Power on Reset) has a function to reset a device. If POR is used, it executes the device RESET function instead of the RESET IC or the RESET circuits.

  • Page 174: Figure 88. Configuration Timing When Power-On

    18. Reset A96G166/A96A166/A96S166 User’s manual Counting for configure option read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Configure) 00 01 02 03 BIT (for Reset) 1us X 256 X 28h = about 10ms...

  • Page 175: Table 35. Boot Process Description

    A96G166/A96A166/A96S166 User’s manual 18. Reset Table 35. Boot Process Description Process Description Remarks ①  No Operation 0.7V to 0.9V  LSI (128kHz) ON ② 1st POR level Detection About 1.1V to 1.3V ③  (LSI 128kHz/32)x32h Delay section Slew Rate >= 0.025V/ms (=10ms) ...

  • Page 176: External Resetb Input

    18. Reset A96G166/A96A166/A96S166 User’s manual 18.3 External resetb input External resetb is input to a Schmitt trigger. If the resetb pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized.

  • Page 177: Low Voltage Reset Process

    18.4 Low voltage reset process A96G166/A96A166/A96S166 has an On-chip brown-out detection circuit (LVR) for monitoring VDD level during operation by comparing it to a fixed trigger level. Trigger level for the LVR can be selected by configuring LVRVS[3:0] bits to be 1.61V, 1.68V, 1.77V, 1.88V, 2.00V, 2.13V, 2.28V, 2.46V, 2.68V, 2.81V, 3.06V, 3.21V, 3.56V, 3.73V, 3.91V, 4.25V.

  • Page 178: Lvi Block Diagram

    18. Reset A96G166/A96A166/A96S166 User’s manual “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB ..27 28 BIT (for Config) 00 01 02 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...

  • Page 179: Register Map

    A96G166/A96A166/A96S166 User’s manual 18. Reset 18.6 Register Map Table 36. Reset Operation Register Map Name Address Direction Default Description RSTFR Reset Flag Register LVRCR Low Voltage Reset Control Register LVICR Low Voltage Indicator Control Register 18.7 Reset operation register description RSTFR (Reset Flag Register): E8H –...
  • Page 180 18. Reset A96G166/A96A166/A96S166 User’s manual LVRCR (Low Voltage Reset Control Register): D8H – – – LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – – Initial value: 00H LVRVS[3:0] LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 1.61V 1.68V 1.77V 1.88V 2.00V 2.13V...
  • Page 181 A96G166/A96A166/A96S166 User’s manual 18. Reset LVICR (Low Voltage Indicator Control Register): 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value: 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable Enable LVIVS[3:0]...

  • Page 182: 19 Memory Programming

    19. Memory programming A96G166/A96A166/A96S166 User’s manual 19 Memory programming A96G166/A96A166/A96S166 has flash memory to which a program can be written, erased, and overwritten while mounted on the board. Serial ISP mode is supported. Flash of A96G166/A96A166/A96S166 features the followings: Flash Size : 16Kbytes ...

  • Page 183: Register Description

    A96G166/A96A166/A96S166 User’s manual 19. Memory programming 19.1.2 Register description FEMR (Flash Mode Register): 1020H FSEL ERASE PBUFF OTPE FEEN Initial value: 00H FSEL Select flash memory. Deselect flash memory Select flash memory Enable program or program verify mode with VFY...
  • Page 184 19. Memory programming A96G166/A96A166/A96S166 User’s manual FECR (Flash Control Register): 1021H EXIT1 EXIT0 WRITE READ nFERST nPBRST Initial value: 03H Enable flash bulk erase mode Disable bulk erase mode of Flash memory Enable bulk erase mode of Flash memory EXIT[1:0] Exit from program mode.
  • Page 185 A96G166/A96A166/A96S166 User’s manual 19. Memory programming FEARL1 (Flash address low Register 1): 1025H ARL17 ARL16 ARL15 ARL14 ARL13 ARL12 ARL11 ARL10 Initial value: 00H ARL1[7:0] Flash address low 1 FEARM1 (Flash address middle Register 1): 1024H ARM17 ARM16 ARM15 ARM14...

  • Page 186: Figure 96. Read Device Internal Checksum (Full Size)

    19. Memory programming A96G166/A96A166/A96S166 User’s manual Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEMR, 0x81) Set auto verify mode Write(OCD_CODE, FETR, 0x08) Write(OCD_CODE, FECR, 0x07) Busy check (FESR[7]=L) Read 24...

  • Page 187: Figure 97. Read Device Internal Checksum (User Define Size)

    A96G166/A96A166/A96S166 User’s manual 19. Memory programming Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEARM,Start Address Upper) Set auto verify mode Write(OCD_XDATA, FEARL,Start Address Lower) Write(OCD_XDATA, FEARM1,End Address Upper) Write(OCD_XDATA, FEARL1,End Address Lower)

  • Page 188: Table 38. Program And Erase Time

    19. Memory programming A96G166/A96A166/A96S166 User’s manual FETCR (Flash Time control Register): 1023H TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Initial value: 00H TCR[7:0] Flash Time control Program and erase time is controlled by setting FETCR register. Program and erase timer uses 10-bit counter.

  • Page 189: Memory Map

    A96G166/A96A166/A96S166 User’s manual 19. Memory programming 19.2 Memory map 19.2.1 Flash memory map Program memory uses 16K bytes of flash memory. It is read by byte and written by byte or page. One page is 32-bytes FFFFh pgm/ers/vfy Flash 3FFFh...

  • Page 190: Serial In-System Program Mode

    19. Memory programming A96G166/A96A166/A96S166 User’s manual 19.3 Serial in-system program mode Serial in-system program uses the interface of debugger which uses two wires. Refer to Development tools in details about debugger. 19.3.1 Flash operation Configuration (This Configuration is just used for follow description) FEMR[4] &...

  • Page 191: Figure 101. The Sequence Of Bulk Erase Of Flash Memory

    A96G166/A96A166/A96S166 User’s manual 19. Memory programming Master Reset Page Buffer Reset Page Buffer Load Configuration Reg.<0> Set Erase Erase Latency (500us) Page Buffer Reset Configuration Reg.<0> clear Reg.<6:5> setting Cell Read Pass/Fail? Figure 101. The Sequence of Bulk Erase of Flash Memory Flash read Enter OCD (=ISP) mode.
  • Page 192 19. Memory programming A96G166/A96A166/A96S166 User’s manual Write 0x55 to 0xFAAA. C. Write 0xA5 to 0xF555. NOTES: Refer to how to enter ISP mode. Command sequence to activate Flash write/erase mode. It is composed of sequentially writing data of Flash memory.
  • Page 193 A96G166/A96A166/A96S166 User’s manual 19. Memory programming 11. Repeat 2 to 8 until all pages are erased Flash bulk erase mode Enable program mode. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 Select page buffer. FEMR:1000_1001 Write ‘h00 to page buffer. (Data value is not important.) Set erase mode.
  • Page 194 19. Memory programming A96G166/A96A166/A96S166 User’s manual Start program. FECR:0000_1011 Insert one NOP operation 10. Read FESR until PEVBSY is 1. Flash OTP area erase mode Enable program mode. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 Select page buffer. FEMR:1000_1001 Write ‘h00 to page buffer. (Data value is not important.) Set erase mode and select OTP area.

  • Page 195: Mode Entrance Method Of Isp Mode

    A96G166/A96A166/A96S166 User’s manual 19. Memory programming Flash page buffer read Enable program mode. Select page buffer. FEMR:1000_1001 Read data from Flash. Summary of flash program/erase mode Table 39. Operation Mode Operation mode Description Flash read Read cell by byte. Flash write Write cell by bytes or page.

  • Page 196: Security

    19.5 Security A96G166/A96A166/A96S166 provides Lock bits which can be left un-programmed (“0”) or can be programmed (“1”) to obtain the additional features listed in Table 41. The Lock bit can only be erased to “0” with the bulk erase command and a value of more than 0x40 at FETCR.

  • Page 197: Configure Option

    19. Memory programming 19.6 Configure option For the configure option control, corresponding data should be written in the configure option area (003EH to 003FH) by programmer (writer tools). CONFIGURE OPTION 2: ROM Address 0001H (A96G166) – VAPEN – – –...
  • Page 198 19. Memory programming A96G166/A96A166/A96S166 User’s manual CONFIGURE OPTION 1: ROM Address 0000H – – – – PAEN PASS2 PASS1 PASS0 Initial value: 00H PAEN Enable Specific Area Write Protection Disable Protection Enable Protection PASS [2:0] Select Specific Area for Write Protection NOTE: When PAEN = ‘1’, it is applied.

  • Page 199: Password Function

    19. Memory programming 19.7 Password function A96G166/A96A166/A96S166 provides security mode which is called “Password Function”. This function obtain the additional features listed in Table 42. Password Lock bit allow you to access or not register and flash of the device.

  • Page 200: Figure 103. Using Ocd/E-Pgm+/E-Gang4/E-Gang6

    19. Memory programming A96G166/A96A166/A96S166 User’s manual This function can be set up using OCD/E-PGM+/E-GANG4/E-GANG6. See the guide for this feature below. 1. Press “config” button 2. Check “Password” box, and Change the Password(0~11byte) 3. Reset the device, please enter the password. If the password is correct, the device is accessible.

  • Page 201: 20 Electrical Characteristics

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics 20 Electrical characteristics 20.1 Absolute maximum ratings Table 43. Absolute Maximum Ratings Parameter Symbol Rating Unit Note Supply voltage -0.3~+6.5 – Normal voltage pin -0.3~VDD+0.3 Voltage on any pin with respect to VSS -0.3~VDD+0.3 42.5...

  • Page 202: A/D Converter Characteristics

    20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual 20.3 A/D converter characteristics Table 45. A/D Converter Characteristics =-40°C ~ +85°C or T =-40°C ~ 105°C, VDD=2.2V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit Integral Linear Error AVDD = 5.0V – ±4 ±8...

  • Page 203: Vdc1.55 Reference Voltage Characteristics

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics 20.4 VDC1.55 Reference Voltage Characteristics Table 47. VDC1.55 Reference Voltage Characteristics =-40°C ~ +85°C or T =-40°C ~ 105°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit VDC1.55 reference voltage VDC1.55 – – 1.55 –...

  • Page 204: Low Voltage Reset And Low Voltage Indicator Characteristics

    20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual 20.6 Low voltage reset and low voltage indicator characteristics Table 49. LVR and LVI Characteristics =-40°C ~ +85°C or T =-40°C ~ 105°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit Detection level The LVR can select all levels.

  • Page 205: High Speed Internal Rc Oscillator Characteristics

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics 20.7 High speed internal RC oscillator characteristics Table 50. High Speed Internal RC Oscillator Characteristics =-40°C ~ +85°C or T =-40°C ~ 105°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit Frequency = 1.8 – 5.5V –...

  • Page 206: Dc Characteristics

    20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual 20.9 DC characteristics Table 52. DC Characteristics = -40°C ~ +85°C or T =-40°C ~ 105°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Conditions Unit Input high voltage All input pins 0.7VDD –...

  • Page 207: Ac Characteristics

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics All supply current items don’t include the current of an internal Watch-dog timer RC (WDTRC) oscillator and a peripheral block. All supply current items include the current of the power-on reset (POR) block. 20.10 AC characteristics Table 53.

  • Page 208: Usart Characteristics

    20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual 20.11 USART characteristics The following table and figures show USART timing condition in SPI or Synchronous mode operation. Table 54. USART Timing Characteristics in SYNC. or SPI Mode Operations = -40°C ~ +85°C or T =-40°C ~ 105°C, VDD=1.8V ~ 5.5V)

  • Page 209: Figure 105. Spi Master Mode Timing (Ucpha = 0, Msb First)

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics /SS0 (OUTPUT) LEAD XCK0 0.8VDD (UCPOL=0) 0.2VDD (OUTPUT) XCKL XCKH XCK0 (UCPOL=1) (OUTPUT) MISO BIT 6 … 1 (INPUT) MOSI BIT 6 … 1 (OUTPUT) Figure 105. SPI master mode timing (UCPHA = 0, MSB first)

  • Page 210: Figure 107. Spi Slave Mode Timing (Ucpha = 0, Msb First)

    20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual /SS0 (OUTPUT) LEAD XCK0 0.8VDD (UCPOL=0) 0.2VDD (OUTPUT) XCKL XCKH XCK0 (UCPOL=1) (OUTPUT) MISO BIT 6 … 1 (INPUT) MOSI BIT 6 … 1 (OUTPUT) Figure 107. SPI slave mode timing (UCPHA = 0, MSB first)

  • Page 211: Spi Characteristics

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics 20.12 SPI characteristics Table 55. SPI Characteristics =-40°C– +85°C or T =-40°C ~ 105°C, VDD=1.8V – 5.5V) Parameter Symbol Conditions Unit Output clock pulse period tSCK Internal SCK source – – Input clock pulse period External SCK source –...

  • Page 212: I2C Characteristics

    20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual 20.13 I2C characteristics Table 56. I2C Characteristics =-40°C ~ +85°C or T =-40°C ~ 105°C, VDD=1.8V ~ 5.5V, f =8MHz) Parameter Symbol Standard Mode High-Speed Mode Unit Clock frequency tSCL Clock high pulse width tSCLH –...

  • Page 213: Data Retention Voltage In Stop Mode

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics 20.14 Data retention voltage in stop mode Table 57. Data Retention Voltage in Stop Mode =-40°C ~ +85°C or T =-40°C ~ 105°C, VDD=1.8V ~ 5.5V) Parameter Symbol Conditions Unit Data retention supply voltage –...

  • Page 214: Internal Flash Rom Characteristics

    20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual 20.15 Internal flash ROM characteristics Table 58. Internal Flash Rom Characteristics =-40°C ~ +85°C or T =-40°C ~ 105°C, VDD=1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Condition Unit Sector write time – – Sector erase time –...

  • Page 215: Main Clock Oscillator Characteristics

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics 20.17 Main clock oscillator characteristics Table 60. Main Clock Oscillator Characteristics =-40°C ~ +85°C or T =-40°C ~ 105°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Condition Unit Crystal Main oscillation frequency 2.2V – 5.5V –...

  • Page 216: Sub-Clock Oscillator Characteristics

    20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual 20.18 Sub-clock oscillator characteristics Table 61. Sub Clock Oscillator Characteristics =-40°C ~ +85°C or T =-40°C ~ 105°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Condition Unit Crystal Sub oscillation frequency 1.8V – 5.5V 32.768 External Clock SXIN input frequency –...

  • Page 217: Main Oscillation Stabilization Characteristics

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics 20.19 Main oscillation stabilization characteristics Table 62. Main Oscillation Stabilization Characteristics =-40°C ~ +85°C or T =-40°C ~ 105°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Unit Crystal fx > 4MHz, VDD = 2.7V ~ 5.5V, –...

  • Page 218: Operating Voltage Range

    20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual 20.21 Operating voltage range = 4 to 12MHz) =32 to 38kHz) 12.0MHz 32.768kHz 10.0MHz Supply voltage (V) Supply voltage (V) Figure 119. Operating Voltage Range 20.22 Recommended circuit and layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the PCB layout.

  • Page 219: Typical Characteristics

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics 20.23 Typical characteristics Graphs and tables provided in this section are only for design guidance which is not guaranteed. In the graphs and the tables, some data are out of specified operating range (e.g. out of specified VDD range).

  • Page 220: Figure 122. Idle (Idd2) Current

    20. Electrical characteristics A96G166/A96A166/A96S166 User’s manual Figure 122. IDLE (IDD2) Current Figure 123. SUB RUN (IDD3) Current...

  • Page 221: Figure 124. Sub Idle (Idd4) Current

    A96G166/A96A166/A96S166 User’s manual 20. Electrical characteristics Figure 124. SUB IDLE (IDD4) Current Figure 125. SUB IDLE (IDD4) Current...

  • Page 222: 21 Package Information

    21. Package information A96G166/A96A166/A96S166 User’s manual 21 Package information This chapter provides A96G166/A96A166/A96S166 package information. 21.1 16 SOPN package information Figure 126 16 SOPN Package Outline...

  • Page 223: 20 Tssop Package Information

    A96G166/A96A166/A96S166 User’s manual 21. Package information 21.2 20 TSSOP package information Figure 127. 20 TSSOP Package Outline...

  • Page 224: 20 Sop Package Information

    21. Package information A96G166/A96A166/A96S166 User’s manual 21.3 20 SOP package information Figure 128. 20 SOP Package Outline...

  • Page 225: 24 Qfn Package Information

    A96G166/A96A166/A96S166 User’s manual 21. Package information 21.4 24 QFN package information Figure 129. 24 QFN Package Outline...

  • Page 226: 28 Sop Package Information

    21. Package information A96G166/A96A166/A96S166 User’s manual 21.5 28 SOP package information Figure 130. 28 SOP Package Outline...

  • Page 227: 32 Lqfp Package Information

    A96G166/A96A166/A96S166 User’s manual 21. Package information 21.6 32 LQFP package information Figure 131. 32 LQFP Package Outline...

  • Page 228: 22 Development Tools

    ABOV semiconductor does not provide any compiler for A96G166/A96A166/A96S166. It is recommended to consult a compiler provider. Since A96G166/A96A166/A96S166 has Mentor 8051 as its core, and ROM is smaller than 64Kbytes in size, a developer can use any standard 8051 compiler of other providers.

  • Page 229: Programmers

    22. Development tools 22.3 Programmers 22.3.1 E-PGM+ E-PGM+ USB is a single programmer. A user can program A96G166/A96A166/A96S166 directly using the E-PGM+. Figure 133. E-PGM+ (Single Writer) and Pinouts 22.3.2 OCD emulator OCD emulator allows a user to write code on the device too, since OCD debugger supports ISP (In System Programming).

  • Page 230: Flash Programming

    22.4 Flash programming Program memory of A96G166/A96A166/A96S166 is a flash type. This flash ROM is accessed through four pins such as DSCL, DSDA, VDD, and VSS in serial data format. For more information about flash memory programming, please refer to Chapter 19 Memory programming.

  • Page 231: Circuit Design Guide

    A96G166/A96A166/A96S166 User’s manual 22. Development tools 22.4.2 Circuit design guide When programming flash memory, the programming tool needs 4 signal lines, DSCL, DSDA, VDD, and VSS. If a user designs a PCB circuit, the user should consider the usage of these 4 signal lines for the on-board programming.

  • Page 232: On-Chip Debug System

    On-chip debug system A96G166/A96A166/A96S166 supports On-chip debug (OCD) system. We recommend to develop and debug program with A96G1 series. On-chip debug system of A96G166/A96A166/A96S166 can be used for programming the non-volatile memories and on-chip debugging. Detail descriptions for programming via the OCD interface can be found in this section.

  • Page 233: Two-Pin External Interface

    A96G166/A96A166/A96S166 User’s manual 22. Development tools 22.5.1 Two-pin external interface Basic transmission packet 10-bit packet transmission using two-pin interface.  1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge.  Parity is even of ‘1’ for 8-bit data in transmitter.

  • Page 234: Figure 138. Data Transfer On Twin Bus

    22. Development tools A96G166/A96A166/A96S166 User’s manual Packet transmission timing Figure 138. Data Transfer on Twin Bus Figure 139. Bit Transfer on Serial Bus Figure 140. Start and Stop Condition...

  • Page 235: Figure 141. Acknowledge On Serial Bus

    A96G166/A96A166/A96S166 User’s manual 22. Development tools Figure 141. Acknowledge on Serial Bus Figure 142. Clock Synchronization during Wait Procedure...

  • Page 236: Figure 143. Connection Of Transmission

    22. Development tools A96G166/A96A166/A96S166 User’s manual Connection of transmission Two-pin interface connection uses open-drain (wire-AND bidirectional I/O). Figure 143. Connection of Transmission...

  • Page 237: 23 Ordering Information

    A96G166/A96A166/A96S166 User’s manual 23. Ordering information 23 Ordering information Table 66. A96G166/A96A166/A96S166 Device Ordering Information Part number FLASH XRAM IRAM Timer Communication GPIO High Package Temperature (PWM) function 12-bit current Range USART (Channel) port A96G166KN 16KB 512 bytes 256bytes 15 inputs 32 LQFP -40C~+85C...

  • Page 238: Figure 144. A96G166/A96A166/A96S166 Device Numbering Nomenclature

    23. Ordering information A96G166/A96A166/A96S166 User’s manual A96G166 K N ( ) N (T) A96G166 Family Name Application General Special Pin Count 32 pin 28 pin 24 pin 20 pin Package Type LQFP 0.8mm Pin Pitch TSSOP Temperature none -40°C ~ 85°C -40°C ~ 105°C...

  • Page 239: Appendix

    A96G166/A96A166/A96S166 User’s manual Appendix Appendix Instruction table Instructions are either1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
  • Page 240 Appendix A96G166/A96A166/A96S166 User’s manual Table 67. Instruction Table (continued) LOGICAL Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data...
  • Page 241 A96G166/A96A166/A96S166 User’s manual Appendix Table 67. Instruction Table (continued) DATA TRANSFER Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7 MOV A,#data...
  • Page 242 Appendix A96G166/A96A166/A96S166 User’s manual Table 67. Instruction Table (continued) BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit...
  • Page 243 A96G166/A96A166/A96S166 User’s manual Appendix Table 67. Instruction Table (continued) BRANCHING Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...
  • Page 244 Appendix A96G166/A96A166/A96S166 User’s manual Table 67. Instruction Table (continued) MISCELLANEOUS Mnemonic Description Bytes Cycles Hex code No operation ADDITIONAL INSTRUCTIONS (selected through EO[7:4]) Mnemonic Description Bytes Cycles Hex code MOVC M8051W/M8051EW-specific instruction supporting @(DPTR++), software download into program memory TRAP...

  • Page 245: Revision History

    Corrected symbol package type Figure 144. A96G166/A96A166/A96S166 Device Numbering Nomenclature. Added 16 SOPN package at Figure 2. A96G166 16SOPN Pin Assignment, Table 2. Normal Pin Description and Figure 126 16 SOPN Package Outline. Added A96G166AE at Table 66. A96G166/A96A166/A96S166 Device...
  • Page 246 Modified the bit position of EIPOL1 at 6.11.6 Interrupt register description. Modified invalid number USART Table A96G166/A96A166/A96S166 Device Features and Peripheral Counts. 2021.04.02 1.11 Corrected the typo of P3FSRL and IE2 at 5.5.2 Register description for P3 and 6.11.1 Interrupt Enable Register (IE, IE1, IE2, and IE3). 2021.04.22 1.12 Corrected the description of CONFIGURE OPTION 1 register at 19.6...
  • Page 247 ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders.

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