Sharp CD-K1861V Service Manual page 50

CD-K1861V
IC2 VHiLC78631E-1: Servo/Signal Control (LC78631E) (2/2)
Pin
Terminal Name Input/Output
No.
51 XVSS
52 XOUT
53 XIN
54 XVDD
55 RVSS
56 RCHN
57 RCHP
58* RVDD
59* MUTER
60* SBSY
61* EFLG
62* PW
63* SFSY
64 SBCK
65* DOUT
66* FSX
67 WRQ
68 RWC
69 SQOUT
70 COIN
71 CQCK
72 RES
73* TESEF
74* CONT2
75 16M
76 4.2M
77 TEST5
78 CS
79 DEFI
80 VCOC
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note: The same potential must be to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
Unused input ports of general-purpose input/output ports (I/O) must be connected to 0V or set output port.
V/P
15
CLV+,CLV- 13
14
FSEO 22
21
PCK
EFMO
9
EFMI
11
DEFI
79
PDO1,PDO2 2,
3
FR,ISET
5,
7
FAST
VPDO
1
80
VCOC
— Crystal osccillator garound. Normaly 0v.
Output 16.9344 MHz crystal oscillator connections. Use a 33.8688 MHz Crystal oscillator for quadspeed playback.
Input 16.9344 MHz crystal oscillator connections. Use a 33.8688 MHz Crystal oscillator for quadspeed playback.
— Crystal oscillator power supply.
—
Output
One-bit D/A
Output
converter pins
—
Output
Output Subcode block synchronization signal output.
Output C1 and C2 error correction state monitor.
Output Subcode P,Q,R,S,T,U and W output.
Output Subcode frame synchronization signal output. Falls when the subcode output goes to the standby state.
Input Subcode readout clock input. This is a Schmitt input.
Output Digital output.
Output Outputs a 7.35 kHz synchronization signal generated by dividing the crystal oscillator frequency.
Output Subcode Q outputstandby output.
Input Read/write control input.
Output Subcode Q output.
Input Input for commands from the control microprocessor.
Input Command input acousition clock. Also used as the SQOUT subcode readout clock input.
This is a Schmitt input.
Input Chip reset input. This pin must be set low temporary when power is first applled.
Output
Output Output port.
Output 16.9344 MHz output. 33.8688 MHz output in 4x playback mode.
Output 4.2336 MHz output.
Input Test input. A pull-down resistor built in.
Input Chip select input. A pull-down resistor is built in.
Input Defect detection signal input.
Input Variable pitch VCO control input.
CLV
FRAME
SYNCHRONOUB
PROTECTION
FAST
PLL
DETECT
VARIABLE TJ
PITCHRO COMMAND
PKK
I/F
23,24,
52 53 19,20 28,29 30,31 78,68
25
Figure 50 BLOCK DIAGRAM OF IC
Function
Right channel ground. Normaly 0V.
Right channel N output.
Right channel P output.
Right channel power supply.
Right channel mute output.
ADDRESS
GENERATOR
DRAM
CIRC
EFM
COMPENSATION
(ECC)
DEMODULATION
SUB CODE
ANTI-SHOCK I/F
DEMODULATION
DE EMPHASIS
DOUT
64 60,62, 65 32
63,67,69
– 50 –
DATA
MUTE
PQRT
D-ATT
DAC
DF
34,35,
36
66,
FSX,EFLG
61
42,
LRSY,ROMXA,
43,
44,
CK2,C2F
45
MUTER
59
56,
RCHP,RCHN
57
48, LCHP,LCHN
49
46 MUTEL