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PIN DIAGRAM (MST9E19A)
RXCKN
1
RXCKP
2
GND
3
Pin 1
RX0N
4
RX0P
5
AVDD_DVI
6
RX1N
7
RX1P
8
GND
9
RX2N
10
RX2P
11
AVDD_DVI
12
REXT
13
DDCD_DA
14
DDCD_CK
15
HSYNC1
16
VSYNC1
17
RMID
18
VCLAMP
19
REFP
20
REFM
21
BIN1P
22
BIN1M
23
SOGIN1
24
GIN1P
25
GIN1M
26
RIN1P
27
RIN1M
28
BIN0M
29
BIN0P
30
GIN0M
31
GIN0P
32
SOGIN0
33
RIN0M
34
RIN0P
35
AVDD_ADC
36
GND
37
HSYNC0
38
VSYNC0
39
C1
40
Y1
41
C0
42
Y0
43
VCOM2
44
CVBS3
45
CVBS2
46
CVBS1
47
VCOM1
48
CVBS0
49
VCOM0
50
CVBSOUT
51
GND
52
Version 0.1
SXGA/WXGA+ LCD TV Controller with Video Decoder & 10-bit Dual LVDS Transmitter
Copyright © 2006 MStar Semiconductor, Inc. All rights reserved.
MST9E19A
Preliminary Data Sheet Version 0.1
PWM3
156
PWM2
155
DIGO[9]
154
DIGO[8]
153
GND
152
VDDP
151
DIGO[7]
150
DIGO[6]
149
DIGO[5]
148
DIGO[4]
147
DIGO[3]
146
DIGO[2]
145
DIGO[1]
144
DIGO[0]
143
VDDC
142
GND
141
VDDP
140
PWM_SENSE
139
PWM_DRV
138
PWM_FB
137
IRIN
136
INT
135
DDCA_CK
134
DDCA_DA
133
DDCR_CK
132
DDCR_DA
131
PWM1
130
PWM0
129
SAR3
128
127
SAR2
SAR1
126
SAR0
125
SDO
124
CSZ
123
122
SDI
SCK
121
GND
120
VDDP
119
ALE
118
RDZ
117
WRZ
116
AD[7]
115
114
AD[6]
113
AD[5]
AD[4]
112
AD[3]
111
AD[2]
110
AD[1]
109
108
AD[0]
VDDC
107
GND
106
AVDD_MEMPLL
105
5/19/2006
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