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Circuit Operating Descriptions
13-3-2 Processor Core
The ST20-C202 processor core is composed of the ST20C2+ CPU running at 243 MHz,
a diagnostic controller unit (for low intrusion, real-time debugging), memory (8 Kbyte
instruction cache, 8 Kbyte data cache and 4 Kbyte SRAM) and a 16 priority-level
interrupt controller. The instruction and data caches are 2-way set associative.
13-3-3 Memory Subsystem
The STi5100 has a local memory interface (LMI) and a flash and peripheral interface
(FMI).
The STi5100's local memory interface is used for all data requirements in unified
memory applications, including graphics, video and audio buffers. It provides 16-bit wide
DDR SDRAM support only at up to 166 MHz.
1) Local memory interface (LMI)
The LMI is a 16-bit wide DDR SDRAM interface with a peak bandwidth of 664
Mbyte/s (166 MHz). It supports one bank of 128-Mbit, 256-Mbit, or 512-Mbit DDR
SDRAM. The LMI provides a fully cacheable address space for data and instructions,
with data cacheability controlled in 512 Kbyte blocks for up to 8 Mbytes.
2) Flash and peripheral memory interface (FMI)
The FMI provides a glueless interface to SRAM, flash, SFlash. and peripherals, in up
to four configurable banks over a 16-bit wide interface. Bus cycle strobe timings can
be programmed from 0 to 15 phases for slower peripherals. The FMI output drive of
the STi5100 is programmable on a bus-by-bus basis. Support is provided for
connection to an ATAPI HDD.
13-4
Samsung Electronics
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