Linear Technology DC2520A Demo Manual page 9

DC2520A JUMPERS
Definitions
JP1: REF selects INT or EXT reference for the ADC. The
default setting is INT.
JP2: VCCIO sets the output levels at P1 to either 3.3V
or 2.5V. Use 2.5V to interface to the DC890 which is the
default setting. Use 3.3V to interface to the DC2026.
JP3: I/O selects LVDS or CMOS logic levels. The default
setting is CMOS. Only CMOS is currently supported.
DC2520A CONNECTORS
Definitions
P1: DC890 interface is used to communicate with the
DC890 controller.
J1: CLK provides the master clock for the DC2520A when
interfaced to the DC890.
J2: FPGA PROGRAM is used to program the FPGA. This
is for factory use only.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DEMO MANUAL DC2520A
JP4: EEPROM is for factory use only. The default posi-
tion is WP.
JP5-JP6: AIN0-AIN3 can be used to short individual AIN
inputs to ground or can be used drive the individual AIN
inputs. The default is to leave these open.
JP13-JP14: Coupling selects AC or DC coupling for V
and V . Default setting is DC.
IN2
JP15: Sets V for the single-end to differential drivers
CM
of AIN0-AIN3
J3: JTAG is for factory use only.
J4: DC590/DC2026 interface is used to communicate with
the DC2026 Linduino controller or DC590.
J5 and J6: Provide analog input voltages to AIN0-AIN3
of the ADC.
J7: Routes the signals of J5 and J6 to AIN0-AIN3.
IN1
dc2520af
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