Exar XRT86VL38 Manual

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MARCH 2005

GENERAL DESCRIPTION

The XRT86VL38 is an eight-channel 1.544 Mbit/s or

2.048 Mbit/s DS1/E1/J1 framer and LIU integrated

solution

featuring

Reconfigurable,

Redundancy).

interface is optimized with internal impedance, and

with the patented pad structure, the XRT86VL38

provides protection from power failures and hot

swapping.

The XRT86VL38 contains an integrated DS1/E1/J1

framer and LIU which provide DS1/E1/J1 framing and

error accumulation in accordance with ANSI/ITU_T

specifications. Each framer has its own framing

synchronizer and transmit-receive slip buffers. The

slip buffers can be independently enabled or disabled

as required and can be configured to frame to the

common DS1/E1/J1 signal formats.

Each Framer block contains its own Transmit and

Receive T1/E1/J1 Framing function. There are 3

Transmit HDLC controllers per channel which

encapsulate contents of the Transmit HDLC buffers

into LAPD Message frames. There are 3 Receive

HDLC controllers per channel which extract the

1. XRT86VL38 8-

IGURE

Local PCM

XRT86VL38

Highway

1 of 8-channels

Tx Serial

Clock

Rx Serial

Clock

8kHz sync

OSC

Back Plane

1.544-16.384 Mbit/s

System (Terminal) Side

Exar

Corporation 48720 Kato Road, Fremont CA, 94538

PRELIMINARY

technology

(Relayless,

The

physical

DS1 (T1/E1/J1) F

CHANNEL

External Data

Link Controller

Tx Overhead In

2-Frame

Tx Serial

Slip Buffer

Data In

Elastic Store

2-Frame

Rx Serial

Slip Buffer

Data Out

Elastic Store

PRBS

Performance

Generator &

Monitor

Analyser

Signaling &

Interface

JTAG

Alarms

INT

TxON

Memory

OCTAL T1/E1/J1 FRAMER/LIU COMBO

payload content of Receive LAPD Message frames

from the incoming T1/E1/J1 data stream and write the

contents into the Receive HDLC buffers. Each framer

also contains a Transmit and Overhead Data Input

port, which permits Data Link Terminal Equipment

direct access to the outbound T1/E1/J1 frames.

Likewise, a Receive Overhead output data port

permits Data Link Terminal Equipment direct access

to the Data Link bits of the inbound T1/E1/J1 frames.

The XRT86VL38 fully meets all of the latest T1/E1/J1

specifications:

E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/

E1.408-1990, AT&T TR 62411 (12-90) TR54016, and

ITU G-703, G.704, G706 and G.733, AT&T Pub.

43801, and ETS 300 011, 300 233, JT G.703, JT

G.704, JT G706, I.431. Extensive test and diagnostic

functions

include

Pseudo Random bit sequence (PRBS) test pattern

generation, Performance Monitor, Bit Error Rate

(BER) meter, forced error insertion, and LAPD

unchannelized data payload processing according to

ITU-T standard Q.921.

Applications and Features (next page)

/LIU C

RAMER

OMBO

Rx Overhead Out

Tx LIU

Tx Framer

Interface

LLB

Rx LIU

Rx Framer

Interface

LIU &

HDLC/LAPD

Loopback

Controllers

Control

DMA

Microprocessor

Interface

ALE_AS

µP

D[7:0]

A[14:0]

Select

RDY_DTACK

Intel/Motorola µP

Configuration, Control &

Status Monitor

•

(510) 668-7000

FAX (510) 668-7017

XRT86VL38

ANSI T1/E1.107-1988, ANSI T1/

Loop-backs,

Boundary

1:2 Turns Ratio

TTIP

TRING

1:1 Turns Ratio

RTIP

RRING

RxLOS

Line Side

•

www.exar.com

REV. P1.0.6

scan,

Table of Contents

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Summary of Contents for Exar XRT86VL38

Page 1 XRT86VL38 to the Data Link bits of the inbound T1/E1/J1 frames. provides protection from power failures and hot swapping. The XRT86VL38 fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/ The XRT86VL38 contains an integrated DS1/E1/J1 E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/...
Page 2 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 APPLICATIONS • High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems • SONET/SDH terminal or Add/Drop multiplexers (ADMs) • T1/E1/J1 add/drop multiplexers (MUX) • Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 •...
Page 3 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 • PRBS, QRSS, and Network Loop Code generation and detection • Programmable Interrupt output pin • Supports programmed I/O and DMA modes of Read-Write access • Each framer block encodes and decodes the T1/E1/J1 Frame serial data •...
Page 4 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 420 BALL - TAPE BALL GRID ARRAY (BOTTOM VIEW, SEE PIN LIST FOR DESCRIPTION) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 O O O O O O O O O O O O O O O O O O O O O O O O O O...
Page 5 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 484 BALL - SHRINK THIN BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION) O O O O O O O O O O O O O O O O O O O O O O...
Page 6: Table Of Contents
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 LIST OF PARAGRAPHS 1.0 PIN LISTS ..............................6 2.0 PIN DESCRIPTIONS ..........................14 3.0 MICROPROCESSOR INTERFACE BLOCK ..................52 3.1 OPERATING THE MICROPROCESSOR INTERFACE IN INTEL-ASYNCHRONOUS MODE ......53 3.1.1 THE INTEL-ASYNCHRONOUS READ-CYCLE ......................54 3.1.2 THE INTEL-ASYNCHRONOUS WRITE CYCLE ......................
Page 7 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 5.8.6 FLAG SEQUENCE ..............................327 5.8.7 ADDRESS FIELD ................................ 327 5.8.8 ADDRESS FIELD EXTENSION BIT (EA) ........................327 5.8.9 COMMAND OR RESPONSE BIT (C/R) ........................327 5.8.10 SERVICE ACCESS POINT IDENTIFIER (SAPI) ...................... 328 5.8.11 TERMINAL ENDPOINT IDENTIFIER (TEI) .......................
Page 8 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 9.1 DESCRIPTION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK ....356 9.1.1 BRIEF DISCUSSION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT XRT84V24 COMPATIBLE 2.048MBIT/S MODE ......................356 9.2 TRANSMIT/RECEIVE HIGH-SPEED BACK-PLANE INTERFACE ..............358 9.2.1 NON-MULTIPLEXED HIGH-SPEED MODE .......................
Page 9 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13.3 THE DS1 FRAMING STRUCTURE ....................... 416 13.4 T1 SUPER FRAME FORMAT (SF) ........................ 417 13.5 T1 EXTENDED SUPERFRAME FORMAT (ESF) ..................418 13.6 T1 NON-SIGNALING FRAME FORMAT ....................... 420 13.7 T1 DATA MULTIPLEXED FRAMING FORMAT (T1DM) ................420...
Page 10 Figure 38.: HDLC Controllers ............................323 Figure 39.: LAPD Frame Structure ..........................326 Figure 40.: Block Diagram of the DS1 Transmit Overhead Input Interface of the XRT86VL38 ........332 Figure 41.: DS1 Transmit Overhead Input Interface Timing in ESF Framing Format mode .......... 334 Figure 42.: DS1 Transmit Overhead Input Timing in N or SLC®96 Framing Format Mode ..........
Page 11 Figure 74.: Waveforms for Connecting the Receive Non-Multiplexed High-Speed Input Interface at MVIP 2.048Mbit/s, 4.096Mbit/s, and 8.192Mbit/s .......................... 360 Figure 75.: Interfacing XRT86VL38 Transmit to local terminal equipment using 16.384Mbit/s, HMVIP 16.384Mbit/s, and H.100 16.384Mbit/s ............................364 Figure 76.: Timing signal when the framer is running at Bit-Multiplexed 16.384Mbit/s mode ........364 Figure 77.: Waveforms for Connecting the Transmit Multiplexed High-Speed Input Interface at HMVIP And H.100...
Page 12: Figure 1.: Xrt86Vl38 8-Channel Ds1 (T1/E1/J1) Framer/Liu Combo
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Figure 105.: Generation of CAS Multi-frame Yellow Alarm by the CPE upon detection of “AIS16” pattern sent by the Repeater Figure 106.: Simple Diagram of DS1 System Model ..................... 402 Figure 107.: Generation of Yellow Alarm by the CPE upon detection of line failure ............403 Figure 108.: Generation of AIS by the Repeater upon detection of Yellow Alarm originated by the CPE .....
Page 13 Table 8:: The Roles of Various Microprocessor Interface Pins, when configured to operate in the Power PC Mode ..62 Table 7:: Motorola Asychronous Mode Microprocessor Interface Timing Specifications ..........62 Table 9:: XRT86VL38 Framer/LIU Register Map ......................67 Table 10:: Register Summary ............................68 Table 11:: Clock Select Register .............................
Page 14 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Table 56:: Receive Interface Speed when Multiplexed Mode is Enabled (TxMUXEN = 1) ........... 143 Table 57:: Receive Interface Control Register (RICR) - T1 Mode ................. 144 Table 58:: Receive Interface Speed When Multiplexed Mode is Disabled (TxMUXEN = 0) .......... 146 Table 59:: Receive Interface Speed when Multiplexed Mode is Enabled (TxMUXEN = 1) ...........
Page 15 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Table 116:: PMON T1/E1 Receive Change of Frame Alignment Counter ..............204 Table 117:: PMON LAPD T1/E1 Frame Check Sequence Error Counter 1 ..............205 Table 118:: T1/E1 PRBS Bit Error Counter MSB ......................205 Table 119:: T1/E1 PRBS Bit Error Counter LSB ......................
Page 16 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Table 176:: Microprocessor Register #703, Bit Description - Global Register 4 ............296 Table 177:: Microprocessor Register #704, Bit Description - Global Register 5 ............298 Table 178:: List of the Possible Conditions that can Generate Interrupts, in each Framer ..........300 Table 179:: Address of the Block Interrupt Status Registers ..................
Page 17: 1.0 Pin Lists
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 1.0 PIN LISTS 1: 420 B 1: 420 B 1: 420 B ABLE ABLE ABLE UMBER UMBER UMBER 1: 420 B ABLE UMBER TXOH0 TXCHN1_1 TRST RXSYNC2 DVDD18 RXCRCSYNC0 TXCHN0_4 DGND RXOHCLK0...
Page 18: Table 1:: 420 Ball List By Ball Number
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 1: 420 B 1: 420 B 1: 420 B 1: 420 B ABLE ABLE ABLE ABLE UMBER UMBER UMBER UMBER TXOHCLK2 RXCHN3_1 RVDD4 TRING6 TXCHN2_4 RRING2 TTIP4 TGND6 TXOH2 RGND2 TRING4 RTIP1...
Page 19 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 1: 420 B 1: 420 B 1: 420 B 1: 420 B ABLE ABLE ABLE ABLE UMBER UMBER UMBER UMBER AA24 REQ1 AD10 TXCHCLK6 DBEN AA25 TXCHN7_0 AD11 GPIO0_0 AA26 fADDR RXSYNC7...
Page 20 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 1: 420 B 1: 420 B ABLE ABLE UMBER UMBER AE16 TXCHCLK5 AF22 TXCHN4_1 AE17 RXOH5 AF23 TXOHCLK4 AE18 AF24 TXSYNC4 AE19 RXCASYNC5 AF25 TXOH4 AE20 TXCHN4_3 AF26 RXCHN4_2 AE21 RXCHCLK5 AE22...
Page 21: Table 2:: 484 Ball List By Ball Number
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 2: 484 B 2: 484 B 2: 484 B ABLE ABLE ABLE 2: 484 B ABLE UMBER UMBER UMBER UMBER TXMSYNC1 RXSERCLK0 TXOH2 AVDD_LV TXOH1 RXCHN0_2 RXOHCLK3 E1MCLKOUT TXSERCLK1 RXOH0 TRING0 MCLKIN...
Page 22 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 2: 484 B 2: 484 B 2: 484 B 2: 484 B ABLE ABLE ABLE ABLE UMBER UMBER UMBER UMBER RGND1 RTIP3 ADDR10 ADDR3 TTIP1 TVDD3 PTYPE2 TVDD7 RVDD1 TRING3 TRING7 RXOH3...
Page 23 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 2: 484 B 2: 484 B 2: 484 B 2: 484 B ABLE ABLE ABLE ABLE UMBER UMBER UMBER UMBER TXCHCLK6 RXLOS4 RXSER6 AB19 RXCHCLK5 RXCHN6_1 ACK0 AA10 RXCHN6_0 AB20 TXOHCLK4 TXSYNC5...
Page 24 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 2: 484 B 2: 484 B 2: 484 B 2: 484 B ABLE ABLE ABLE ABLE UMBER UMBER UMBER UMBER NO CONNECT PINS...
Page 25: 2.0 Pin Descriptions
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 2.0 PIN DESCRIPTIONS TRANSMIT SERIAL DATA INPUT 420 P 484 P IGNAL ESCRIPTION TxSER0/ Transmit Serial Data Input TxPOS0 This input pin along with TxSERCLK functions as the Transmit Serial input port to the T1/E1 framer block. These TxSERn pins, are used as the trans-...
Page 26 TxSERCLK is configured as input, users must provide a 1.544MHz clock TxSERCLK5/ AF15 AA12 rate to this input pin for T1 mode of operation. If the XRT86VL38 is config- TxLINECLK5 ured in E1 mode of operation, users must then provide a 2.048MHz clock TxSERCLK6/ rate to this input pin.
Page 27 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 TRANSMIT SERIAL DATA INPUT 420 P 484 P IGNAL ESCRIPTION TxSYNC0/ Transmit Single Frame Sync Pulse Input/Output TxNEG0 These TxSYNCn pins are used to indicate a single frame boundary for DS1 or E1 mode. In both DS1 or E1 mode, the single frame boundary TxSYNC1/ repeats every 125 microseconds.
Page 28 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 TRANSMIT SERIAL DATA INPUT 420 P 484 P IGNAL ESCRIPTION TxMSYNC0/ Multiframe Sync Pulse/Transmit Input Clock TxINCLK0 This pin is a multiplexed I/O pin. When the device is configured to be in standard rate mode, this signal indicates the multi-frame boundary.
Page 29 2. These 8 pins are internally pulled “Low” for each channel. TxCHCLK0 Transmit Channel Clock Output Signal TxCHCLK1 The exact function of this pin depends on whether or not the XRT86VL38 is configured to use the transmit fractional/signaling interface to input frac- TxCHCLK2 tional data.
Page 30 Input: TxSIG0 The exact function of these pins depends on whether or not the TxCHN1_0/ XRT86VL38 is configured to use the transmit fractional/signaling interface. TxSIG1 The two different functions are described below: TxCHN2_0/ If transmit fractional/signaling interface is not used - Transmit Time Slot...
Page 31 Fractional Input: TxFrTD0 The exact function of these pins depends on whether or not the TxCHN1_1/ XRT86VL38 is configured to use the transmit fractional/signaling interface. TxFrTD1 The two different functions are described below: TxCHN2_1/ If transmit fractional/signaling interface is not used - Transmit Time...
Page 32 Synchronization Pulse: TxOHSYNC0 The exact function of these pins depends on whether or not the TxCHN1_3/ XRT86VL38 is configured to use the transmit fractional/signaling interface. TxOHSYNC1 The two different functions are described below: TxCHN2_3/ If transmit fractional/signaling interface is not used - Transmit Time...
Page 33 TxOH0 Transmit Overhead Input TxOH1 This input pin, along with TxOHCLK functions as the Transmit Over- head input port to the XRT86VL38 device. The exact function of TxOH2 these pins depends on whether or not the XRT86VL38 device is TxOH3...
Page 34 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 TRANSMIT AND RECEIVE OVERHEAD INTERFACE 420 P 484 P IGNAL ESCRIPTION TxOHCLK0 Transmit OH Serial Clock Output Signal TxOHCLK1 This output clock signal functions as a demand clock signal for the transmit overhead data input interface block.
Page 35 This output pin, along with RxOHCLK functions as the Receive Overhead output port to the XRT86VL38 device. The exact function RxOH2 of these pins depends on whether or not the XRT86VL38 device is RxOH3 configured to use the RxOHn pins for the destination of Datalink bits...
Page 36 RxOHCLK0 Receive OH Serial Clock Output Signal RxOHCLK1 This pin, along with the RxOHn pins functions as the Receive Over- head Output Interface for the XRT86VL38 device. RxOHCLK2 DS1 Mode RxOHCLK3 If the RxOH pins have been configured to be the destination for the...
Page 37 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 RECEIVE SERIAL DATA OUTPUT 420 P 484 P IGNAL ESCRIPTION RxSYNC0/ Receive Single Frame Sync Pulse Input/Output RxNEG0 These RxSYNCn pins are used to indicate a single frame boundary for DS1 or E1 mode. In both DS1 or E1 mode, the single frame RxSYNC1/ boundary repeats every 125 microseconds.
Page 38 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 RECEIVE SERIAL DATA OUTPUT 420 P 484 P IGNAL ESCRIPTION RxCASYNC0 Receive CAS Multiframe Sync Output Signal - E1 Mode Only RxCASYNC1 The RxCASYNCn pins are used to indicate the E1 CAS Multif-frame boundary.
Page 39 This clock signal is used by the Receive payload data output Inter- face to update the contents on the RxSERn pins. When the RxSERCLK1/ XRT86VL38 is configured in the standard rate mode, data applied to RxLINECLK1 the RxSER pin can be updated on either the rising edge or the falling...
Page 40 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 RECEIVE SERIAL DATA OUTPUT 420 P 484 P IGNAL ESCRIPTION RxSERCLK0/ (Continued) RxLINECLK0 DS1/E1 Multiplexed High-Speed Backplane Interface (RxSER- CLK as Input Only) RxSERCLK1/ In the multiplexed high-speed interface mode, this pin is used as the...
Page 41 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 RECEIVE SERIAL DATA OUTPUT 420 P 484 P IGNAL ESCRIPTION RxSER0/ Receive Serial Data Output RxPOS0 This output pin along with RxSERCLK functions as the Receive Serial output port from the T1/E1 framer block. These RxSERn pins,...
Page 42 Signaling Input: RxSig0 The exact function of these pins depends on whether or not the RxCHN1_0/ XRT86VL38 is configured to use the receive fractional/signaling RxSig1 interface. The two different functions are described below: RxCHN2_0/ If Receive fractional/signaling interface is not used - Receive Time...
Page 43 Fractional Input: RxFrTD0 The exact function of these pins depends on whether or not the RxCHN1_1/ XRT86VL38 is configured to use the receive fractional/signaling RxFrTD1 interface. The two different functions are described below: RxCHN2_1/ If receive fractional/signaling interface is not used - Receive...
Page 44 Slot Identifier Serial Output: RxCHN0 The exact function of these pins depends on whether or not the RxCHN1_2/ XRT86VL38 is configured to use the receive fractional/signaling RxCHN1 interface. The two different functions are described below: RxCHN2_2/ If receive fractional/signaling interface is not used - Receive...
Page 45 Line Clock Output: RxSCLK0 The exact function of these pins depends on whether or not the RxCHN1_4/ XRT86VL38 is configured to use the receive fractional/signaling RxSCLK1 interface. The two different functions are described below: RxCHN2_4/ If receive fractional/signaling interface is not used - Receive...
Page 46 RTIP input pin. RxLOS_0 Receive Loss of Signal Output Indicator RxLOS_1 The XRT86VL38 device will assert this output pin (i.e., toggle it “high”) anytime (and for the duration that) the Receive DS1/E1 RxLOS_2 Framer or LIU block declares the LOS defect condition.
Page 47 TTIP1 TTIP is the positive differential output to the line interface. This out- put pin, along with the corresponding TRING output pin, function as TTIP2 the Transmit DS1/E1 output signal drivers for the XRT86VL38 TTIP3 device. TTIP4 The user is expected to connect this signal and the corresponding...
Page 48 TRING1 TRING is the negative differential output to the line interface. This output pin, along with the corresponding TTIP output pin, function as TRING2 the Transmit DS1/E1 output signal drivers for the XRT86VL38 TRING3 device. TRING4 The user is expected to connect this signal and the corresponding...
Page 49 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 TIMING INTERFACE 420 P 484 P IGNAL ESCRIPTION T1MCLKnOUT LIU T1 Output Clock Reference This output pin is defaulted to 1.544MHz, but can be programmed to output 3.088MHz, 6.176MHz, or 12.352MHz in register 0x0FE4.
Page 50 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 GPIO CONTROL 420 P 484P IGNAL ESCRIPTION GPIO1_3 General Purpose Input/Output Pins GPIO1_2 Each of these pins can be configured to function as either a general- purpose input or output pin. The exact function of these pins depend...
Page 51 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 JTAG The XRT86VL38 device’s JTAG features comply with the IEEE 1149.1 standard. Please refer to the industry specification for additional information on boundary scan operations. 420 P 484P IGNAL ESCRIPTION Test clock: Boundary Scan Test clock input: The TCLK signal is the clock for the TAP controller, and it generates the boundary scan data register clocking.
Page 52 T1/E1 Framer. On the transmit side (i.e., To transmit data from external DMA con- troller to HDLC buffers within the XRT86VL38), DMA transfers are only requested when the transmit buffer status bits indicate that there is space for a complete message or cell.
Page 53 PTYPE0 Microprocessor Type Input: PTYPE1 These input pins permit the user to specify which type of Micropro- cessor/Microcontroller to be interfaced to the XRT86VL38 device. PTYPE2 The following table presents the three different microprocessor types that the XRT86VL38 supports. MICROPROCESSOR...
Page 54 Ready/Data Transfer Acknowledge Output: The exact behavior of this pin depends upon the type of Micropro- cessor/Microcontroller the XRT86VL38 has been configured to oper- ate in, as defined by the PTYPE[2:0] pins. Intel Type Microprocessors - RDY* - Ready Output...
Page 55 PTYPE[2:0] pins. Intel-Asynchronous Mode - ALE If the Microprocessor Interface of the XRT86VL38 device has been configured to operate in the Intel-Asynchronous Mode, then this active-high input pin is used to latch the address (present at the...
Page 56 Mode, then this input pin will function as the RD* (Active Low Read Strobe) input signal from the Microprocessor. Once this active- low signal is asserted, then the XRT86VL38 device will place the contents of the addressed register (or buffer location) on the Microprocessor Interface Bi-directional data bus (D[7:0]).
Page 57 The Microprocessor Interface will latch the contents on the Bi-Direc- tional Data Bus (into the “target” register or address location, within the XRT86VL38) upon the rising edge of this input pin. Motorola-Asynchronous Mode - R/W* - Read/Write Operation Identification Input Pin: If the Microprocessor Interface is operating in the “Motorola-Asyn-...
Page 58 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 MICROPROCESSOR INTERFACE 420 P 484P IGNAL ESCRIPTION ACK0 DMA Cycle Acknowledge Input—DMA Controller 0 (Write): The external DMA Controller will assert this input pin “Low” when the following two conditions are met: 1.
Page 59 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 POWER SUPPLY PINS (3.3V) 420 P 484P IGNAL ESCRIPTION Framer Block Power Supply (I/O) AC11 AE18 AD23 AA25 RVDD Receiver Analog Power Supply for LIU Section E1, H5, K6, L6, M7, N4, R5, T5...
Page 60 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 POWER SUPPLY PINS (1.8V) 420 P 484P IGNAL ESCRIPTION AVDD18 Analog Power Supply for LIU Section VDDPLL18 Analog Power Supply for PLL GROUND PINS 420 P 484P IGNAL ESCRIPTION Framer Block Ground...
Page 61 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 GROUND PINS 420 P 484P IGNAL ESCRIPTION DGND Digital Ground for LIU Section AGND Analog Ground for LIU Section RGND Receiver Analog Ground for LIU Section TGND Transmitter Analog Ground for LIU Section...
Page 62 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 NO CONNECT PINS 420 P 484P IGNAL ESCRIPTION No Connection...
Page 63: 3.0 Microprocessor Interface Block
5h (101) Power PC (Synchronous) The XRT86VL38 uses multipurpose pins to configure the device appropriately. The local µP configures the Framer/LIU by writing data into specific addressable, on-chip Read/Write registers. The microprocessor interface provides the signals which are required for a general purpose microprocessor to read or write data into these registers.
Page 64: Operating The Microprocessor Interface In Intel-Asynchronous Mode
(residing on the Address Bus) into the Microprocessor Interface circuitry of the XRT86VL38 device and to indicate the start of a READ or WRITE cycle. Pull- ing this input pin "high" enables the input bus drivers for the Address Bus input pins.
Page 65: The Intel-Asynchronous Read-Cycle
2. While the microprocessor is placing this address value on the Address Bus, the Address Decoding circuitry (within the user's system) should assert the CS* (Chip Select) pin of the XRT86VL38 device, by toggling it "low". This action enables further communication between the microprocessor and the XRT86VL38 Micro- processor Interface block.
Page 66: The Intel-Asynchronous Write Cycle
1. Place the address of the "target" register or buffer location on the Address Bus input pins, A[14:0]. While the microprocessor is placing the address value on the Address Bus, the Address Decoding circuitry (within the user's system) should assert the CS* (Chip Select) input pin of the XRT86VL38 device, by toggling it "low".
Page 67: Figure 4.: Intel Μp Interface Signals During Write Operations
7. After waiting the appropriate amount of time, for the data (on the bi-directional data bus) to stabilize and can be safely accepted by the microprocessor. At this time, the XRT86VL38 device will indicate that this data can be latched into the "target" address location, by toggling the RDY*/DTACK* output pin "low".
Page 68: Operating The Microprocessor Interface In The Motorola-Asynchronous Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 5. I µP I I/O R IGURE NTEL NTERFACE IMING URING ROGRAMMED EAD AND RITE PERATIONS READ OPERATION WRITE OPERATION ALE = 1 ADDR[14:0] Valid Address Valid Address Valid Data for Readback...
Page 69: The Motorola-Asynchronous Read-Cycle
If the Microprocessor Interface has been configured to operate in the Motorola-Asynchronous Mode, then the Microprocessor should do all of the following to perform a read operation: 1. Place the address of the "target" register within the XRT86VL38 device, on the Address Bus Input pins, A[14:0].
Page 70: The Motorola-Asynchronous Write-Cycle
6. Next the microprocessor should initiate the current bus cycle by toggling the RD*/DS* (Data Strobe) input pin "low". This step enables the bi-directional data bus output drivers, within the XRT86VL38 device. At this point, the bi-directional data bus output drivers will proceed to driver the contents of the "Address" reg- ister onto the bi-directional data bus, D[7:0].
Page 71 If the Microprocessor Interface (of the XRT86VL38 device) has been configured to operate in the Motorola- Asynchronous Mode, then the Microprocessor should do all of the following to perfrom a write operation: 1. Place the address of the "target" register or buffer location (within the XRT86VL38 device) on the Address Bus input pins, A[14:0].
Page 72: Figure 7.: Motorola Asychronous Mode Interface Signals During Write Operations
M ic ro p ro c e s so r to g g le s “R /W *” lo w T o D en o te W R IT E o pe ra tio n The figure and table below present timing information when the XRT86VL38 device is configured in motorola asychronous mode.
Page 73: Operating The Microprocessor Interface In The Powerpc 403 Mode
PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents on the Bi-Directional Data Bus (D[7:0]) into the "target" on-chip register or buffer location within the XRT86VL38 device. RDY*/ Active High READY Output - RDY...
Page 74: The Powerpc 403 Read-Cycle
READ Operation by making sure that the WR*/R/W* (R/W*) input pin is held at a logic "high". 2. 2. Place the address of the "target" register or buffer location (within the XRT86VL38 device) on the Address Bus input pin, A[14:0].
Page 75: The Powerpc 403 Write-Cycle
3. While the microprocessor is placing this address value on the Address Bus, the Address Decoding circuitry (within the user's system) should assert the CS* (Chip Select) pin of the XRT86VL38 device, by toggling it "low". This action enables further communication between the microprocessor and the XRT86VL38 Micro- processor Interface block.
Page 76 : As the Microprocessor/Address Decoding logic asserts the WR*/R/W* signal, the user should make sure that the Microprocessor/Address Decoding circuitry respects the "R/W* to Rising edge of PCLK Set-up time" requirements.) 2. Place the address of the "target" register or buffer location (within the XRT86VL38 device) on the Address Bus input pins, A[14:0].
Page 77: Dma Read/Write Operations
XRT86VL38 each time the WR (Write Strobe) input pin is strobed “Low”. The XRT86VL38 ends the DMA cycle by negating the DMA request input (REQ0) while WR is still active. The external DMA Controller acknowledges the end of DMA Transfer by driving the ACK0 input pin “High”.
Page 78: Memory Mapped I/O Addressing
ODE FOR THE AND A ICROPROCESSOR REQ[1:0] ACK[1:0] µ PCLK DATA[7:0] Microprocessor XRT86VL38 Memory Mapped I/O Addressing 9: XRT86VL38 F /LIU R ABLE RAMER EGISTER [13:0] DDRESS ONTENTS n100h - n1FFh Channel n - Control Register (Framer Block) n300h - n3FFh...
Page 79: Table 10: Register Summary
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 DESCRIPTION OF THE CONTROL REGISTERS 10: R ABLE EGISTER UMMARY UNCTION YMBOL Control Registers (0xn100 - 0xn1FF) Clock and Select Register 0xn100 T1/E1 Line Interface Control Register LICR 0xn101 T1/E1 General Purpose Input/Output Control...
Page 80 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 10: R ABLE EGISTER UMMARY UNCTION YMBOL Slip Buffer Control Register SBCR 0xn116 T1/E1 FIFO Latency Register FIFOLR 0xn117 T1/E1 DMA 0 (Write) Configuration Register D0WCR 0xn118 T1/E1 DMA 1 (Read) Configuration Register...
Page 81 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 10: R ABLE EGISTER UMMARY UNCTION YMBOL Receive Data Link Byte Count Register 2 RDLBCR2 0xn145 T1/E1 Data Link Control Register 3 DLCR3 0xn153 T1/E1 Transmit Data Link Byte Count Register 3...
Page 82 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 10: R ABLE EGISTER UMMARY UNCTION YMBOL 315- LAPD Buffer 0 Control Register LAPDBCR0 0xn600 T1/E1 0xn660 LAPDn Buffer 1 (0xn700 - 0xn760) 411- LAPD Buffer 1 Control Register LAPDBCR1 0xn700 T1/E1...
Page 83 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 10: R ABLE EGISTER UMMARY UNCTION YMBOL Alarm & Error Interrupt Enable Register AEIER 0xnB03 Alarm & Error Interrupt Enable Register 0xnB03 Framer Interrupt Status Register FISR 0xnB04 Framer Interrupt Status Register...
Page 84 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 10: R ABLE EGISTER UMMARY UNCTION YMBOL Channel 1 LIU Control Register C1LIUCR 0x0F10 T1/E1 0x0F1F Channel 2 LIU Control Register C2LIUCR 0x0F20 T1/E1 0x0F2F Channel 3 LIU Control Register C3LIUCR 0x0F30...
Page 85: Register Descriptions
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 3.4.1 Register Descriptions 11: C ABLE LOCK ELECT EGISTER 0 - T1/E1 M (CSR) n100 EGISTER LOCK ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION BPVI Bipolar Violation Insertion This READ/WRITE bit field is used to force a single Bipolar Violation (BPV) on the transmit output of TTIP/TRING.
Page 86: Table 11: Clock Select Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 11: C ABLE LOCK ELECT EGISTER 0 - T1/E1 M (CSR) n100 EGISTER LOCK ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1:0 CSS[1:0] Clock Source Select These READ/WRITE bit fields selects the transmit timing source for the Transmit Framer block.
Page 87 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 12: L ABLE NTERFACE ONTROL EGISTER 1 - T1/E1 M (LICR) n101 EGISTER NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 5:4 LB[1:0] Framer Loopback Selection These two READ/WRITE bit fields are used to select any of the follow- ing loop-back modes for the framer section.
Page 88: Table 13:: General Purpose Input/Output 0 Control Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 12: L ABLE NTERFACE ONTROL EGISTER 1 - T1/E1 M (LICR) n101 EGISTER NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Encode AMI/B8ZS Encode AMI or B8ZS/HDB3 Line Code Select This READ/WRITE bit field enables or disables the B8ZS/HDB3 encoder on the transmit path.
Page 89 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13: G ABLE ENERAL URPOSE NPUT UTPUT ONTROL EGISTER (GPIOCR0) 0102 EGISTER ENERAL URPOSE NPUT UTPUT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION GPIO0_1DIR GPIO0_1 Direction This READ/WRITE bit-field permits the user to define the General Pur- pose I/O Pin, GPIO0_1 as either in Input pin or an Output pin, as described below.
Page 90 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13: G ABLE ENERAL URPOSE NPUT UTPUT ONTROL EGISTER (GPIOCR0) 0102 EGISTER ENERAL URPOSE NPUT UTPUT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION GPIO0_2 GPIO0_2 Control The exact function of this bit-field depends upon whether General Pur- pose I/O Pin, GPIO0_2 has been configured to function as an input or an output pin, as described below.
Page 91 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13: G ABLE ENERAL URPOSE NPUT UTPUT ONTROL EGISTER (GPIOCR0) 0102 EGISTER ENERAL URPOSE NPUT UTPUT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION GPIO0_1 GPIO0_1 Control The exact function of this bit-field depends upon whether General Pur- pose I/O Pin, GPIO0_1 has been configured to function as an input or an output pin, as described below.
Page 92 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 14: G ABLE ENERAL URPOSE NPUT UTPUT ONTROL EGISTER (GPIOCR1) 4102 EGISTER ENERAL URPOSE NPUT UTPUT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION GPIO1_3DIR GPIO1_3 Direction This READ/WRITE bit-field permits the user to define the General Pur- pose I/O Pin, GPIO1_3 as either in Input pin or an Output pin, as described below.
Page 93 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 14: G ABLE ENERAL URPOSE NPUT UTPUT ONTROL EGISTER (GPIOCR1) 4102 EGISTER ENERAL URPOSE NPUT UTPUT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION GPIO1_0DIR GPIO1_0 Direction This READ/WRITE bit-field permits the user to define the General Pur- pose I/O Pin, GPIO1_0 as either in Input pin or an Output pin, as described below.
Page 94: Table 14:: General Purpose Input/Output 1 Control Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 14: G ABLE ENERAL URPOSE NPUT UTPUT ONTROL EGISTER (GPIOCR1) 4102 EGISTER ENERAL URPOSE NPUT UTPUT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION GPIO1_2 GPIO1_2 Control The exact function of this bit-field depends upon whether General Pur- pose I/O Pin, GPIO1_2 has been configured to function as an input or an output pin, as described below.
Page 95 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 14: G ABLE ENERAL URPOSE NPUT UTPUT ONTROL EGISTER (GPIOCR1) 4102 EGISTER ENERAL URPOSE NPUT UTPUT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION GPIO1_1 GPIO1_1 Control The exact function of this bit-field depends upon whether General Pur- pose I/O Pin, GPIO1_1 has been configured to function as an input or an output pin, as described below.
Page 96: Table 15:: Framing Select Register-E1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 15: F -E1 M ABLE RAMING ELECT EGISTER 7- E1 M (FSR) n107 EGISTER RAMING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION MODENB Annex B Enable This READ/WRITE bit field forces the framing synchronizer to be compliant with ITU-T G.706 Annex B for CRC-to-non-CRC interwork-...
Page 97 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 15: F -E1 M ABLE RAMING ELECT EGISTER 7- E1 M (FSR) n107 EGISTER RAMING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION CASSEL(1) CAS Multiframe Alignment Algorithm Select These READ/WRITE bit fields allow the user to select which CAS...
Page 98 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 15: F -E1 M ABLE RAMING ELECT EGISTER 7- E1 M (FSR) n107 EGISTER RAMING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION CRCSEL(1) CRC Multiframe Alignment Criteria Select These two READ/WRITE bit fields allow the user to select which...
Page 99 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 15: F -E1 M ABLE RAMING ELECT EGISTER 7- E1 M (FSR) n107 EGISTER RAMING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FASSEL FAS Alignment Algorithm Select This READ/WRITE bit field specifies which algorithm the Receive E1 Framer block uses in its search for the FAS Alignment.
Page 100: Table 16:: Framing Select Register-T1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 16: F -T1 M ABLE RAMING ELECT EGISTER 7- T1 M (FSR) n107 EGISTER RAMING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SIGFRAME Enable Signaling Update This READ/WRITE bit-field enable or disable Signaling Update on the superframe boundary.
Page 101 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 16: F -T1 M ABLE RAMING ELECT EGISTER 7- T1 M (FSR) n107 EGISTER RAMING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FASTSYNC Faster Sync Algorithm This READ/WRITE bit-field is used to specify one of the synchroniza- tion criteria.
Page 102 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 17: A - E1 M ABLE LARM ENERATION EGISTER 8 -E1 M (AGR) n108 EGISTER LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION AUXPG AUXP Generation This READ/WRITE bit-field enables or disables the generation of AUXP pattern which is an unframed 1010….
Page 103: Table 17: Alarm Generation Register - E1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 17: A - E1 M ABLE LARM ENERATION EGISTER 8 -E1 M (AGR) n108 EGISTER LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION YEL(1) Yellow Alarm and Multiframe Yellow Alarm Generation These READ/WRITE bit-fields activate and deactivate the transmission YEL(0) of yellow alarm.
Page 104 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 17: A - E1 M ABLE LARM ENERATION EGISTER 8 -E1 M (AGR) n108 EGISTER LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION AISD(1) AIS Pattern Detection Select These Read/Write bit-fields are used to specify the types of AIS pattern...
Page 105: Table 18: Alarm Generation Register -T1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 18: A -T1 M ABLE LARM ENERATION EGISTER 8 - T1 M (AGR) n108 EGISTER LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION YEL(1) Yellow Alarm and Multiframe Yellow Alarm Generation The exact function of these READ/WRITE bit fields depends on whether or YEL(0) not the one second alarm rule is enforced.
Page 106 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 18: A -T1 M ABLE LARM ENERATION EGISTER 8 - T1 M (AGR) n108 EGISTER LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 5-4 YEL[1:0] (Continued) ABLE YELLOW ALARM DURATION AND FORMAT WHEN ONE SECOND...
Page 107 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 18: A -T1 M ABLE LARM ENERATION EGISTER 8 - T1 M (AGR) n108 EGISTER LARM ENERATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION AISG(1) AIS Generation Select These Read/Write bit-fields are used to specify the types of AIS pattern that AISG(0) the transmit T1 framer block will generate, as described in the table below.
Page 108 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 21: S MUX R - E1 M ABLE YNCHRONIZATION EGISTER 9 - E1 M MUX R (SMR) n109 EGISTER YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 ESRC[1:0] Source for E bits These READ/WRITE bit-fields determine where the source of the E bits that will be inserted in the outbound E1 frames.
Page 109 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 21: S MUX R - E1 M ABLE YNCHRONIZATION EGISTER 9 - E1 M MUX R (SMR) n109 EGISTER YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION DLSRC(1) Data Link Source Select These READ/WRITE bit fields are used to specify the source of the DLSRC(0) Data Link bits that will be inserted in the outbound E1 frames.
Page 110: Table 21: Synchronization Mux Register - E1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 21: S MUX R - E1 M ABLE YNCHRONIZATION EGISTER 9 - E1 M MUX R (SMR) n109 EGISTER YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION CRCSRC CRC-4 Bits Source Select This Read/Write bit-field is used to specify the source for the CRC-4 bits that will be inserted into the outbound E1 frames.
Page 111 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 22: S MUX R - T1 M ABLE YNCHRONIZATION EGISTER 9 - T1 M MUX R (SMR) n109 EGISTER YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION MSYNC Tx Super Frame Sync This READ/WRITE bit field determines the transmit single frame sync (TxSYNC) signal as being the transmit single frame sync (TxSYNC) or the superframe sync (TxMSYNC) signals.
Page 112 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 22: S MUX R - T1 M ABLE YNCHRONIZATION EGISTER 9 - T1 M MUX R (SMR) n109 EGISTER YNCHRONIZATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION CRCSRC CRC-6 Bits Source Select This Read/Write bit-field is used to specify the source for the CRC-6 bits that will be inserted into the outbound T1 frames.
Page 113: Table 23: Transmit Signaling And Data Link Select Register - E1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 23: T - E1 M ABLE RANSMIT IGNALING AND ELECT EGISTER 10 - E1 M (TSDLSR) n10A EGISTER RANSMIT IGNALING AND ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSa8ENB Transmit Sa8 Enable This READ/WRITE bit field specifies if the Sa8 bit-field (bit 7 within timeslot 0 of non-FAS frames) will be involved in the transmission of Data Link Information.
Page 114 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 23: T - E1 M ABLE RANSMIT IGNALING AND ELECT EGISTER 10 - E1 M (TSDLSR) n10A EGISTER RANSMIT IGNALING AND ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSa5ENB Transmit Sa5 Enable This READ/WRITE bit field specifies if the Sa5 bit-field (bit 4 within timeslot 0 of non-FAS frames) will be involved in the transmission of Data Link Information.
Page 115 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 23: T - E1 M ABLE RANSMIT IGNALING AND ELECT EGISTER 10 - E1 M (TSDLSR) n10A EGISTER RANSMIT IGNALING AND ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSIGDL(2) Transmit Signaling and Data Link Select:...
Page 116 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 23: T - E1 M ABLE RANSMIT IGNALING AND ELECT EGISTER 10 - E1 M (TSDLSR) n10A EGISTER RANSMIT IGNALING AND ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION (Continued) 2-0 TxSIGDL[2:0] SIGDL...
Page 117: Table 24:: Transmit Signaling And Data Link Select Register - T1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 24: T - T1 M ABLE RANSMIT IGNALING AND ELECT EGISTER 10 - T1 M (TSDLSR) n10A EGISTER RANSMIT IGNALING AND ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved Reserved Reserved Reserved...
Page 118 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 24: T - T1 M ABLE RANSMIT IGNALING AND ELECT EGISTER 10 - T1 M (TSDLSR) n10A EGISTER RANSMIT IGNALING AND ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxDL[1] DL Select These two READ/WRITE bit-fields specifies the source for data link TxDL[0] bits that will be inserted in the outbound T1 frames.
Page 119 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 25: F E1 M ABLE RAMING ONTROL EGISTER 11 -- E1 M (FCR) n10B EGISTER RAMING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION CASC(1) Loss of CAS Multiframe Alignment Declaration Criteria Select...
Page 120: Table 25: Framing Control Register E1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 25: F E1 M ABLE RAMING ONTROL EGISTER 11 -- E1 M (FCR) n10B EGISTER RAMING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION CRCC(1) Loss of CRC-4 Multiframe Alignment Criteria Select These two Read/Write bits are used to select the Loss of CRC-4 Multi- CRCC(0) frame Alignment Declaration criteria.
Page 121 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 25: F E1 M ABLE RAMING ONTROL EGISTER 11 -- E1 M (FCR) n10B EGISTER RAMING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FASC(2) Loss of FAS Alignment Criteria Select These three Read/Write bits are used to select the Loss of FAS Align- FASC(1) ment Declaration criteria.
Page 122 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 26: F T1 M ABLE RAMING ONTROL EGISTER 11 -- T1 M (FCR) n10B EGISTER RAMING ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TOLR[2] Tolerance Bits [2:0] These three READ/WRITE bit-fields along with the RANG[2:0] bits are TOLR[1] used to form the declaration criteria for loss of frame alignment.
Page 123 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 27: R & D - E1 M ABLE ECEIVE IGNALING ELECT EGISTER 12 - E1 M & D (RSDLSR) n10C EGISTER ECEIVE IGNALING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxSa5ENB Receive Sa5 Enable...
Page 124 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 27: R & D - E1 M ABLE ECEIVE IGNALING ELECT EGISTER 12 - E1 M & D (RSDLSR) n10C EGISTER ECEIVE IGNALING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxSIGDL(2) Receive Signaling and Datalink Select:...
Page 125 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 27: R & D - E1 M ABLE ECEIVE IGNALING ELECT EGISTER 12 - E1 M & D (RSDLSR) n10C EGISTER ECEIVE IGNALING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION (Continued) 2-0 RxSIGDL...
Page 126 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 28: R & D (RSDLSR) T1 M ABLE ECEIVE IGNALING ELECT EGISTER 12 - T1 M & D (RSDLSR) n10C EGISTER ECEIVE IGNALING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxDLBW[1] Receive Data Link Bandwidth...
Page 127 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 28: R & D (RSDLSR) T1 M ABLE ECEIVE IGNALING ELECT EGISTER 12 - T1 M & D (RSDLSR) n10C EGISTER ECEIVE IGNALING ELECT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxDL[1] DataLink Select...
Page 128 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 30: S 1 - T1/E1 M ABLE IGNALING HANGE EGISTER 14 T1/E1 M 1 (SCR 1) n10E EGISTER IGNALING HANGE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Ch.8 These Reset Upon Read bits indicate whether the signaling data asso- ciated with Channels 8-15 has changed since the last read of this regis- Ch.9...
Page 129 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 32: S 3 - E1 M ABLE IGNALING HANGE EGISTER 33: R 16 - E1 M 3 (SCR 3) ABLE EGISTER IGNALING HANGE EGISTER n110 DDRESS UNCTION EFAULT ESCRIPTION PERATION Ch.24 These Reset Upon Read bits indicate whether the signaling data associated with Channels 24-31 has changed since the last read of Ch.25...
Page 130: Table 35:: Receive Extra Bits Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 34: R ABLE ECEIVE ATIONAL EGISTER (RNBR) n111 EGISTER ECEIVE ATIONAL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Received National Bits These Read Only bit-fields contain the values of the National bits within the most recently received non-FAS frame.
Page 131 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 35: R ABLE ECEIVE XTRA EGISTER (REBR) n112 EGISTER ECEIVE XTRA EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Extra Bit 2 (E1 Mode Only) This READ ONLY bit field is used to indicate the most recently received Extra Bit value (bit 7 within timeslot 16 of frame 0 of the signaling multi- frame).
Page 132: Table 36: Data Link Control Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 36: D ABLE ONTROL EGISTER 1 (DLCR1) n113 EGISTER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLC-96 SLC®96 Enable, 6 bit for ESF This READ/WRITE bit-field is used to enable or disable SLC®96 data link message transmission.
Page 133 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 36: D ABLE ONTROL EGISTER 1 (DLCR1) n113 EGISTER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Tx_ABORT Transmit ABORT This READ/WRITE bit-field configures the Transmit HDLC1 Control- ler to transmit an ABORT sequence (string of 7 or more consecutive 1’s) to the Remote terminal.
Page 134 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 37: T ABLE RANSMIT OUNT EGISTER 1 (TDLBCR1) n114 EGISTER RANSMIT OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION BUFAVAL//BUFSEL Transmit HDLC1 Buffer Available/Buffer Select This READ/WRITE bit-field has two functions. When this bit is being written, it specifies which one of the two Transmit HDLC1 Buffers has been loaded for transmission.
Page 135: Table 39:: Slip Buffer Control Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 38: R ABLE ECEIVE OUNT EGISTER 1 (RDLBCR1) n115 EGISTER ECEIVE OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RDLBC6 Receive HDLC Message - byte count The exact function of these bits depends on whether the Receive RDLBC5 HDLC 1 Controller is configured to receive MOS or BOS messages.
Page 136: Table 40:: Fifo Latency Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 39: S ABLE UFFER ONTROL EGISTER (SBCR) n116 EGISTER UFFER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SB_SDIR Slip Buffer (RxSync) Direction Select This READ/WRITE bit field selects the direction of the receive frame boundary (RxSYNC) signal if the receive buffer is not bypassed.
Page 137: Table 41:: Dma 0 (Write) Configuration Register
4 - 3 Reserved Reserved DMA0_CHAN(2) Channel Select These three READ/WRITE bit-fields select which T/E1 channel within DMA0_CHAN(1) the XRT86VL38 uses the Transmit DMA_0 (Write) interface. 000 = Channel 0 DMA0_CHAN(0) 001 = Channel 1 001 = Channel 2 011 = Channel 3...
Page 138 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 42: DMA 1 (R ABLE ONFIGURATION EGISTER DMA 1 (R (D1CR) n119 EGISTER ONFIGURATION EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-6 Reserved Reserved DMA1 RST DMA_1 Reset This READ/WRITE bit-field resets the Receive DMA (Read) Channel 1 0 = Normal operation.
Page 139: Table 43:: Interrupt Control Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 43: I ABLE NTERRUPT ONTROL EGISTER (ICR) n11A EGISTER NTERRUPT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-3 Reserved Reserved INT_WC_RUR Interrupt Write-to-Clear or Reset-upon-Read Select This READ/WRITE bit-field configures all Interrupt Status bits to be either Reset Upon Read or Write-to-Clear 0=Setting this bit to ‘0’...
Page 140: Table 45:: Customer Installation Alarm Generation Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 45: C ABLE USTOMER NSTALLATION LARM ENERATION EGISTER 28 - T1 (CIAGR) n11C USTOMER NSTALLATION LARM ENERATION EGISTER EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION [7:4] Reserved Reserved [3:2] CIAG CI Alarm Transmit (Only in ESF) These two READ/WRITE bit-fields are used to enable or disable AIS-CI or RAI-CI generation.
Page 141: Table 46:: Performance Report Control Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 46: P ABLE ERFORMANCE EPORT ONTROL EGISTER 29 - T1 (PRCR) n11D ERFORMANCE EPORT ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION LBO_ADJ_ENB Transmit Line Build Out Auto Adjustment: This READ/WRITE bit-field is used to enable or disable the transmit line build out auto adjustment feature.
Page 142: Table 47: Gapped Clock Control Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 47: G ABLE APPED LOCK ONTROL EGISTER 30 - T1/E1 (GCCR) n11E APPED LOCK ONTROL EGISTER EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FrOutclk Framer Output Clock Reference This READ/WRITE bit-field is used to enable or disable high-speed T1/E1 rate on the T1OSCCLK and the E1OSCCLK output pins.
Page 143: Table 48: Transmit Interface Control Register - E1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 48: T - E1 M ABLE RANSMIT NTERFACE ONTROL EGISTER 31 - E1 M (TICR) n120 EGISTER RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSyncFrD Transmit Synchronous fraction data interface...
Page 144 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 48: T - E1 M ABLE RANSMIT NTERFACE ONTROL EGISTER 31 - E1 M (TICR) n120 EGISTER RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxICLKINV Transmit Clock Inversion This READ/WRITE bit-field selects whether data transition will happen on the rising or falling edge of the transmit clock.
Page 145: Table 49: Transmit Interface Speed When Multiplexed Mode Is Disabled (Txmuxen = 0)
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 48: T - E1 M ABLE RANSMIT NTERFACE ONTROL EGISTER 31 - E1 M (TICR) n120 EGISTER RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxIMODE[1] Transmit Interface Mode selection This READ/WRITE bit-field determines the transmit interface speed.
Page 146: Table 50: Transmit Interface Speed When Multiplexed Mode Is Enabled (Txmuxen = 1)
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 48: T - E1 M ABLE RANSMIT NTERFACE ONTROL EGISTER 31 - E1 M (TICR) n120 EGISTER RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 TxIMODE[1:0] (Continued): 50: T ABLE...
Page 147 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 51: T - T1 M ABLE RANSMIT NTERFACE ONTROL EGISTER 31 - T1 M (TICR) n120 EGISTER RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSyncFrD Tx Synchronous fraction data interface This READ/WRITE bit-field selects whether TxCHCLK or TxSERCLK will be used for fractional data input if fractional interface is enabled.
Page 148 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 51: T - T1 M ABLE RANSMIT NTERFACE ONTROL EGISTER 31 - T1 M (TICR) n120 EGISTER RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxFr1544 Fractional/Signaling Interface Enabled This READ/WRITE bit-field is used to enable or disable the transmit fractional data interface, signaling input, as well as the 32MHz transmit clock and the transmit overhead Signal output.
Page 149: Table 51: Transmit Interface Control Register - T1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 51: T - T1 M ABLE RANSMIT NTERFACE ONTROL EGISTER 31 - T1 M (TICR) n120 EGISTER RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxIMODE[1] Transmit Interface Mode selection This READ/WRITE bit-field determines the transmit interface speed. The...
Page 150 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 51: T - T1 M ABLE RANSMIT NTERFACE ONTROL EGISTER 31 - T1 M (TICR) n120 EGISTER RANSMIT NTERFACE ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 1-0 TxIMODE[1:0] (Continued) 53: T ABLE...
Page 151: Table 54: Receive Interface Control Register (Ricr) - E1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 54: R (RICR) - E1 M ABLE ECEIVE NTERFACE ONTROL EGISTER 32 - E1 M (RICR) EGISTER ECEIVE NTERFACE ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION RxSyncFrD Receive Synchronous fraction data interface This READ/WRITE bit-field selects whether RxCHCLK or RxSERCLK will be used for fractional data output if receive fractional interface is enabled.
Page 152 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 54: R (RICR) - E1 M ABLE ECEIVE NTERFACE ONTROL EGISTER 32 - E1 M (RICR) EGISTER ECEIVE NTERFACE ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION RxICLKINV Receive Clock Inversion This READ/WRITE bit-field selects whether data transition will happen on the rising or falling edge of the receive clock.
Page 153 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 54: R (RICR) - E1 M ABLE ECEIVE NTERFACE ONTROL EGISTER 32 - E1 M (RICR) EGISTER ECEIVE NTERFACE ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION RxIMODE[1] Receive Interface Mode Selection This READ/WRITE bit-field determines the receive interface speed. The...
Page 154 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 54: R (RICR) - E1 M ABLE ECEIVE NTERFACE ONTROL EGISTER 32 - E1 M (RICR) EGISTER ECEIVE NTERFACE ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION 1-0 RxIMODE (Continued): 56: R ABLE ECEIVE...
Page 155 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 57: R (RICR) - T1 M ABLE ECEIVE NTERFACE ONTROL EGISTER 32 - T1 M (RICR) EGISTER ECEIVE NTERFACE ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION RxSyncFrD Receive Synchronous fraction data interface This READ/WRITE bit-field selects whether RxCHCLK or RxSERCLK will be used for fractional data output if receive fractional interface is enabled.
Page 156: Table 57: Receive Interface Control Register (Ricr) - T1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 57: R (RICR) - T1 M ABLE ECEIVE NTERFACE ONTROL EGISTER 32 - T1 M (RICR) EGISTER ECEIVE NTERFACE ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION RxFr1544 Receive Fractional/Signaling Interface Enabled This READ/WRITE bit-field is used to enable or disable the receive fractional output interface, receive signaling output, the serial channel number output, as well as the 8kHz and the received recovered clock output.
Page 157 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 57: R (RICR) - T1 M ABLE ECEIVE NTERFACE ONTROL EGISTER 32 - T1 M (RICR) EGISTER ECEIVE NTERFACE ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION RxIMODE[1] Receive Interface Mode Selection This READ/WRITE bit-field determines the receive interface speed. The...
Page 158 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 57: R (RICR) - T1 M ABLE ECEIVE NTERFACE ONTROL EGISTER 32 - T1 M (RICR) EGISTER ECEIVE NTERFACE ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION 1-0 RxIMODE[1:0] (Continued):( 59: R ABLE ECEIVE...
Page 159 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 60: DS1/E1 T ABLE EGISTER DS1/E1 T 1 (TR1) EGISTER EGISTER UNCTION EFAULT ESCRIPTION PERATION PRBSTyp PRBS Pattern Type This READ/WRITE bit-field selects the type of PRBS pattern that the T1/E1 Transmit/Receive framer will generate or detect. PRBS 15...
Page 160 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 60: DS1/E1 T ABLE EGISTER DS1/E1 T 1 (TR1) EGISTER EGISTER UNCTION EFAULT ESCRIPTION PERATION DATAInv PRBS Data Invert: This READ/WRITE bit-field inverts the Transmit PRBS/QRTS output data and the Receive PRBS/QRTS input data. The exact function of this bit depends on whether PRBS switch function is enabled or not.
Page 161 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 60: DS1/E1 T ABLE EGISTER DS1/E1 T 1 (TR1) EGISTER EGISTER UNCTION EFAULT ESCRIPTION PERATION TxPRBSEnb Transmit PRBS Generation Enable This READ/WRITE bit-field enables or disables the Transmit PRBS pattern generator. The exact function of this bit depends on whether PRBS switch function is enabled or not.
Page 162: Table 61: Ds1/E1 Test Register 2(Tr2)
PRBS_Switch PRBS Switch This READ/WRITE bit-field enables or disables the PRBS switch function within the XRT86VL38 device. By enabling the PRBS switch function, PRBS functionality will switch from the line side to the backplane interface. T1/E1 Receive framer will generate the PRBS pattern and insert it onto the receive...
Page 163 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 61: DS1/E1 T 2(TR2) ABLE EGISTER DS1/E1 T 2 (TR2) EGISTER EGISTER UNCTION EFAULT ESCRIPTION PERATION BER[1] Bit Error Rate This READ/WRITE bit-field is used to insert PRBS bit error at the BER[0] rates presented at the table below.
Page 164 ESCRIPTION PERATION 7-6 RXLBCALEN[1:0] Receive Loopback Code Activation Length This READ/WRITE bit-field determines the receive loopback code activation length. There are four lengths supported by the XRT86VL38 as presented in the table below: ECEIVE OOPBACK CTIVATION RXLBCALEN[1:0] ENGTH Selects 4-bit receive loopback code activa-...
Page 165 UNCTION EFAULT ESCRIPTION PERATION 3-2 TXLBCLEN[1:0] Transmit Loopback Code Length This READ/WRITE bit-field determines transmit loopback code length. There are four lengths supported by the XRT86VL38 as pre- sented in the table below RANSMIT OOPBACK ODE ACTIVATION TXLBCLEN[1:0] ENGTH Selects 4-bit transmit loopback code...
Page 166: Table 64:: Receive Loopback Activation Code Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 63: T ABLE RANSMIT OOPBACK ODER EGISTER (TLCR) EGISTER RANSMIT OOPBACK EGISTER UNCTION EFAULT ESCRIPTION PERATION 7-1 TXLBC[6:0] 1010101 Transmit Loopback Code These seven READ/WRITE bit-fields determine the transmit loop- back code. The MSB of the transmit loopback code is loaded first for transmission.
Page 167: Table 65:: Receive Loopback Deactivation Code Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 65: R ABLE ECEIVE OOPBACK EACTIVATION EGISTER (RLDCR) EGISTER ECEIVE OOPBACK EACTIVATION EGISTER UNCTION EFAULT ESCRIPTION PERATION 7-1 RXLBDC[6:0] 1010101 Receive deactivation loopback code These seven READ/WRITE bit-fields determine the receive loop- back deactivation code.
Page 168: Table 67: Transmit Sa Select Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 67: T Sa S ABLE RANSMIT ELECT EGISTER (TSASR) EGISTER RANSMIT ELECT EGISTER UNCTION EFAULT ESCRIPTION PERATION TxSa6SEL Transmit Sa6 bit select This READ/WRITE bit-field determines whether National Bit (Sa6) is inserted from the transmit serial input (TxSER_n) pin or from the Transmit Sa6 register (Register address = 0xn135).
Page 169 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 67: T Sa S ABLE RANSMIT ELECT EGISTER (TSASR) EGISTER RANSMIT ELECT EGISTER UNCTION EFAULT ESCRIPTION PERATION LB2ENB Local Loopback 2 auto enable This READ/WRITE bit-field enables or disables local loopback mode when the National bits (Sa5, Sa6) received from the transmit backplane interface follows a specific pattern.
Page 170 No power automatic transmission This READ/WRITE bit-field enables the auto Sa-bit transmission upon detecting Loss of Power condition. The XRT86VL38 device recognizes the Loss of Power condition by monitoring the Loss of Power input pin (pin AB1). When the Loss of Power input pin is HIGH indicates a Loss of Power condition is occurring.
Page 171 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 68: T Sa A 1 - E1 M ABLE RANSMIT ONTROL EGISTER 1 (TSACR1) EGISTER RANSMIT ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION NOP_LOSLFA_ENB No power and LOS/LFA automatic transmission This READ/WRITE bit-field enables the auto Sa-bit transmission upon detecting the following two conditions: 1.
Page 172 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 70: T Sa A ABLE RANSMIT ONTROL EGISTER (TSACR2) EGISTER RANSMIT ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION AIS_1_ENB AIS reception This READ/WRITE bit-field enables the automatic Sa-bit transmis- sion upon detecting AIS condition.
Page 173 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 70: T Sa A ABLE RANSMIT ONTROL EGISTER (TSACR2) EGISTER RANSMIT ONTROL EGISTER UNCTION EFAULT ESCRIPTION PERATION CRCDET_ENB CRC detection This READ/WRITE bit-field enables the automatic Sa-bit transmis- sion upon detecting CRC-4 error condition.
Page 174: Table 72: Transmit Sa4 Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 72: T Sa4 R ABLE RANSMIT EGISTER (TSA4R) EGISTER RANSMIT EGISTER UNCTION EFAULT ESCRIPTION PERATION 7-0 TxSa4[7:0] 11111111 Transmit Sa4 Sequence The content of this register sources the transmit Sa4 bits if data link selects Sa 4 bit for transmission and if Sa4 is inserted from register.
Page 175: Table 75:: Transmit Sa7 Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 75: T Sa7 R ABLE RANSMIT EGISTER (TSA7R) EGISTER RANSMIT EGISTER UNCTION EFAULT ESCRIPTION PERATION 7-0 TxSa7[7:0] 11111111 Transmit Sa7 Sequence The content of this register sources the transmit Sa7 bits if data link selects Sa 7 bit for transmission and if Sa7 is inserted from register.
Page 176: Table 78:: Receive Sa5 Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 78: R ABLE ECEIVE EGISTER (RSA5R) EGISTER ECEIVE EGISTER UNCTION EFAULT ESCRIPTION PERATION 7-0 RxSa5[7:0] 00000000 Received Sa5 Sequence The content of this register stores the Sa 5 bits in the most recently received CRC-4 multiframe.
Page 177 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 81: R ABLE ECEIVE EGISTER (RSA8R) n13F EGISTER ECEIVE EGISTER UNCTION EFAULT ESCRIPTION PERATION 7-0 RxSa8[7:0] 00000000 Received Sa8 Sequence The content of this register stores the Sa 8 bits in the most recently received CRC-4 multiframe.
Page 178 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 83: D ABLE ONTROL EGISTER 2 (DLCR2) n143 EGISTER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SLC-96 SLC®96 Enable, 6 bit for ESF This READ/WRITE bit-field is used to enable or disable SLC®96 data link message transmission.
Page 179 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 83: D ABLE ONTROL EGISTER 2 (DLCR2) n143 EGISTER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Tx_ABORT Transmit ABORT This READ/WRITE bit-field configures the Transmit HDLC 2 Con- troller to transmit an ABORT sequence (string of 7 or more consecu- tive 1’s) to the Remote terminal.
Page 180 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 84: T ABLE RANSMIT OUNT EGISTER 2 (TDLBCR2) n144 EGISTER RANSMIT OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION BUFAVAL//BUFSEL Transmit HDLC 2 Buffer Available/Buffer Select This READ/WRITE bit-field has two functions. When this bit is being written, it specifies which one of the two Transmit HDLC 2 Buffers has been loaded for transmission.
Page 181 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 85: R ABLE ECEIVE OUNT EGISTER 2 (RDLBCR2) n145 EGISTER ECEIVE OUNT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RDLBC6 Receive HDLC Message - byte count The exact function of these bits depends on whether the Receive RDLBC5 HDLC 2 Controller is configured to receive MOS or BOS messages.
Page 182 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 86: D ABLE ONTROL EGISTER 3 (DLCR3) n153 EGISTER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Rx_FCS_DIS Receive Frame Check Sequence (FCS) Verification Enable/Dis- able This READ/WRITE bit-field is used to enable or disable the Receive HDLC 3 Controller’s to compute and verify the FCS value in the...
Page 183: Table 87: Transmit Data Link Byte Count Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 86: D ABLE ONTROL EGISTER 3 (DLCR3) n153 EGISTER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Tx_FCS_EN Transmit LAPD Message with Frame Check Sequence (FCS) This READ/WRITE bit-field configures Transmit HDLC 3 Controller to include or not include the FCS octets in the outbound LAPD mes- sage frames.
Page 184: Table 88:: Receive Data Link Byte Count Register
Receive HDLC 3 buffer. 89: D ID R ABLE EVICE EGISTER ID R (DEVID) EGISTER EVICE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION DEVID[7:0] DEVID 0x3B This register is used to identify the XRT86VL38 Framer/LIU. The value of this register is 0x3Bh.
Page 185: Table 90:: Revision Id Register
7-0 REVID[7:0] 00000001 REVID This register is used to identify the revision number of the XRT86VL38. The value of this register for the current revision is A - 0x01h. : The content of this register is subject to change when a newer revision of the device is issued.
Page 186 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 91: T 31 E1 M ABLE RANSMIT HANNEL ONTROL EGISTER 59-90 E1 0-31 (TCCR 0-31) : 0Xn300 n31F EGISTER RANSMIT HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Reserved Reserved TxCond(3:0) 0000...
Page 187 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 91: T 31 E1 M ABLE RANSMIT HANNEL ONTROL EGISTER 59-90 E1 0-31 (TCCR 0-31) : 0Xn300 n31F EGISTER RANSMIT HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxCond(3:0) 0000 (Continued) 0X6 = If these bits are set to ‘0x6h’, the contents of the timeslot octet will be substituted with the value 0xFF (VACANT Code) prior to transmission to the Remote Terminal Equipment.
Page 188 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 92: T 31 T1 M ABLE RANSMIT HANNEL ONTROL EGISTER 59-90 T1 T 0-23 (TCCR 0-23) n300 n317 EGISTER RANSMIT HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION LAPDcntl[1] Transmit LAPD Control...
Page 189 EFAULT ESCRIPTION PERATION 5 - 4 TxZERO[1:0] Selects Type of Zero Suppression These READ/WRITE bit-fields select the type of zero code suppression used by the XRT86VL38 device ZERO[1:0] YPE OF UPPRESSION ELECTED No zero code suppression is used AT&T bit 7 stuffing is used GTE zero code suppression is used.
Page 190 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 92: T 31 T1 M ABLE RANSMIT HANNEL ONTROL EGISTER 59-90 T1 T 0-23 (TCCR 0-23) n300 n317 EGISTER RANSMIT HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-0 TxCond(3:0) 0000 Transmit Channel Conditioning for Timeslot 0 to 23 These READ/WRITE bit-fields allow the user to provide individual control over each transmit T1 channel.
Page 191 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 92: T 31 T1 M ABLE RANSMIT HANNEL ONTROL EGISTER 59-90 T1 T 0-23 (TCCR 0-23) n300 n317 EGISTER RANSMIT HANNEL ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-0 TxCond(3:0) 0000 (Continued) 0X6 = If these bits are set to ‘0x6h’, the contents of the timeslot octet...
Page 192 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 93: T ABLE RANSMIT EGISTER 91-122 T1/E1 T 0 (UCR 0-31) n320 n33F EGISTER RANSMIT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TUCR[7:0] b00010111 Transmit Programmable User code. These eight READ/WRITE bit-fields allow users to program any...
Page 193 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 94: T - E1 M ABLE RANSMIT IGNALING ONTROL EGISTER X 123-154 - E1 (TSCR 0-31) H n340 EGISTER RANSMIT IGNALING ONTROL EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION C (x) See Note Transmit Signaling bit C or x bit...
Page 194 Signaling data is inserted from this register (TSCRs). Signaling data is inserted from the transmit Overhead input pin (TxOH_n) if XRT86VL38 is configured in the base rate configuration and if the Transmit Signaling Interface bit is disabled. (i.e. TxMUXEN bit = 0, TxI-...
Page 195: Table 95: Transmit Signaling Control Register X - T1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 95: T - T1 M ABLE RANSMIT IGNALING ONTROL EGISTER X 123-154 - T1 (TSCR) (0-23) n340 EGISTER RANSMIT IGNALING ONTROL EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION A (x) See Note...
Page 196 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 95: T - T1 M ABLE RANSMIT IGNALING ONTROL EGISTER X 123-154 - T1 (TSCR) (0-23) n340 EGISTER RANSMIT IGNALING ONTROL EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSIGSRC[1] See Note Channel signaling control...
Page 197 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 96: R (RCCR 0-31) - E1 M ABLE ECEIVE HANNEL ONTROL EGISTER X 155-186 E1 (RCCR 0-31) n360 EGISTER ECEIVE HANNEL ONTROL EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION LAPDcntl[1] Receive LAPD Control...
Page 198: Table 96: Receive Channel Control Register X (Rccr 0-31) - E1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 96: R (RCCR 0-31) - E1 M ABLE ECEIVE HANNEL ONTROL EGISTER X 155-186 E1 (RCCR 0-31) n360 EGISTER ECEIVE HANNEL ONTROL EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-0 RxCOND[3:0] 0000...
Page 199 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 96: R (RCCR 0-31) - E1 M ABLE ECEIVE HANNEL ONTROL EGISTER X 155-186 E1 (RCCR 0-31) n360 EGISTER ECEIVE HANNEL ONTROL EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-0 RxCOND[3:0] 0000 (Continued) 0X6 = If these bits are set to ‘0x6h’, the contents of the timeslot octet...
Page 200 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 97: R (RCCR 0-23) - T1 M ABLE ECEIVE HANNEL ONTROL EGISTER X 155-186 - T1 (RCCR 0-23) n360 EGISTER ECEIVE HANNEL ONTROL EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION LAPDcntl[1] Receive LAPD Control...
Page 201 EFAULT ESCRIPTION PERATION 5-4 RxZERO[1:0] Selects Type of Zero Suppression These READ/WRITE bit-fields select the type of zero code suppres- sion used by the XRT86VL38 device. YPE OF UPPRESSION ZERO[1:0] ELECTED No zero code suppression is used AT&T bit 7 stuffing is used GTE zero code suppression is used.
Page 202: Table 97: Receive Channel Control Register X (Rccr 0-23) - T1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 97: R (RCCR 0-23) - T1 M ABLE ECEIVE HANNEL ONTROL EGISTER X 155-186 - T1 (RCCR 0-23) n360 EGISTER ECEIVE HANNEL ONTROL EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-0 RxCOND[3:0]...
Page 203 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 97: R (RCCR 0-23) - T1 M ABLE ECEIVE HANNEL ONTROL EGISTER X 155-186 - T1 (RCCR 0-23) n360 EGISTER ECEIVE HANNEL ONTROL EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION 3-0 RxCOND[3:0]...
Page 204 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 98: R (RUCR 0-31) ABLE ECEIVE EGISTER X 187-218 T1/E1 R (RUCR 0-31) n380 EGISTER ECEIVE EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-0 RxUSER[7:0] 00011000 Receive Programmable User code. These eight READ/WRITE bit-fields allow users to program any...
Page 205: Table 99:: Receive Signaling Control Register X (Rscr) (0-31)
Receive signaling data can be substituted with either all ones pattern or with signaling bits from the Receive Signalling Substitu- tion Register (RSSR). The XRT86VL38 device also provides ability to substitute 16-code (A, B, C, D) Signaling, 4-code (A, B) Signaling, and 2-code (A) Signaling.
Page 206 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 99: R (RSCR) (0-31) ABLE ECEIVE IGNALING ONTROL EGISTER X 219-250 T1/E1 R (RSCR) (0-31) n3A0 EGISTER ECEIVE IGNALING ONTROL EGISTER X DDRESS UNCTION EFAULT ESCRIPTION PERATION RxSIGE[1] Signaling extraction. These READ/WRITE bit-fields control per-channel signaling extrac- RxSIGE[0] tion.
Page 207: Table 100:: Receive Substitution Signaling Register (Rssr) E1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 100: R (RSSR) E1 M ABLE ECEIVE UBSTITUTION IGNALING EGISTER 251-282 E1 M (RSSR 0-31) H n3C0 EGISTER ECEIVE UBSTITUTION IGNALING EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SIG2-A 2-code signaling A This READ/WRITE bit-field provides signaling bit A on a per channel basis when 2-code signaling substitution is enabled.
Page 208: Table 101:: Receive Substitution Signaling Register (Rssr) T1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 100: R (RSSR) E1 M ABLE ECEIVE UBSTITUTION IGNALING EGISTER 251-282 E1 M (RSSR 0-31) H n3C0 EGISTER ECEIVE UBSTITUTION IGNALING EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SIG16-B 16-code signaling B This READ/WRITE bit-field provides signaling bit B on a per channel basis when 16-code signaling substitution is enabled.
Page 209 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 101: R (RSSR) T1 M ABLE ECEIVE UBSTITUTION IGNALING EGISTER 251-282 - T1 (RSSR 0-23) H n3C0 EGISTER ECEIVE UBSTITUTION IGNALING EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SIG16-C, 4-A, 2-A 16-code Signaling Bit C, 4-code/2-code Signaling Bit A This READ/WRITE bit-field provides signaling bit C on a per chan- nel basis when 16-code signaling substitution is enabled.
Page 210: Table 103: Lapd Buffer 0 Control Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 103: LAPD B ABLE UFFER ONTROL EGISTER 315-410 LAPD B (LAPDBCR0) n600 EGISTER UFFER ONTROL EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION 7-0 LAPD Buffer 0 LAPD Buffer 0 (96-Bytes) This register is used to transmit and receive LAPD messages within buffer 0 of the HDLC controller.
Page 211: Table 107:: Pmon T1/E1 Receive Framing Alignment Bit Error Counter
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 105: PMON T1/E1 R ABLE ECEIVE BIPOLAR IOLATION OUNTER PMON R MSB (RLCVCU) n900 EGISTER ECEIVE BIPOLAR IOLATION OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RLCVC[15] Performance Monitor “Receive Line Code Violation” - Upper...
Page 212: Table 108:: Pmon T1/E1 Receive Framing Alignment Bit Error Counter
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 108: PMON T1/E1 R ABLE ECEIVE RAMING LIGNMENT RROR OUNTER PMON R LSB (RFAECL) n903 EGISTER ECEIVE RAMING LIGNMENT RROR OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RFAEC[7] Performance Monitor “Receive Framing Alignment Error Counter”...
Page 213: Table 110:: Pmon T1/E1 Receive Crc-4 Block Error Counter - Msb
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 110: PMON T1/E1 R CRC-4 B - MSB ABLE ECEIVE LOCK RROR OUNTER PMON R (RSBBECU) H n905 EGISTER ECEIVE YNCHRONIZATION LOCK RROR OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RSBBEC[15] Performance Monitor “Receive Synchronization Bit Error Counter” -...
Page 214: Table 113:: Pmon E1 Receive Far End Block Error Counter
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 112: PMON E1 R - MSB ABLE ECEIVE RROR OUNTER PMON R (RFEBECU) n907 EGISTER ECEIVE LOCK RROR OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RFEBEC[15] Performance Monitor - Receive Far-End Block Error Counter -...
Page 215: Table 115:: Pmon T1/E1 Receive Loss Of Frame Counter
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 114: PMON T1/E1 R ABLE ECEIVE OUNTER PMON R (RSC) n909 EGISTER ECEIVE OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RSC[7] Performance Monitor - Receive Slip Counter (8-bit Counter) These Reset-Upon-Read bit fields reflect the cumulative number of...
Page 216: Table 118:: T1/E1 Prbs Bit Error Counter Msb
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 117: PMON LAPD T1/E1 F ABLE RAME HECK EQUENCE RROR OUNTER PMON LAPD1 F 1 (LFCSEC1) n90C EGISTER RAME HECK EQUENCE RROR OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FCSEC1[7] Performance Monitor - LAPD 1 Frame Check Sequence Error...
Page 217: Table 120:: T1/E1 Transmit Slip Counter
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 120: T1/E1 T ABLE RANSMIT OUNTER T1/E1 T (T1/E1TSC) n90F EGISTER RANSMIT OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSLIP[7] Performance Monitor - Transmit Slip Counter (8-bit Counter) These Reset-Upon-Read bit fields reflect the cumulative number of...
Page 218 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 123: T1/E1 F ABLE RAME HECK EQUENCE RROR OUNTER PMON LAPD2 F 2 (LFCSEC2) n91C EGISTER RAME HECK EQUENCE RROR OUNTER DDRESS UNCTION EFAULT ESCRIPTION PERATION FCSEC2[7] Performance Monitor - LAPD 2 Frame Check Sequence Error...
Page 219: Table 125: Block Interrupt Status Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 125: B ABLE LOCK NTERRUPT TATUS EGISTER (BISR) nB00 EGISTER LOCK NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Sa6 Block Interrupt Status This READ ONLY bit-field Indicates whether or not the SA 6 block has an interrupt request awaiting service.
Page 220 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 125: B ABLE LOCK NTERRUPT TATUS EGISTER (BISR) nB00 EGISTER LOCK NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION HDLC HDLC Block Interrupt Status This READ ONLY bit-field indicates whether or not the HDLC block has any interrupt request awaiting service.
Page 221: Table 126: Block Interrupt Enable Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 126: B ABLE LOCK NTERRUPT NABLE EGISTER (BIER) nB01 EGISTER LOCK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SA6_ENB SA6 Block interrupt enable This READ/WRITE bit permits the user to either enable or disable the SA 6 Block for interrupt generation.
Page 222 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 126: B ABLE LOCK NTERRUPT NABLE EGISTER (BIER) nB01 EGISTER LOCK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION HDLC_ENB HDLC Block Interrupt Enable This READ/WRITE bit permits the user to either enable or disable the HDLC Block for interrupt generation.
Page 223 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 126: B ABLE LOCK NTERRUPT NABLE EGISTER (BIER) nB01 EGISTER LOCK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION ALARM_ENB Alarm & Error Block Interrupt Enable This READ/WRITE bit permits the user to either enable or disable the Alarm &...
Page 224 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 127: A & E ABLE LARM RROR NTERRUPT TATUS EGISTER & E (AEISR) nB02 EGISTER LARM RROR NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION E1/T1 Rx Red Alarm Receive Red Alarm State...
Page 225 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 127: A & E ABLE LARM RROR NTERRUPT TATUS EGISTER & E (AEISR) nB02 EGISTER LARM RROR NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxMYEL Status RUR/ Change of CAS Multiframe Yellow Alarm Interrupt Status.
Page 226 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 127: A & E ABLE LARM RROR NTERRUPT TATUS EGISTER & E (AEISR) nB02 EGISTER LARM RROR NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION E1/T1 LCV Int Status RUR/ Line Code Violation Interrupt Status.
Page 227 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 127: A & E ABLE LARM RROR NTERRUPT TATUS EGISTER & E (AEISR) nB02 EGISTER LARM RROR NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION E1/T1 RxAIS Status RUR/ Change in Receive AIS Condition Interrupt Status.
Page 228 This READ/WRITE bit-field permits the user to either enable or disable the “Change in CAS Multiframe Yellow Alarm” Interrupt, within the XRT86VL38 device. If the user enables this interrupt, then the Receive E1 Framer block will gener- ate an interrupt in response to either one of the following conditions.
Page 229 This READ/WRITE bit-field permits the user to either enable or disable the “Change in Red Alarm Condition” Interrupt, within the XRT86VL38 device. If the user enables this inter- rupt, then the Receive T1/E1 Framer block will generate an interrupt in response to either one of the following condi- tions.
Page 230 This READ/WRITE bit-field permits the user to either enable or disable the “Change in Yellow Alarm Condition” Interrupt, within the XRT86VL38 device. If the user enables this inter- rupt, then the Receive T1/E1 Framer block will generate an interrupt in response to either one of the following condi- tions.
Page 231: Table 129: Framer Interrupt Status Register E1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 129: F E1 M ABLE RAMER NTERRUPT TATUS EGISTER 531 E1 M (FISR) nB04 EGISTER RAMER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION COMFA Status RUR/ Change of CAS Multiframe Alignment Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change of...
Page 232 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 129: F E1 M ABLE RAMER NTERRUPT TATUS EGISTER 531 E1 M (FISR) nB04 EGISTER RAMER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION COFA Status RUR/ Change of FAS Framing Alignment (COFA) Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change of...
Page 233 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 129: F E1 M ABLE RAMER NTERRUPT TATUS EGISTER 531 E1 M (FISR) nB04 EGISTER RAMER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION Sync Error Status RUR/ CRC-4 Error Interrupt Status.
Page 234 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 130: F T1 M ABLE RAMER NTERRUPT TATUS EGISTER 531 T1 M (FISR) nB04 EGISTER RAMER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RUR/ Change in Signaling Bits Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in Signaling Bits”...
Page 235 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 130: F T1 M ABLE RAMER NTERRUPT TATUS EGISTER 531 T1 M (FISR) nB04 EGISTER RAMER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RUR/ Change of In Frame Condition Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change of In-Frame Condition”...
Page 236: Table 130: Framer Interrupt Status Register T1 Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 130: F T1 M ABLE RAMER NTERRUPT TATUS EGISTER 531 T1 M (FISR) nB04 EGISTER RAMER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RUR/ Synchronization Bit Error (CRC-6) Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “CRC-6 Error”...
Page 237 This READ/WRITE bit-field permits the user to either enable or dis- able the “Change in CAS Multiframe Alignment” Interrupt, within the XRT86VL38 device. If the user enables this interrupt, then the Receive E1 Framer block will generate an interrupt in response to either one of the following conditions.
Page 238: Table 131: Framer Interrupt Enable Register E1 Mode
This READ/WRITE bit-field permits the user to either enable or dis- able the “Change in FAS Framing Alignment (COFA)” Interrupt, within the XRT86VL38 device. If the user enables this interrupt, then the Receive E1 Framer block will generate an interrupt when it detects a Change of FAS Framing Alignment Signal (e.g., the FAS...
Page 239 This READ/WRITE bit-field permits the user to either enable or dis- able the “Framing Alignment Bit Error Detection” Interrupt, within the XRT86VL38 device. If the user enables this interrupt, then the Receive E1 Framer block will generate an interrupt when it detects one or more Framing Alignment Bit error within the incoming E1 data stream.
Page 240: Table 132: Framer Interrupt Enable Register T1 Mode
This READ/WRITE bit-field permits the user to either enable or dis- able the “Change in FAS Framing Alignment (COFA)” Interrupt, within the XRT86VL38 device. If the user enables this interrupt, then the Receive T1 Framer block will generate an interrupt when it detects a Change of Framing Alignment Signal (e.g., the Framing...
Page 241 This READ/WRITE bit-field permits the user to either enable or dis- able the “Framing Alignment Bit Error Detection” Interrupt, within the XRT86VL38 device. If the user enables this interrupt, then the Receive T1 Framer block will generate an interrupt when it detects one or more Framing Alignment Bit error within the incoming T1 data stream.
Page 242 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 133: D ABLE TATUS EGISTER 1 (DLSR1) nB06 EGISTER TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSOT RUR/ Transmit HDLC1 Controller Start of Transmission (TxSOT) Interrupt Status This Reset-Upon-Read bit indicates whether or not the “Transmit HDLC1 Controller Start of Transmission (TxSOT) “Interrupt has...
Page 243 This READ/WRITE bit enables or disables the “Transmit HDLC1 Controller Start of Transmission (TxSOT) “Interrupt within the XRT86VL38 device. Once this interrupt is enabled, the Transmit HDLC1 Controller will generate an interrupt when it has started to transmit a data link message.
Page 244 This READ/WRITE bit enables or disables the “Receive HDLC1 Controller Start of Reception (RxSOT) “Interrupt within the XRT86VL38 device. Once this interrupt is enabled, the Receive HDLC1 Controller will generate an interrupt when it has started to receive a data link message.
Page 245: Table 134:: Data Link Interrupt Enable Register 1
Receipt of Abort Sequence Interrupt Enable This READ/WRITE bit enables or disables the “Receipt of Abort Sequence“ Interrupt within the XRT86VL38 device. Once this inter- rupt is enabled, the Receive HDLC1 Controller will generate an interrupt when it has detected the Abort Sequence (i.e. a string of seven (7) consecutive 1’s) within the incoming data link channel.
Page 246 96 LOCK/ 96 is in SYNC/CAS Multiframe Alignment is in SYNC CAS SYNC The exact function of this bit depends on whether the XRT86VL38 is configured in T1 or E1 mode. In T1 Mode: This READ ONLY bit field indicates whether or not frame synchroni- ®...
Page 247 PERATION MLOCK/CRCMLOCK Multiframe is in SYNC/CRC Multiframe is in SYNC The exact function of this bit depends on whether the XRT86VL38 is configured in T1 or E1 mode. In T1 Mode: This READ ONLY bit field indicates whether or not the T1 Receive Framer Block is declaring T1 Multiframe LOCK status.
Page 248 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 135: S (SBISR) - T1/E1 M ABLE UFFER NTERRUPT TATUS EGISTER (SBISR) nB08 EGISTER UFFER NTERRUPT TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxSB_EMPT RUR/ Receive Slip buffer Empty Interrupt Status This Reset-Upon-Read bit indicates whether or not the Receive Slip Buffer Empty interrupt has occurred since the last read of this regis- ter.
Page 249 Transmit Slip Buffer Full Interrupt Enable This READ/WRITE bit enables or disables the Transmit Slip Buffer Full interrupt within the XRT86VL38 device. Once this interrupt is enabled, the transmit Slip Buffer Full interrupt is declared when the transmit slip buffer is filled. If the transmit slip buffer is full and a WRITE operation occurs, then a full frame of data will be deleted, and the interrupt status bit will be set to ‘1’.
Page 250: Table 136: Slip Buffer Interrupt Enable Register (Sbier) - T1/E1 Mode
Receive Slip Buffer Full Interrupt Enable This READ/WRITE bit enables or disables the Receive Slip Buffer Full interrupt within the XRT86VL38 device. Once this interrupt is enabled, the Receive Slip Buffer Full interrupt is declared when the receive slip buffer is filled. If the Receive slip buffer is full and a WRITE operation occurs, then a full frame of data will be deleted, and the interrupt status bit will be set to ‘1’.
Page 251: Table 137: Receive Loopback Code Interrupt And Status Register (Rlcisr)
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 137: R (RLCISR) ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER (RLCISR) nB0A EGISTER ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION AUXPSTAT AUXP state This READ ONLY bit indicates whether or not the Receive T1/E1 Framer Block is currently detecting Auxiliary (101010..) pattern.
Page 252 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 137: R (RLCISR) ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER (RLCISR) nB0A EGISTER ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION NONCRCINT RUR/WC Change of CRC-4-to-non-CRC-4 interworking interrupt Status -...
Page 253 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 137: R (RLCISR) ABLE ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER (RLCISR) nB0A EGISTER ECEIVE OOPBACK NTERRUPT AND TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RXAINT RUR/WC Change in Receive Loopback Activation Code interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in Receive Loopback Activation Code”...
Page 254: Table 138:: Receive Loopback Code Interrupt Enable Register (Rlcier)
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 138: R (RLCIER) ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER (RLCIER) nB0B EGISTER ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION AUXPINTENB Change in Auxiliary Pattern interrupt enable This READ WRITE bit field enables or disables the “Change in Aux- iliary Pattern”...
Page 255 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 138: R (RLCIER) ABLE ECEIVE OOPBACK NTERRUPT NABLE EGISTER (RLCIER) nB0B EGISTER ECEIVE OOPBACK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RXAENB Receive Loopback Activation Code Interrupt Enable This READ/WRITE bit field enables or disables the “Change in Receive Loopback Activation Code”...
Page 256: Table 139: Receive Sa Interrupt Register (Rsair) - E1 Mode Only
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 139: R SA I (RSAIR) - E1 M ABLE ECEIVE NTERRUPT EGISTER SA I (RSAIR) nB0C EGISTER ECEIVE NTERRUPT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SA6_1111 RUR/ Change in Debounced Sa6 = 1111 Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in Debounced Sa6=1111”...
Page 257 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 139: R SA I (RSAIR) - E1 M ABLE ECEIVE NTERRUPT EGISTER SA I (RSAIR) nB0C EGISTER ECEIVE NTERRUPT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SA6_1010 RUR/ Change in Debounced Sa6 = 1010 Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in Debounced Sa6=1010”...
Page 258 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 139: R SA I (RSAIR) - E1 M ABLE ECEIVE NTERRUPT EGISTER SA I (RSAIR) nB0C EGISTER ECEIVE NTERRUPT EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SA6_other RUR/ Debounced Sa6 = other Combination Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in Debounced Sa6=other combination”...
Page 259 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 140: R SA I (RSAIER) ABLE ECEIVE NTERRUPT NABLE EGISTER SA I (RSAIER) nB0D EGISTER ECEIVE NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SA6_1111_ENB Change in Debounced Sa6 = 1111 Interrupt Enable This READ/WRITE bit field enables or disables the “Change in...
Page 260: Table 140: Receive Sa Interrupt Enable Register (Rsaier)
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 140: R SA I (RSAIER) ABLE ECEIVE NTERRUPT NABLE EGISTER SA I (RSAIER) nB0D EGISTER ECEIVE NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SA6_1010_ENB Change in Debounced Sa6 = 1010 Interrupt Enable This READ/WRITE bit field enables or disables the “Change in...
Page 261 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 140: R SA I (RSAIER) ABLE ECEIVE NTERRUPT NABLE EGISTER SA I (RSAIER) nB0D EGISTER ECEIVE NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SA6_other_ENB Debounced Sa6 = Other Combination Interrupt enable This READ/WRITE bit field enables or disables the “Debounced...
Page 262 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 141: E ABLE XCESSIVE TATUS EGISTER (EXZSR) nB0E EGISTER XCESSIVE TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SA7_EQ_0_INT RUR/ Change in “Sa 7 Equals 0” Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in Sa7 Equals 0”...
Page 263: Table 142: Excessive Zero Enable Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 142: E ABLE XCESSIVE NABLE EGISTER (EXZER) nB0F EGISTER XCESSIVE NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SA7_EQ_0_ENB Change in “Sa 7 Equals 0” Interrupt Enable This READ/WRITE bit field enables or disables the “Change in Sa7 Equals 0”...
Page 264: Table 144: Ss7 Enable Register For Lapd1
This READ ONLY bit indicates the type of data link message received by Receive HDLC 2 Controller. Two types of data link mes- sages are supported within the XRT86VL38 device: Message Ori- ented Signaling (MOS) or Bit-Oriented Signalling (BOS). 0 = Reading a ‘0’ indicates Bit-Oriented Signaling (BOS) type data link message is received 1 = Reading a ‘1’...
Page 265 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 145: D ABLE TATUS EGISTER 2 (DLSR2) nB16 EGISTER TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxEOT RUR/ Transmit HDLC2 Controller End of Transmission (TxEOT) Inter- rupt Status This Reset-Upon-Read bit indicates whether or not the Transmit HDLC2 Controller End of Transmission (TxEOT) Interrupt has occurred since the last read of this register.
Page 266 This READ/WRITE bit enables or disables the “Transmit HDLC2 Controller Start of Transmission (TxSOT) “Interrupt within the XRT86VL38 device. Once this interrupt is enabled, the Transmit HDLC2 Controller will generate an interrupt when it has started to transmit a data link message.
Page 267 This READ/WRITE bit enables or disables the “Transmit HDLC2 Controller End of Transmission (TxEOT) “Interrupt within the XRT86VL38 device. Once this interrupt is enabled, the Transmit HDLC2 Controller will generate an interrupt when it has finished transmitting a data link message.
Page 268 This READ ONLY bit indicates the type of data link message received by Receive HDLC 3 Controller. Two types of data link messages are supported within the XRT86VL38 device: Message Oriented Signaling (MOS) or Bit-Oriented Signalling (BOS). 0 = Reading a ‘0’ indicates Bit-Oriented Signaling (BOS) type data link message is received 1 = Reading a ‘1’...
Page 269 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 149: D ABLE TATUS EGISTER 3 (DLSR3) EGISTER TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION TxSOT RUR/ Transmit HDLC3 Controller Start of Transmission (TxSOT) Inter- rupt Status This Reset-Upon-Read bit indicates whether or not the “Transmit HDLC3 Controller Start of Transmission (TxSOT) “Interrupt has...
Page 270 This READ/WRITE bit enables or disables the “Transmit HDLC3 Controller Start of Transmission (TxSOT) “Interrupt within the XRT86VL38 device. Once this interrupt is enabled, the Transmit HDLC3 Controller will generate an interrupt when it has started to transmit a data link message.
Page 271 This READ/WRITE bit enables or disables the “Receive HDLC3 Controller Start of Reception (RxSOT) “Interrupt within the XRT86VL38 device. Once this interrupt is enabled, the Receive HDLC3 Controller will generate an interrupt when it has started to receive a data link message.
Page 272 Receipt of Abort Sequence Interrupt Enable This READ/WRITE bit enables or disables the “Receipt of Abort Sequence“ Interrupt within the XRT86VL38 device. Once this inter- rupt is enabled, the Receive HDLC3 Controller will generate an interrupt when it has detected the Abort Sequence (i.e. a string of seven (7) consecutive 1’s) within the incoming data link channel.
Page 273: Table 153:: Customer Installation Alarm Status Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 153: C ABLE USTOMER NSTALLATION LARM TATUS EGISTER (CIASR) nB40 EGISTER USTOMER NSTALLATION LARM TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION [7:6] Reserved Reserved RxAIS-CI_state Receive Alarm Indication Signal-Customer Installation (AIS-CI) State...
Page 274 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 153: C ABLE USTOMER NSTALLATION LARM TATUS EGISTER (CIASR) nB40 EGISTER USTOMER NSTALLATION LARM TATUS EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxAIS-CI RUR/ Change in Receive AIS-CI Condition Interrupt Status This Reset-Upon-Read bit field indicates whether or not the “Change in AIS-CI Condition”...
Page 275: Table 154: Customer Installation Alarm Status Register
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 154: C ABLE USTOMER NSTALLATION LARM TATUS EGISTER (CIAIER) nB41 EGISTER USTOMER NSTALLATION LARM NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION RxAIS-CI_ENB Change in Receive AIS-CI Condition Interrupt Enable This READ/WRITE bit field enables or disables the “Change in AIS- CI Condition”...
Page 276: Programming The Line Interface Unit (Liu Section)
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Programming the Line Interface Unit (LIU Section) Channel Control Registers 155: M #555, 571, 587, 603, 619, 635, 651 & 667 B ABLE ICROPROCESSOR EGISTER ESCRIPTION EGISTER DDRESS HANNEL 0F00 HANNEL 0F10...
Page 277: Table 155: Microprocessor Register #555, 571, 587, 603, 619, 635, 651 & 667 Bit Description
Receiver ON: This READ/WRITE bit-field permits the user to either turn on or turn off the Receive Section of XRT86VL38. If the user turns on the Receive Section, then XRT86VL38 will begin to receive the incoming DS1or E1 data-stream via the RTIP and RRING input pins.
Page 278 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 156: E ABLE QUALIZER ONTROL AND RANSMIT UILD EQC[4:0] T1/E1 M ECEIVE ENSITIVITY RANSMIT ABLE 0x00h T1 Long Haul/36dB 100Ω TP 0x01h T1 Long Haul/36dB -7.5dB 100Ω TP 0x02h T1 Long Haul/36dB -15dB 100Ω...
Page 279 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 157: M #556, 572, 588, 604, 620, 636, 652 & 668 B ABLE ICROPROCESSOR EGISTER ESCRIPTION EGISTER DDRESS HANNEL 0F01 HANNEL 0F11 HANNEL 0F21 HANNEL 0F31 HANNEL EGISTER ESET 0F41 UNCTION HANNEL...
Page 280: Table 157: Microprocessor Register #556, 572, 588, 604, 620, 636, 652 & 668 Bit Description
This READ/WRITE bit field permits the user to enable or dis- able the Jitter Attenuator in the Receive Path within the XRT86VL38 device. 0 = Disables the Jitter Attenuator to operate in the Receive Path within the Receive DS1/E1 LIU Block.
Page 281 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 157: M #556, 572, 588, 604, 620, 636, 652 & 668 B ABLE ICROPROCESSOR EGISTER ESCRIPTION JABW_n Jitter Attenuator Bandwidth Select: In E1 mode: This READ/WRITE bit-field is used to select the Jitter Attenua- tor Bandwidth as well as the FIFO size.
Page 282 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 158: M #557, 573, 589, 605, 621, 637, 653 & 669 B ABLE ICROPROCESSOR EGISTER ESCRIPTION INVQRSS_n Invert QRSS Pattern: This READ/WRITE bit-field inverts the output QRSS pattern if the LIU Block is configured to transmit a QRSS pattern.
Page 283: Table 158: Microprocessor Register #557, 573, 589, 605, 621, 637, 653 & 669 Bit Description
“00001” to the line for the selected channel number n. When Network Loop-Up code is being transmitted, the XRT86VL38 will ignore the “Automatic Loop-Code detection and Remote Loop-Back activation” (NLCDE1 =“1”, NLCDE0 =“1” of register 0x0Fn3) in order to avoid activating Remote Digital Loop-Back automatically when the remote terminal responds to the Loop-Back request.
Page 284 Transmitter ON: This READ/WRITE bit-field permits the user to either turn on or turn off the Transmit Driver of XRT86VL38. If the user turns on the Transmit Driver, then XRT86VL38 will begin to trans- mit DS1 or E1 data (on the line) via the TTIP and TRING out- put pins.
Page 285 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 159: M #558, 574, 590, 606, 622, 638, 654 & 670 B ABLE ICROPROCESSOR EGISTER ESCRIPTION EGISTER DDRESS HANNEL 0F03 HANNEL 0F13 HANNEL 0F23 HANNEL 0F33 HANNEL EGISTER ESET 0F43 UNCTION HANNEL...
Page 286: Table 159: Microprocessor Register #558, 574, 590, 606, 622, 638, 654 & 670 Bit Description
Loop-Up Code Detection Enable: When NLCDE1 =”0” and NLCDE0 = “1”, the XRT86VL38 is configured to monitor the receive data for the Loop-Up code Pattern (i.e. a string of four ‘0’s follow by one ‘1’ pattern).
Page 287: Table 160: Microprocessor Register #559, 575, 591, 607, 623, 639, 655 & 671 Bit Description
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 159: M #558, 574, 590, 606, 622, 638, 654 & 670 B ABLE ICROPROCESSOR EGISTER ESCRIPTION NLCDE0_n Network Loop Code Detection Enable Bit 0 : Please See register description of bit D7 within this register for the function of this bit.
Page 288 This READ/WRITE bit-field permits the user to either enable or disable the “Change in Network Loop-Code Detection” Inter- rupt. If the user enables this interrupt, then the XRT86VL38 device will generate an interrupt any time when either one of the following events occur.
Page 289: Table 161: Microprocessor Register #560, 576, 592, 608, 624, 640, 656 & 672 Bit Description
“Change of the Receive LOS Defect Condition” Interrupt. If the user enables this interrupt, then the XRT86VL38 device will generate an interrupt any time when either one of the following events occur. 1. Whenever the Receive Section (within XRT86VL38) declares the LOS Defect Condition.
Page 290 Transmit Output Line signal. 0 = Indicates that the Transmit Section of XRT86VL38 is NOT currently declaring the Transmit DMO Alarm condition. 1 = Indicates that the Transmit Section of XRT86VL38 is cur- rently declaring the Transmit DMO Alarm condition.
Page 291 When the XRT86VL38 is configured in the Loop-Code detec- tion mode (i.e., NLCDE1 = “1” and NLCDE0 =”1”),the state of the NLCD status bit is reset to “0” and the XRT86VL38 is pro- grammed to monitor the receive input data for the Loop-Up code.
Page 292: Table 162: Microprocessor Register #561, 577, 593, 609, 625, 641, 657 & 673 Bit Description
The value of this bit is based on the current status of Quasi- random pattern detector of channel n. 0 = Indicates that the XRT86VL38 is NOT currently declaring the QRSS Pattern LOCK. 1 = Indicates that the XRT86VL38 is currently declaring the QRSS Pattern LOCK.
Page 293 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 162: M #561, 577, 593, 609, 625, 641, 657 & 673 B ABLE ICROPROCESSOR EGISTER ESCRIPTION FLSIS_n FIFO Limit Interrupt Status: RUR/WC This RESET-upon-READ bit-field indicates whether or not the “FIFO Limit” Interrupt has occurred since the last read of this register.
Page 294: Table 163: Microprocessor Register #562, 578, 594, 610, 626, 642, 658 & 674 Bit Description
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 162: M #561, 577, 593, 609, 625, 641, 657 & 673 B ABLE ICROPROCESSOR EGISTER ESCRIPTION RLOSIS_n Change of Receive LOS (Loss of Signal) Defect Condition RUR/WC Interrupt Status: This RESET-upon-READ bit-field indicates whether or not the “Change of the Receive LOS Defect Condition”...
Page 295: Table 164: Microprocessor Register #563, 579, 595, 611, 627, 643, 659 & 675 Bit Description
0x18-0x1F) Arbitrary mode is enabled by writing the E1 Arbi- trary Mode Enable bit (bit D3 within register 0x0FE1) to ‘1’ when the XRT86VL38 device is configured in any E1 EQC set- tings. The shape of each channel's transmitted pulse can be made independently user programmable by selecting the “Arbitrary...
Page 296: Table 165: Microprocessor Register #564, 580, 596, 612, 628, 644, 660 & 676 Bit Description
0x18-0x1F) Arbitrary mode is enabled by writing the E1 Arbi- trary Mode Enable bit (bit D3 within register 0x0FE1) to ‘1’ when the XRT86VL38 device is configured in any E1 EQC set- tings. The shape of each channel's transmitted pulse can be made independently user programmable by selecting the “Arbitrary...
Page 297: Table 167: Microprocessor Register #566, 582, 598, 614, 630, 646, 662 & 678 Bit Description
0x18-0x1F) Arbitrary mode is enabled by writing the E1 Arbi- trary Mode Enable bit (bit D3 within register 0x0FE1) to ‘1’ when the XRT86VL38 device is configured in any E1 EQC set- tings. The shape of each channel's transmitted pulse can be made independently user programmable by selecting the “Arbitrary...
Page 298 0x18-0x1F) Arbitrary mode is enabled by writing the E1 Arbi- trary Mode Enable bit (bit D3 within register 0x0FE1) to ‘1’ when the XRT86VL38 device is configured in any E1 EQC set- tings. The shape of each channel's transmitted pulse can be made independently user programmable by selecting the “Arbitrary...
Page 299: Table 168: Microprocessor Register #567, 583, 599, 615, 631, 647, 663 & 679 Bit Description
0x18-0x1F) Arbitrary mode is enabled by writing the E1 Arbi- trary Mode Enable bit (bit D3 within register 0x0FE1) to ‘1’ when the XRT86VL38 device is configured in any E1 EQC set- tings. The shape of each channel's transmitted pulse can be made independently user programmable by selecting the “Arbitrary...
Page 300: Table 170: Microprocessor Register #569, 585, 601, 617, 633, 649, 665 & 681 Bit Description
0x18-0x1F) Arbitrary mode is enabled by writing the E1 Arbi- trary Mode Enable bit (bit D3 within register 0x0FE1) to ‘1’ when the XRT86VL38 device is configured in any E1 EQC set- tings. The shape of each channel's transmitted pulse can be made independently user programmable by selecting the “Arbitrary...
Page 301: Table 171: Microprocessor Register #570, 586, 602, 618, 634, 650, 666 & 682 Bit Description
0x18-0x1F) Arbitrary mode is enabled by writing the E1 Arbi- trary Mode Enable bit (bit D3 within register 0x0FE1) to ‘1’ when the XRT86VL38 device is configured in any E1 EQC set- tings. The shape of each channel's transmitted pulse can be made independently user programmable by selecting the “Arbitrary...
Page 302 0x18-0x1F) Arbitrary mode is enabled by writing the E1 Arbi- trary Mode Enable bit (bit D3 within register 0x0FE1) to ‘1’ when the XRT86VL38 device is configured in any E1 EQC set- tings. The shape of each channel's transmitted pulse can be made independently user programmable by selecting the “Arbitrary...
Page 303 SRESET This READ/WRITE bit field allows users to reset the XRT86VL38 device. Writing a “1” to this bit longer than 10µs initiates a device reset through the microprocessor interface. Once the XRT86VL38 is reset, all internal circuits are placed in the reset state except the microprocessor register bits.
Page 304 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 173: M #700, B ABLE ICROPROCESSOR EGISTER ESCRIPTION LOBAL EGISTER EGISTER DDRESS EGISTER ESET 0x0FE1h UNCTION ALUE Bit # Reserved Reserved Guage1 Wire Gauge Selector Bit 1: Guage0 This READ/WRITE bit-field together with Guage0 bit (bit D4 within this register) are used to select the wire gauge size as shown in the table below.
Page 305 This READ/WRITE bit-field allows users to tristate the out- put pins of all channels for in-circuit testing purposes. When In-Circuit-Testing is enabled, all output pins of the XRT86VL38 are placed in “Tri-state”. When In-Circuit-Test- ing is disabled, all output pins will resume to normal condi- tion.
Page 306 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 174: M #701, B ABLE ICROPROCESSOR EGISTER ESCRIPTION LOBAL EGISTER TxONCNTL Transmitter ON Control This bit sets the LIU to control the TxON function with either the individual channel register bit or the global hardware pin 0 = Control of the transmit section is set to the hardware pins.
Page 307 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 175: M #702, B ABLE ICROPROCESSOR EGISTER ESCRIPTION LOBAL EGISTER MCLKnE11 Master E1 Output Clock Reference MCLKnE10 These two READ/WRITE bit-fields allow users to select the programmable output clock rates for the E1MCLKnOUT pin.
Page 308 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 176: M #703, B ABLE ICROPROCESSOR EGISTER ESCRIPTION LOBAL EGISTER CLKSEL3 Clock Select Input CLKSEL2 These four READ/WRITE bit-fields allow users to select the programmable input clock rates for the MCLKIN input pin. The...
Page 309 0 = Indicates that No interrupt has occurred on Channel 7 within the XRT86VL38 device since the last read of this regis- ter. 1 = Indicates that an interrupt has occurred on Channel 7 within the XRT86VL38 device since the last read of this regis- ter.
Page 310 0 = Indicates that No interrupt has occurred on Channel 3 within the XRT86VL38 device since the last read of this regis- ter. 1 = Indicates that an interrupt has occurred on Channel 3 within the XRT86VL38 device since the last read of this regis- ter.
Page 311: The Interrupt Structure Within The Framer
The XRT86VL38 Framer comes equipped with registers to support the servicing of this wide array of potential “interrupt re- quest” sources. Table 178 lists the possible conditions that can generate interrupts.
Page 312 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Determine the Framer(s) Requesting the Interrupt If the interrupting device turns out to be the Framer, then the microprocessor must determine which of the four framer chan- nels requested the interrupt. Hence, upon reaching this state, one of the very first things that the microprocessor must do within the user Framer interrupt service routine, is to perform a read of each of the Block Interrupt Status Registers within all of the Framer channels that have been enabled for Interrupt Generation via their respective Interrupt Control Registers.
Page 313 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 180: B ABLE LOCK NTERRUPT NABLE EGISTER (BIER) nB01 EGISTER LOCK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION SA6_ENB SA6 Block interrupt enable This READ/WRITE bit permits the user to either enable or disable the SA 6 Block for interrupt generation.
Page 314 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 180: B ABLE LOCK NTERRUPT NABLE EGISTER (BIER) nB01 EGISTER LOCK NTERRUPT NABLE EGISTER DDRESS UNCTION EFAULT ESCRIPTION PERATION HDLC_ENB HDLC Block Interrupt Enable This READ/WRITE bit permits the user to either enable or disable the HDLC Block for interrupt generation.
Page 315: Configuring The Interrupt System, At The Framer Level
3.6.1 Configuring the Interrupt System, at the Framer Level The XRT86VL38 Framer IC permits the user to enable or disable each of the four Framers for interrupt generation. Further, the chip permits the user to make the following configuration selection.
Page 316 Configuring the "Interrupt Status Bits", within a given Framer to be "Reset-upon-Read" or "Write-to-Clear". The XRT86VL38 Source-Level Interrupt Status Register bits can be configured to be either “Reset-upon-Read” or “Write-to- Clear”. If the user configures the Interrupt Status Registers to be “Reset-upon-Read”, then when the microprocessor is reading the interrupt status register, the following will happen.
Page 317 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 microprocessor has written 0x00 into this register. (Hence, the Interrupt Service Routine must include this write operation). The Interrupt Status Register (associated with a given framer) can be configured to be either “Reset-upon-Read” or “Write- to-Clear”...
Page 318: General Description And Interface
REV. P1.0.6 4.0 GENERAL DESCRIPTION AND INTERFACE The XRT86VL38 supports multiple interfaces for various modes of operation. The purpose of this section is to present a general overview of the common interfaces and their connection diagrams. Each mode will be described in full detail in later sections of the datasheet.
Page 319: R3 Technology (Relayless / Reconfigurable / Redundancy)
EXAR’s R technology has re-defined DS-1/E1/J1 physical interface design for 1:1 and 1+1 redundancy applications. Without relays and one Bill of Materials, EXAR offers multi-port, integrated Framer/LIU solutions to assist high density aggregate applications and framing requirements with reliability.
Page 320: Receive Interface With 1:1 And 1+1 Redundancy
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 4.2.5 Receive Interface with 1:1 and 1+1 Redundancy The receivers on the backup card should be programmed for "High" impedance. Since there is no external resistor in the circuit, the receivers on the backup card will not load down the line interface. This key design feature eliminates the need for relays and provides one bill of materials for all interface modes of operation.
Page 321: Power Failure Protection
For 1:1 or 1+1 line card redundancy in T1/E1 applications, power failure could cause a line card to change the characteristics of the line impedance, causing a degradation in system performance. The XRT86VL38 was designed to ensure reliability during power failures. The LIU has patented high impedance circuits that allow the receiver inputs and the transmitter outputs to be in "High"...
Page 322: T1/E1 Serial Pcm Interface
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 T1/E1 Serial PCM Interface The most common mode is the standard serial PCM interface. Within this mode, only the serial data, serial clock, frame pulse and multi-frame pulse are required for both the transmit and receive paths. For the transmit path, only TxSER is a dedicated input to the device.
Page 323: T1/E1 Fractional Interface
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 T1/E1 Fractional Interface The individual time slots can be enabled/disabled to carry fractional DS-0 data. The purpose of this interface is to enable one or more time slots in the PCM data (TxSER) to be replaced with the fractional DS-0 payload. If this mode is selected, the dedicated hardware pin TxCHN1/T1FR is used to input the fractional DS-0 data within the time slots that are enabled.
Page 324: T1/E1 Time Slot Substitution And Control
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 T1/E1 Time Slot Substitution and Control The time slots within PCM data are reserved for carrying individual DS-0’s. However, the framer block (transmit or receive paths) can substitute the payload with various code definitions. Each time slot can be independently programmed to carry normal PCM data or a variety of user codes.
Page 325: Robbed Bit Signaling/Cas Signaling
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Robbed Bit Signaling/CAS Signaling Signaling is used to convey status information relative to the individual DS-0’s. If a particular DS-0 is On Hook, Off Hook, etc. this information is carried within the robbed bits in T1 (SF/ESF/SLC-96) or the sixteenth time slot in E1.
Page 326: Overhead Interface
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 23. SF / SLC-96 ESF / CAS E IGURE CODE IGNALING IN XTERNAL IGNALING TxSERclk TxSER TS 2 TS 3 TS 1 TxCHN0/TxSIG TxSYNC TxMSYNC 4.10 Overhead Interface The Overhead interface provides an option for inserting the datalink bits into the transmit PCM data or extracting the datalink bits from the receive PCM data.
Page 327: Figure 25.: T1 External Overhead Datalink Bus
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 25. T1 E IGURE XTERNAL VERHEAD ATALINK Frame1 Frame2 Frame3 Frame4 Frame5 Frame6 TxSYNC TxOHclk (4kHz) TxOH Datalink Bit Datalink Bit Datalink Bit 26. E1 O IGURE VERHEAD XTERNAL ATALINK Non-FAS Frame...
Page 328: Framer Bypass Mode
Framer Bypass Mode The framer bypass mode allows the XRT86VL38 to be used as a stand alone Line Interface Unit. In this mode, a few of the backplane interface signals multiplex into the digital Input/output signals to and from the LIU block.
Page 329: High-Speed Non-Multiplexed Interface
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 4.12 High-Speed Non-Multiplexed Interface The speed of transferring data through a back plane interface in a non-multiplexed manner typically operates at 1.544Mbps, 2.048Mbps, 4.096Mbps, or 8.192Mbps. For 12.352Mbps and 16.384Mbps, see the High-Speed Multiplexed Section.
Page 330: High-Speed Multiplexed Interface
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 4.13 High-Speed Multiplexed Interface In addition to the non-multiplexed mode, the framer can interface through the backplane in a high-speed multiplexed application, either through a bit-muxed or byte-muxed (in HMVIP or H.100) manner. In this mode, the chip is divided into two multiplexed blocks, four channels per block.
Page 331: Loopback Modes Of Operation
5.0 LOOPBACK MODES OF OPERATION LIU Physical Interface Loopback Diagnostics The XRT86VL38 supports several loopback modes for diagnostic testing. The following section describes the local analog loopback, remote loopback, digital loopback, and dual loopback modes. The LIU physical interface loopback modes are independent from the Framer loopback modes. Therefore, it is possible to configure multiple loopback modes creating tremendous flexibility within the looped diagnostic features.
Page 332: Digital Loopback
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 5.1.3 Digital Loopback With digital loopback activated, the transmit input data at TCLK/TPOS/TNEG is looped back to the receive output data at RCLK/RPOS/RNEG. The digital loopback mode includes the Transmit JA (if enabled). The receive input data at RTIP/RRING is ignored while valid transmit output data continues to be sent to the line.
Page 333: Framer Local Loopback
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 36. S IGURE IMPLIFIED LOCK IAGRAM OF THE RAMER EMOTE OOPBACK NLC/PRBS/QRSS TAOS Framer Timing TTIP Encoder Control TRING Data and RTIP Framer Decoder Clock RRING Recovery 5.1.6 Framer Local Loopback With framer local loopback activated, the transmit PCM input data is looped back to the receive PCM output data.
Page 334: Programming Sequence For Sending Less Than 96-Byte Messages
96-Byte buffers for Receive. The buffers are used to insert messages into the out going data stream for Transmit or to extract messages from the incoming data stream from the Receive path. Total, there are twelve 96-Byte buffers per channel. This allows multiple HDLC messages to be transported to and from EXAR’s framing device.
Page 335: Programming Sequence For Receiving Lapd Messages
Programming Sequence for Receiving LAPD Messages The XRT86VL38 can extract data link information from incoming DS1 frames from either the datalink bits themselves or the D/E time slots within the PCM input data. To extract a LAPD message, the following programming sequence can be used as a reference.
Page 336: Priority Codeword Message
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Where D5 is the MSB and D0 is the LSB. The rightmost "1" is transmitted first. BOS is classified into the following two groups. • Priority Codeword Message • Command and Response Information 5.7.2...
Page 337: Periodic Performance Report
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 39. LAPD F IGURE RAME TRUCTURE 5.8.2 Periodic Performance Report The ANSI T1.403 standard requires that the status of the transmission quality be reported in one-second intervals. The one-second timing may be derived from the DS1 signal or from a separate equally accurate (±32ppm) source.
Page 338: Path And Test Signal Identification Message
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 terminal has lost framing, is only designed as a performance indicator; existing terminal out-of-frame criteria will continue to serve as the basis for terminal alarms. • Frame-Synchronization-Bit Error Event: A frame-synchronization-bit-error event is the occurrence of a received framing-bit-pattern not meeting the severely-errored-framing event criteria.
Page 339 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 5.8.10 Service Access Point Identifier (SAPI) The Service Access Point Identifier identifies a point at which data link layer services are preceded by a data link layer entity type to a layer 3 or management entity. Consequently, the SAPI specifies a data link layer entity type that should process a data link layer frame and also a layer 3 or management entity, which is to receive information carried by the data link layer frame.
Page 340 Fs bit is replaced by the data link message read from memory at the beginning of each D4 super- frame. The XRT86VL38 allocates two 6-byte buffers to provide the SLC®96 Data Link Controller an alternating access mechanism for information transmission. The bit ordering and usage is shown in the following table;...
Page 341 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 5.10 D/E Time Slot Transmit HDLC Controller Block V5.1 or V5.2 Interface V5.2 protocol specifies a provision for transmitting simultaneous LAPD messages. Since only one message can be sent through the datalink bits at one time, an alternative path for communication is offered within the framer block.
Page 342 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 U2 = Not Used (default = 0) R = Not Used (default = 0) NmNi = One second report module 4 count...
Page 343: Figure 40.: Block Diagram Of The Ds1 Transmit Overhead Input Interface Of The Xrt86Vl38
OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 6.0 OVERHEAD INTERFACE BLOCK The XRT86VL38 has the ability to extract or insert DS1 data link information from or into the following: • Facility Data Link (FDL) bits in ESF framing format mode •...
Page 344 Transmit Overhead Input Interface Block becomes input source of the FDL bits. The XRT86VL38 allows the user to select bandwidth of the Facility Data Link Channel in ESF framing format mode. The FDL can be either a 4KHz or 2KHz data link channel. The Transmit Data Link Bandwidth Select bits of the Transmit Data Link Select Register (TDLSR) determine the bandwidth of FDL channel in ESF framing format mode.
Page 345: Figure 41.: Ds1 Transmit Overhead Input Interface Timing In Esf Framing Format Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 41. DS1 T ESF F IGURE RANSMIT VERHEAD NPUT NTERFACE IMING IN RAMING ORMAT MODE 6.1.3 Configure the DS1 Transmit Overhead Input Interface module as source of the Signaling Framing (Fs) bits in N or SLC®96 framing format mode The Fs bits in SLC®96 and N framing format mode can be inserted from:...
Page 346: Figure 42.: Ds1 Transmit Overhead Input Timing In N Or Slc®96 Framing Format Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Figure 42 below shows the timing diagram of the input and output signals associated with the DS1 Transmit Overhead Input Interface module in N or SLC®96 framing format mode. 42. DS1 T SLC®96 F...
Page 347: Figure 44.: Block Diagram Of The Ds1 Receive Overhead Output Interface Of Xrt86Vl38
RxOHClk_n. The Data Link equipment should sample and latch the data link bits at the falling edge of RxOHClk_n. The figure below shows block diagram of the Receive Overhead Output Interface of XRT86VL38. 44. B DS1 R...
Page 348 Overhead Output Interface Block becomes Output source of the FDL bits. The XRT86VL38 allows the user to select bandwidth of the Facility Data Link Channel in ESF framing format mode. The FDL can be either a 4KHz or 2KHz data link channel. The Receive Data Link Bandwidth Select bits of the Receive Data Link Select Register (RDLSR) determine the bandwidth of FDL channel in ESF framing format mode.
Page 349: Figure 45.: Ds1 Receive Overhead Output Interface Module In Esf Framing Format Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 45. DS1 R IGURE ECEIVE VERHEAD UTPUT NTERFACE MODULE IN FRAMING FORMAT MODE Frame # RxSync RxOhClk (4KHz) RxOh (4KHz) RxOhClk (2KHz,odd) RxOh (2KHz,odd) RxOhClk (2KHz,even) RxOh (2KHz,even) 6.2.3 Configure the DS1 Receive Overhead Output Interface module as destination of the Signaling Framing (Fs) bits in N or SLC®96 framing format mode...
Page 350: Figure 46.: Ds1 Receive Overhead Output Interface Timing In N Or Slc®96 Framing Format Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Figure 46 below shows the timing diagram of the output signals associated with the DS1 Receive Overhead Output Interface module in N or SLC®96 framing format mode. 46. DS1 R SLC®96 F...
Page 351: Figure 47.: Ds1 Receive Overhead Output Interface Timing In T1Dm Framing Format Mode
E1 Overhead Interface Block The XRT86VL38 has the ability to extract or insert E1 data link information from or into the E1 National bit sequence. The source and destination of these inserted and extracted data link bits would be from either the internal HDLC Controller or the external device accessible through E1 Overhead Interface Block.
Page 352 If the Transmit Data Link Source Select bits of the Transmit Data Link Select Register are set to 10, the Transmit Overhead Input Interface Block becomes input source of the FDL bits. The XRT86VL38 allows the user to decide on the following: •...
Page 353: Figure 49.: E1 Transmit Overhead Input Interface Timing
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) (ADDRESS = 0XN10AH) ESCRIPTION UMBER Transmit Sa7 Data 0 - Source of the Sa7 Nation bit is not from the data link interface. Link Select 1 - Source the Sa7 National bit from the data link interface.
Page 354: Figure 50.: Block Diagram Of The E1 Receive Overhead Output Interface Of Xrt86Vl38
Sa4 through Sa8 National bits that are extracted from the incoming E1 frames. Independent of the availability of the E1 Receive HDLC Controller module, the XRT86VL38 always output the received National bits through the Receive Overhead Output Interface block.
Page 355: Figure 51.: E1 Receive Overhead Output Interface Timing
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 The table below shows configuration of the Receive Sa Data Link Select bits of the Receive Signaling and Data Link Select Register (RSDLSR). RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (ADDRESS = 0XN10CH)
Page 356: Figure 52.: Taos (Transmit All Ones)
7.1.1 TAOS (Transmit All Ones) The XRT86VL38 has the ability to transmit all ones on a per channel basis by programming the appropriate channel register. This function takes priority over the digital data provided by the Framer block. For example: If a fixed "0011"...
Page 357: Figure 55.: Network Loop Down Code Generation
55. N IGURE ETWORK ENERATION Network Loop-Down Code 7.1.5 QRSS Generation The XRT86VL38 can transmit a QRSS random sequence to a remote location from TTIP/TRING. The polynomial is shown in Table 183. 183: R ABLE ANDOM EQUENCE OLYNOMIALS ANDOM ATTERN...
Page 358: Figure 57.: Long Haul Line Build Out With -15Db Attenuation
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 57. L IGURE UILD UT WITH TTENUATION 58. L -22.5 IGURE UILD UT WITH TTENUATION T1 Short Haul Line Build Out (LBO) The short haul transmitter output pulses are generated using a 7-Bit internal DAC (6-Bit plus the MSB sign bit).
Page 359: Figure 59.: Arbitrary Pulse Segment Assignment
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 special line build out, see the arbitrary pulse section of this datasheet. The short haul LBO settings are shown in Table 184 184: S ABLE HORT UILD EQC[4:0] SETTING ANGE OF ABLE...
Page 360 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 7.3.3 Transmit Jitter Attenuator The transmit path has a dedicated jitter attenuator to reduce phase and frequency jitter in the transmit clock. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. When the Read and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption.
Page 361: Figure 60.: Typical Connection Diagram Using Internal Termination
F. For redundancy applications (or simply to tri-state the transmitters), set TxTSEL to a "1" in the appropriate channel register. A typical transmit interface is shown in Figure 60. 60. T IGURE YPICAL ONNECTION IAGRAM SING NTERNAL ERMINATION XRT86VL38 LIU C=0.68uF Transmitter Line Interface T1/E1/J1 Output RING One Bill of Materials Internal Impedance...
Page 362: Figure 61.: Typical Connection Diagram Using Internal Termination
120 Ω 3h (11) The XRT86VL38 has the ability to switch the internal termination to "High" impedance by programming RxTSEL in the appropriate channel register, if the RxTSEL hardware pin is “High”. For internal termination, set RxTSEL to "1". By default, RxTSEL is set to "0" ("High" impedance). For redundancy applications, a dedicated hardware pin (RxTSEL) is available to control the receive termination for all channels simultaneously.
Page 363: Figure 62.: Simplified Block Diagram Of The Equalizer And Peak Detector
LOF, pattern synchronization, etc. Short haul specifications are for 12dB of flat loss in E1 mode. T1 specifications are 655 feet of cable loss along with 6dB of flat loss in T1 mode. The XRT86VL38 can tolerate cable loss and flat loss beyond the industry specifications. The receive sensitivity in the short haul mode is approximately 4,000 feet without experiencing bit errors, LOF, pattern synchronization, etc.
Page 364: Figure 64. Test Configuration For Measuring Receive Sensitivity
If the network loop code detection is programmed for automatic loop code, the LIU is configured to detect a Loop-Up code. If a Loop-Up code is detected for more than 5 seconds, the XRT86VL38 will automatically program the channel into a remote loopback mode. The LIU will remain in remote loopback even if the Loop-Up code disappears.
Page 365: Figure 65.: Process Block For Automatic Loop Code Detection
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 65. P IGURE ROCESS LOCK FOR UTOMATIC ETECTION Loop-Up Code for 5 sec? Automatic Remote Loopback Loop-Down Disable Remote Code for Loopback 5 sec? 8.2.3 FLSD (FIFO Limit Status Detection) The purpose of the FIFO limit status is to indicate when the Read and Write FIFO pointers are within a pre- determined range (over-flow or under-flow indication).
Page 366: Figure 66.: Simplified Block Diagram Of The Rxmute Function
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 66. S MUTE F IGURE IMPLIFIED LOCK IAGRAM OF THE UNCTION Digital Framer Output RxMUTE RLOS...
Page 367: Figure 67.: Interfacing The Transmit Path To Local Terminal Equipment
Description of the Transmit/Receive Payload Data Input Interface Block Each of the eight framers within the XRT86VL38 device includes a Transmit and Receive Payload Data Input Interface block. Although most configurations are independent for the Tx and Rx path, once E1 framing has been selected, both the Tx and Rx must operate in E1.
Page 368: Figure 69.: Waveforms For Connecting The Transmit Payload Data Input Interface Block To Local Terminal Equipment 357 Figure 68.: Interfacing The Receive Path To Local Terminal Equipment
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 68. I IGURE NTERFACING THE ECEIVE ATH TO LOCAL TERMINAL EQUIPMENT XRT86VL38 RxSERCLK0 RxSER0 Receive RxMSYNC0 Payload Data Input RxSYNC0 Interface RxCHCLK0 Chn 0 RxCHN[4:0]_0 Terminal Equipment RxSERCLK7 RxSER7 Receive RxMSYNC7 Payload...
Page 369: Figure 70.: Waveforms For Connecting The Receive Payload Data Input Interface Block To Local Terminal Equipment
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 70. W IGURE AVEFORMS FOR CONNECTING THE ECEIVE AYLOAD NPUT NTERFACE LOCK TO LOCAL MINAL QUIPMENT Timeslot 0 Timeslot 5 Timeslot 6 Timeslot 31 RxSerClk RxSer Input Data Input Data Rx Fractional Enable Bit = 0...
Page 370: Figure 71.: Transmit Non-Multiplexed High-Speed Connection To Local Terminal Equipment Using Mvip 2.048Mbit/S, 4.096Mbit/S, Or 8.192Mbit/S
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 71. T MVIP IGURE RANSMIT ULTIPLEXED PEED ONNECTION TO LOCAL TERMINAL EQUIPMENT USING 2.048M , 4.096M 8.192M TxINCLK = 2.048/4.096/8.192MHz XRT86VL38 TxSERCLK0 Transmit Payload TxSER0 Data TxINCLK0 Input TxSYNC0 Interface Chn 0...
Page 371: Figure 73.: Waveforms For Connecting The Transmit Non-Multiplexed High-Speed Input Interface At Mvip 2.048Mbit/S, 4.096Mbit/S, And 8.192Mbit/S
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 Figure 73 shows the waveforms for connecting the Transmit non-multiplexed high-speed Input Interface block to local Terminal Equipment. Figure 74 shows the waveforms for connecting the Receive non-multiplexed high-speed Input Interface block to local Terminal Equipment.
Page 372 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 9.2.2 Multiplexed High-Speed Mode Bit-Multiplexed 16.384Mbit/s When the Back-plane interface data rate is 16.384Mbit/s, HMVIP 16.384Mbit/s, and H.100 16.384Mbit/s, the interface signals are all configured as inputs, except the receive serial data on RxSER and the multi frame sync pulse provided by the framer.
Page 373 Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are de-multiplexed inside the XRT86VL38 device and send to each individual channel. These data will be processed by each individual framer and send to LIU interface. The local Terminal Equipment provides a free- running 2.048MHz clock to the Transmit Serial Input clock of each channel.
Page 374 Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are de-multiplexed inside the XRT86VL38 device and send to each individual channel. These data will be processed by each individual framer and send to LIU interface. The local Terminal Equipment provides a free- running 2.048MHz clock to the Transmit Serial Input clock of each channel.
Page 375: Figure 75.: Interfacing Xrt86Vl38 Transmit To Local Terminal Equipment Using 16.384Mbit/S, Hmvip 16.384Mbit/S, And H.100 16.384Mbit/S
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 75. I XRT86VL38 T 16.384M , HMVIP IGURE NTERFACING RANSMIT TO LOCAL TERMINAL EQUIPMENT USING 16.384M H.100 16.384M XRT86VL38 TxSER0 Transmit TxINCLK0 (16.384MHz) Payload Data Input TxSYNC0 Interface TxSERCLK0 (2.048MHz) Chn 0 TxSERCLK1 (2.048MHz)
Page 376: Figure 77.: Waveforms For Connecting The Transmit Multiplexed High-Speed Input Interface At Hmvip And
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 77. W IGURE AVEFORMS FOR ONNECTING THE RANSMIT ULTIPLEXED PEED NPUT NTERFACE AT HMVIP A H.100 16.384M S MODE TxInClk (16.384MHz) TxInClk (INV) 56 cycles TxSer Start of Frame : X is the bit number and y is the channel number...
Page 377: Figure 78.: Interfacing Xrt86Vl38 Receive To Local Terminal Equipment Using 16.384Mbit/S, Hmvip 16.384Mbit/S, And H.100 16.384Mbit/S
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 78. I XRT86VL38 R 16.384M , HMVIP IGURE NTERFACING ECEIVE TO LOCAL TERMINAL EQUIPMENT USING 16.384M H.100 16.384M XRT86VL38 RxSER0 Transmit RxSERCLK0 (12/16MHz) Payload Data Input RxSYNC0 Interface Chn 0 Chn 1...
Page 378 The user can program these bits through microprocessor access. If the XRT86VL38 framer is configure to insert signaling bits from TSCR registers, the E1 Transmit Framer block will fill up the time slot 16 octet with the signaling bits stored inside the TSCR registers. The insertion of signaling bit into PCM data is done on a per-channel basis.
Page 379: Figure 81.: Timing Diagram Of The Txsig Input
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 81. T SIG I IGURE IMING IAGRAM OF THE NPUT 82. T SIG O IGURE IMING IAGRAM OF THE UTPUT Enable Channel Associated Signaling and Signaling Data Source Control The Transmit Signaling Control Register (TSCR) of each channel selects source of signaling data to be inserted into the outgoing E1 frame and enables Channel Associated signaling.
Page 380: Figure 83.: Interfacing The Transmit Path To Local Terminal Equipment
Description of the Transmit/Receive Payload Data Input Interface Block Each of the four framers within the XRT86VL38 device includes a Transmit and Receive Payload Data Input Interface block. Although most configurations are independent for the Tx and Rx path, once T1 framing has been selected, both the Tx and Rx must operate in T1.
Page 381: Figure 85.: Waveforms For Connecting The Transmit Payload Data Input Interface Block To Local Terminal Equipment 370 Figure 84.: Interfacing The Receive Path To Local Terminal Equipment
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 84. I IGURE NTERFACING THE ECEIVE ATH TO LOCAL TERMINAL EQUIPMENT XRT86VL38 RxSERCLK0 RxSER0 Receive RxMSYNC0 Payload Data Input RxSYNC0 Interface RxCHCLK0 Chn 0 RxCHN[4:0]_0 Terminal Equipment RxSERCLK7 RxSER7 Receive RxMSYNC7 Payload...
Page 382: Figure 86.: Waveforms For Connecting The Receive Payload Data Input Interface Block To Local Terminal Equipment
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 86. W IGURE AVEFORMS FOR CONNECTING THE ECEIVE AYLOAD NPUT NTERFACE LOCK TO LOCAL MINAL QUIPMENT Timeslot 0 Timeslot 5 Timeslot 6 Timeslot 23 RxSerClk RxSer Input Data Input Data RxSync(output) Rx Fractional Enable Bit = 0...
Page 383: Figure 87.: Transmit Non-Multiplexed High-Speed Connection To Local Terminal Equipment Using Mvip 2.048Mbit/S, 4.096Mbit/S, Or 8.192Mbit/S
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 The mapping of T1 frame into E1 framing format is shown in the table below. F-Bit Don't Care Bits Don't Care Bits Don't Care Bits TS10 TS11 TS10 TS11 TS12 TS13 TS14...
Page 384: Figure 89.: Waveforms For Connecting The Transmit Non-Multiplexed High-Speed Input Interface At Mvip 2.048Mbit/S, 4.096Mbit/S, And 8.192Mbit/S
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 88. R MVIP IGURE ECEIVE ULTIPLEXED PEED ONNECTION TO LOCAL TERMINAL EQUIPMENT USING 2.048M , 4.096M 8.192M RxSERCLK = 2.048/4.096/8.192MHz XRT86VL38 RxSERCLK0 Receive RxSER0 Payload RxMSYNC0 Data Input Interface RxSYNC0 Chn 0...
Page 385: Figure 90.: Waveforms For Connecting The Receive Non-Multiplexed High-Speed Input Interface At Mvip 2.048Mbit/S, 4.096Mbit/S, And 8.192Mbit/S
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 90. W IGURE AVEFORMS FOR ONNECTING THE ECEIVE ULTIPLEXED PEED NPUT NTERFACE AT MVIP 2.048M , 4.096M 8.192M RxSERCLK (2/4/8MHz) RxSER Don't Care Don't care RxSYNC(input) RxCHN[0]/RxSig Don't care Don't Care Don't Care...
Page 386 Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are de-multiplexed inside the XRT86VL38 and sent to each individual channel. These data will be processed by each individual framer and send to the LIU interface. The local Terminal Equipment provides a free-running 1.544MHz clock to the Transmit Serial Input clock of each channel.
Page 387: Figure 91.: Interfacing Xrt86Vl38 Transmit To Local Terminal Equipment Using 16.384Mbit/S, Hmvip 16.384Mbit/S, And H.100 16.384Mbit/S
OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 the Transmit multiplexed high-speed Input Interface block to local Terminal Equipment. Figure 95 shows the timing signal when the transmit framer is running at 12.352 Bit-Multiplexed Mode 91. I XRT86VL38 T 16.384M , HMVIP IGURE NTERFACING RANSMIT TO LOCAL TERMINAL EQUIPMENT USING 16.384M...
Page 388 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 1. The F-bit of four channels are repeated and grouped together to form the first octet of the multiplexed data stream. The F-bit of Channel 0 is sent first, followed by F-bit of Channel 1 and 2. The F-bit of Channel 3 is sent last.
Page 389: Figure 93.: Timing Signals When The Transmit Framer Is Running At 16.384 Bit-Multiplexed Mode
Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are de-multiplexed inside the XRT86VL38 and send to each individual channel. These data will be processed by each individual framer and send to LIU interface. The local Terminal Equipment provides a free-running 1.544MHz clock to the Transmit Serial Input clock of each channel.
Page 390 Inside the framer, all the "don't care" bits will be stripped away. The framing bits, signaling and payload data are de-multiplexed inside the XRT86VL38 and send to each individual channel. These data will be processed by each individual framer and send to LIU interface. The local Terminal Equipment provides a free-running 1.544MHz clock to the Transmit Serial Input clock of each channel.
Page 391: Figure 94.: Timing Signals When The Transmit Framer Is Running At Hmvip / H.100 16.384Mhz Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 94. T HMVIP / H.100 16.384MH IGURE IMING SIGNALS WHEN THE TRANSMIT FRAMER IS RUNNING AT TxInClk (16.384MHz) TxInClk (INV) 56 cycles TxSer Start of Frame : X is the bit number and y is the channel number...
Page 392: Figure 95.: Interfacing Xrt86Vl38 Receive To Local Terminal Equipment Using 16.384Mbit/S, Hmvip 16.384Mbit/S, And H.100 16.384Mbit/S
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 95. I XRT86VL38 R 16.384M , HMVIP IGURE NTERFACING ECEIVE TO LOCAL TERMINAL EQUIPMENT USING 16.384M H.100 16.384M XRT86VL38 RxSER0 Transmit RxSERCLK0 (12/16MHz) Payload Data Input RxSYNC0 Interface Chn 0 Chn 1...
Page 393: Figure 98.: Waveforms For Connecting The Receive Multiplexed High-Speed Input Interface At Hmvip And H.100 16.384Mbit/ S Mode
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 98. W HMVIP IGURE AVEFORMS FOR ONNECTING THE ECEIVE ULTIPLEXED PEED NPUT NTERFACE AT H.100 16.384M S MODE RxSerClk (16.384MHz) RxSerClk (INV) 56 cycles RxSer Start of Frame : X is the bit number and y is the channel number...
Page 394 TSCR registers. The insertion of signaling bits into PCM data is done on a per- channel basis. In SF or SLC®96 mode, the user can control the XRT86VL38 framer to transmit no signaling (transparent), two-code signaling, or four-code signaling. Two-code signaling is done by substituting the least significant bit (LSB) of the specific channel in frame 6 and 12 with the content of the Signaling bit A of the specific TSCR register.
Page 395: Figure 99.: Timing Diagram Of The Txsig_N Input
24. 10.3.3 Insert Signaling Bits from TxSig_n Pin The XRT86VL38 framer can be configured to insert signaling bits provided by external equipment through the TxSig_n pins. This pin is a multiplexed I/O pin with two functions: •...
Page 396 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 The table below shows configurations of the Transmit Fractional DS1 bit of the Transmit Interface Control Register (TICR). TRANSMIT INTERFACE CONTROL REGISTER (TICR)(ADDRESS = 0XN120H) ESCRIPTION UMBER Transmit This READ/WRITE bit-field permits the user to determine which one of the two functions the multiplexed I/O pin of TxTSb[0]_n/TxSig_n is spotting.
Page 397 Upon microprocessor interruption, the user can intervene by looking into the error conditions. At the same time, the user can configure the XRT86VL38 framer to transmit alarms and error indications to remote terminal. Different alarms and error indications will be transmitted depending on the error condition.
Page 398 1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg- ister (AEISR) is enabled. When these interrupt enable bits are set and AIS is present in the incoming DS1 frame, the XRT86VL38 framer will declare AIS by doing the following: •...
Page 399 4. An interval without valid LOF flag decrements the flag counter. The Red alarm is removed when the counter reaches zero. If LOF condition is present in the incoming DS1 frame, the XRT86VL38 framer can generate a Receive Red Alarm State Change interrupt associated with the setting of Receive Red Alarm State Change bit of the Alarm and Error Status Register to one.
Page 400 1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg- ister (AEISR) is enabled. When these interrupt enable bits are set and Red Alarm is present in the incoming DS1 frame, the XRT86VL38 framer will declare Red Alarm by doing the following: •...
Page 401 3. An interval without valid YEL flag decrements the flag counter. The YEL alarm is removed when the counter reaches zero. If Yellow Alarm condition is present in the incoming DS1 frame, the XRT86VL38 framer can generate a Receive Yellow Alarm State Change interrupt associated with the setting of Receive Yellow Alarm State Change bit of the Alarm and Error Status Register to one.
Page 402 Receive Framer block of the XRT86VL38 framer monitors the incoming DS1 frames for Bipolar Violations. If a Bipolar Violation is present in the incoming DS1 frame, the XRT86VL38 framer can generate a Receive Bipolar Violation interrupt associated with the setting of Receive Bipolar Violation bit of the Alarm and Error Status Register to one.
Page 403 (AEISR) is enabled. When these interrupt enable bits are set and one or more Bipolar Violations are present in the incoming DS1 frame, the XRT86VL38 framer will declare Receive Bipolar Violation by doing the following: • Set the Receive Bipolar Violation bit of the Alarm and Error Status Register to one indicating there are one or more Bipolar Violations.
Page 404 REV. P1.0.6 When these interrupt enable bits are set and one or more Loss of Signals are present in the incoming DS1 frame, the XRT86VL38 framer will declare Receive Loss of Signal by doing the following: • Set the Receive Loss of Signal bit of the Alarm and Error Status Register to one indicating there is one or more Loss of Signals.
Page 405: Figure 100.: Simple Diagram Of E1 System Model
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 100. S IGURE IMPLE IAGRAM OF SYSTEM MODEL Repeater E1 Receive E1 Receive Transmit Receive Framer Block Framer Block Section Section E1 Transmit E1 Transmit Receive Transmit Framer Block Framer Block Section...
Page 406: Figure 101.: Generation Of Yellow Alarm By The Repeater Upon Detection Of Line Failure
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 101. G IGURE ENERATION OF ELLOW LARM BY THE EPEATER UPON DETECTION OF LINE FAILURE Repeater declares Red Alarm internally Repeater generates Yellow Alarm to CO Repeater Yellow Alarm E1 Receive E1 Receive...
Page 407: Figure 102.: Generation Of Ais By The Repeater Upon Detection Of Line Failure
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 102. G IGURE ENERATION OF BY THE EPEATER UPON DETECTION OF LINE FAILURE Repeater declares Red Alarm internally Repeater generates Yellow Alarm to CO Repeater Yellow Alarm E1 Receive E1 Receive Transmit...
Page 408: Figure 103.: Generation Of Yellow Alarm By The Cpe Upon Detection Of Ais Originated By The Repeater
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 103. G IGURE ENERATION OF ELLOW LARM BY THE UPON DETECTION OF ORIGINATED BY THE EPEATER Repeater declares Red Alarm internally CPE detects AIS and Repeater generates generates Yellow Yellow Alarm to CO...
Page 409: Figure 104.: Generation Of Cas Multi-Frame Yellow Alarm And Ais16 By The Repeater
PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 104. G CAS M AIS16 IGURE ENERATION OF ULTI FRAME ELLOW LARM AND BY THE EPEATER Repeater generates CAS Multi-frame Yellow Alarm to CO Repeater CAS Multi- frame Yellow Alarm E1 Receive...
Page 410 (except for framing bits) pattern which can be used by the equipment further down the line to maintain clock recovery and timing synchronization. The XRT86VL38 framer can generate three types of AIS when it is running in E1 format: •...
Page 411 The Transmit Alarm Indication Signal Select bits of the Alarm Generation Register (AGR) enable the three types of AIS transmission that are supported by the XRT86VL38 framer. The table below shows configurations of the Transmit Alarm Indication Signal Select bits of the Alarm Generation Register (AGR).
Page 412 REV. P1.0.6 On the other hand, upon detection of Loss of CAS Multi-frame alignment pattern, the receiver section of the XRT86VL38 framer will transmit a CAS Multi-frame Yellow Alarm back to the source indicating the Loss of CAS Multi-frame synchronization.
Page 413 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 11.6 T1 Brief discussion of alarms and error conditions As defined in ANSI T1.231 specification, alarm conditions are created from defects. Defects are momentary impairments present on the DS1 trunk. If a defect is present for a sufficient amount of time (called the integration time), then the defect becomes an alarm.
Page 414 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 problem further down the line and its transmission is not being received at the CPE. The Figure below illustrates the scenario in which the DS1 connection from the Repeater to CPE is broken.
Page 415 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 108. G IGURE ENERATION OF BY THE EPEATER UPON DETECTION OF ELLOW LARM ORIGINATED BY THE Repeater detects CPE declares Red Yellow alarm and Alarm internally generate AIS to CO Repeater Yellow...
Page 416 The Transmit Alarm Indication Signal Select bits of the Alarm Generation Register (AGR) enable the two types of AIS transmission that are supported by the XRT86VL38 framer. The table below shows configurations of the Transmit Alarm Indication Signal Select bits of the Alarm Generation Register (AGR)
Page 417 Alarm back to the source indicating the loss of an incoming signal. This Yellow Alarm informs the source that there is a problem further down the line and its transmission is not being received at the destination. The XRT86VL38 framer supports transmission of Yellow Alarm when running at the following framing formats: •...
Page 418 Transmit Yellow Alarm in ESF Mode In ESF mode, the XRT86VL38 transmits Yellow Alarm on the 4Kbit/s data link channel. The Facility Data Link bits are sent in the pattern of eight ones followed by eight zeros. The number of repetitions of this pattern depends on the duration of Yellow Alarm Generation Select bits of the Alarm Generation Register.
Page 419 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 ALARM GENERATION REGISTER (AGR)(ADDRESS = 0XN108H) ESCRIPTION UMBER Yellow Alarm 00 - Transmission of Yellow Alarm is disabled. Generation Select 01 - The framer transmits Yellow Alarm by converting the second MSB of all outgoing twenty-four DS0 channel into zero.
Page 420 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 12.0 PERFORMANCE MONITORING (PMON) The function of Performance Monitoring is designed to accumulate error events like line code (bipolar) violations, parity errors, frame alignment errors, etc. using saturating counters. When an accumulation interval is signaled by a one-second interrupt (if enabled), the current counter value can be accessed by the microprocessor.
Page 421 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 12.12 Excessive Zero Violation Counter (16-Bit) This register contains the accumulation of the events in which excessive zeros have occurred. This is defined as more than 3-bit for HDB3, more than 7-bits for B8ZS, and more than 15-bits for AMI. The MSB is stored in...
Page 422 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13.0 APPENDIX A: DS-1/E1 FRAMING FORMATS 13.1 The E1 Framing Structure A single E1 frame consists of 256 bits which is created 8000 times per second. This yields a bit-rate of 2.048Mbps. The 256 bits within each E1 frame are grouped into 32 octets or timeslots. These timeslots are numbered from 0 to 31.
Page 423 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13.1.2 Non-FAS Frame Timeslot 0 within the non-FAS E1 frame contains bits that support signaling or data link message transmission. The bit-format of timeslot 0 is presented in Table 187. The Si bit in the Non-FAS frame typically carries a specific value that will be used by the Receive E1 Framer for CRC Multi-frame alignment purposes.
Page 424 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13.2 The E1 Multi-frame Structure There are two types of E1 Multi-frame structures, CRC Multi-frame and CAS Multi-frame. The CAS Multi- frame can be considered a subset of the CRC Multi-frame, in that CAS is an option to carry signaling information within the CRC Multi-frame structure.
Page 425 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13.2.2 CAS Multi-Frames and Channel Associated Signaling CAS Multi-Frames are only relevant if the user is using CAS or Channel Associated Signaling. If the user is implementing Common Channel Signaling then the CAS Multi-Frame is not available.
Page 426 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13.2.2.2 Common Channel Signaling (CCS) Common Channel Signaling is an alternative form of signaling from CAS. In CCS, whatever signaling data which is transported via the outbound E1 data stream, carries information that applies to all of the voice channels as a set (e.g., timeslots 1 through 15 and 17 through 31) in the E1 frame.
Page 427 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13.3 The DS1 Framing Structure A single T1 frame is 193 bits long and is transmitted at a frame rate of 8000Hz. This results in an aggregate bit rate of 1.544 Mbit/s. Basic frames are divided into 24 timeslots numbered 1 thru 24 and a framing bit as shown in Figure 113.
Page 428 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13.4 T1 Super Frame Format (SF) The Superframe Format (SF), is also referred to as the D4 format. The requirement for associated signaling in frames 6 and 12 dictates that the frames be distinguishable. This leads to a multiframe structure consisting of 12 frames per superframe (SF) as shown in Figure 114 and Table 189.
Page 429 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 189: S ABLE UPERFRAME ORMAT SE IN IMESLOT IGNALLING RAME ERMINAL ERMINAL HANNEL RAFFIC RAMING RAMING 1544 ---- ---- ---- 1737 ---- ---- ---- 1930 ---- ---- ---- 2123 ---- 13.5 T1 Extended Superframe Format (ESF) In Extended Superframe Format (ESF), as shown in Figure 115 and Table 190, the multiframe structure is extended to 24 frames.
Page 430 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 190: E ABLE XTENDED UPERFRAME ORMAT SE IN IGNALLING HANNEL IMESLOT RAME RAFFIC ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----...
Page 431 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13.6 T1 Non-Signaling Frame Format The Non-Signaling (N) framing format is a simplified version of the T1 super frame. The N-Frame consists of four frames with two Fs bits and two Ft bits. The Fs bits can be used as a proprietary 4kbps data link transmission.
Page 432 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 13.8 SLC-96 Format (SLC-96) SLC framing mode allows synchronization to the SLC®96 data link pattern. This pattern described in Bellcore TR-TSY-000008, contains both signaling information and a framing pattern that overwrites the Fs bit of the SF framer pattern.
Page 433 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUMS Power Supply..............Power Rating STBGA and PBGA Package....2.4 ..........- 0.5V to +3.465V - 0.5V to +1.890V CORE..........Storage Temperature .......-65°C to 150°C Input Logic Signal Voltage (Any Pin) ..-0.5V to + 5.5V Operating Temperature Range....-40°C to 85°C...
Page 434 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 ELECTRICAL CHARACTERISTICS 193: E1 R ABLE ECEIVER LECTRICAL HARACTERISTICS = 3.3V + 5% , VDD = 1.8V + 5% = -40° to 85°C, unless otherwise specified CORE ARAMETER ONDITIONS Receiver loss of signal:...
Page 435 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 194: T1 R ABLE ECEIVER LECTRICAL HARACTERISTICS = 3.3V + 5% , VDD = 1.8V + 5%, =-40° to 85°C, unless otherwise specified CORE ARAMETER ONDITIONS Receiver loss of signal: Number of consecutive zeros before...
Page 436 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 196: E1 T ABLE RANSMITTER LECTRICAL HARACTERISTICS = 3.3V + 5% , VDD = 1.8V + 5%, =-40° to 85°C, unless otherwise specified CORE ARAMETER ONDITIONS Ω AMI Output Pulse Amplitude: Transformer with 1:2 ratio and 9.1 Ω...
Page 437 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 117. ITU G.703 P IGURE ULSE EMPLATE 269 ns (244 + 25) V = 100% 194 ns (244 – 50) Nominal pulse 244 ns 219 ns (244 – 25) 488 ns (244 + 244) Note –...
Page 438 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 118. DSX-1 P IGURE ULSE EMPLATE NORMALIZED AMPLITUDE 199: DSX1 I ABLE NTERFACE SOLATED PULSE MASK AND CORNER POINTS INIMUM CURVE AXIMUM CURVE (UI) (UI) ORMALIZED AMPLITUDE ORMALIZED AMPLITUDE -0.77 -.05V -0.77 .05V...
Page 439 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 200: AC E ABLE LECTRICAL HARACTERISTICS = 3.3V + 5% , VDD = 1.8V + 5%, T =25°C, UNLESS OTHERWISE SPECIFIED CORE ARAMETER YMBOL NITS MCLKIN Clock Duty Cycle MCLKIN Clock Tolerance...
Page 440 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 ORDERING INFORMATION RODUCT UMBER ACKAGE PERATING EMPERATURE ANGE ° ° XRT86VL38IB 420 Tape Ball Grid Array C to +85 ° ° XRT86VL38IB484 484 Shrink Thin Ball Grid Array C to +85 PACKAGE DIMENSIONS FOR 420 TAPE BALL GRID ARRAY 420 PLASTIC Thin Ball Grid Array (35.0 mm x 35.0 mm, PBGA)
Page 441 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.6 PACKAGE DIMENSIONS FOR 484 SHRINK THIN BALL GRID ARRAY 484 Shrink Thin Ball Grid Array (23.0 mm x 23.0 mm, STBGA) Rev. 1.00 Note: The control dimension is in millimeter. INCHES MILLIMETERS SYMBOL 0.071...
Page 442 Cnanged pin list and registers descriptions. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement.

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