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Exar XRT86VL38 Manuals
Manuals and User Guides for Exar XRT86VL38. We have
1
Exar XRT86VL38 manual available for free PDF download: Manual
Exar XRT86VL38 Manual (442 pages)
Brand:
Exar
| Category:
PCI Card
| Size: 5 MB
Table of Contents
Table of Contents
6
Figure 1.: XRT86VL38 8-Channel DS1 (T1/E1/J1) Framer/Liu Combo
12
1.0 Pin Lists
17
Table 1:: 420 Ball List by Ball Number
18
Table 2:: 484 Ball List by Ball Number
21
2.0 Pin Descriptions
25
3.0 Microprocessor Interface Block
63
Figure 2.: Simplified Block Diagram of the Microprocessor Interface Block
63
Operating the Microprocessor Interface in Intel-Asynchronous Mode
64
The Intel-Asynchronous Read-Cycle
65
The Intel-Asynchronous Write Cycle
66
Figure 3.: Intel Μp Interface Signals During Read Operations
66
Figure 4.: Intel Μp Interface Signals During Write Operations
67
Operating the Microprocessor Interface in the Motorola-Asynchronous Mode
68
Figure 5.: Intel Μp Interface Timing During Programmed I/O Read and Write Operations
68
The Motorola-Asynchronous Read-Cycle
69
The Motorola-Asynchronous Write-Cycle
70
Figure 6.: Motorola Asynchronous Mode Interface Signals During Read Operations
70
Figure 7.: Motorola Asychronous Mode Interface Signals During Write Operations
72
Figure 8.: Motorola Asychronous Mode Interface Signals During Programmed I/O Read and Write Operations
72
Operating the Microprocessor Interface in the Powerpc 403 Mode
73
The Powerpc 403 Read-Cycle
74
Table 8:: the Roles of Various Microprocessor Interface Pins, When Configured to Operate in the Power PC Mode
74
The Powerpc 403 Write-Cycle
75
Figure 9.: Power PC Mode Interface Signals During Read Operations
75
Dma Read/Write Operations
77
Figure 10.: Power PC Mode Interface Signals During Write Operations
77
Memory Mapped I/O Addressing
78
Figure 11.: DMA Mode for the XRT86VL38 and a Microprocessor
78
Table 10: Register Summary
79
Table 34:: Receive National Bits Register
79
Table 37:: Transmit Data Link Byte Count Register
79
Table 38:: Receive Data Link Byte Count Register
79
Table 83:: Data Link Control Register
79
Table 84:: Transmit Data Link Byte Count Register
79
Table 85:: Receive Data Link Byte Count Register
79
Table 86:: Data Link Control Register
79
Register Descriptions
85
Table 11: Clock Select Register
86
Table 12: Line Interface Control Register
86
Table 13:: General Purpose Input/Output 0 Control Register
88
Table 14:: General Purpose Input/Output 1 Control Register
94
Table 15:: Framing Select Register-E1 Mode
96
Table 16:: Framing Select Register-T1 Mode
100
Table 17: Alarm Generation Register - E1 Mode
103
Table 18: Alarm Generation Register -T1 Mode
105
Table 21: Synchronization Mux Register - E1 Mode
110
Table 22: Synchronization Mux Register - T1 Mode
110
Table 23: Transmit Signaling and Data Link Select Register - E1 Mode
113
Table 24:: Transmit Signaling and Data Link Select Register - T1 Mode
117
Table 25: Framing Control Register E1 Mode
120
Table 35:: Receive Extra Bits Register
130
Table 36: Data Link Control Register
132
Table 39:: Slip Buffer Control Register
135
Table 40:: FIFO Latency Register
136
Table 41:: DMA 0 (Write) Configuration Register
137
Table 43:: Interrupt Control Register
139
Table 44:: LAPD Select Register
139
Table 45:: Customer Installation Alarm Generation Register
140
Table 46:: Performance Report Control Register
141
Table 47: Gapped Clock Control Register
142
Table 48: Transmit Interface Control Register - E1 Mode
143
Table 49: Transmit Interface Speed When Multiplexed Mode Is Disabled (Txmuxen = 0)
145
Table 50: Transmit Interface Speed When Multiplexed Mode Is Enabled (Txmuxen = 1)
146
Table 51: Transmit Interface Control Register - T1 Mode
149
Table 52: Transmit Interface Speed When Multiplexed Mode Is Disabled (Txmuxen = 0)
149
Table 54: Receive Interface Control Register (Ricr) - E1 Mode
151
Table 57: Receive Interface Control Register (Ricr) - T1 Mode
156
Table 61: Ds1/E1 Test Register 2(Tr2)
162
Table 64:: Receive Loopback Activation Code Register
166
Table 65:: Receive Loopback Deactivation Code Register
167
Table 66:: Receive T1/E1 Defect Detection Enable Register
167
TABLE 67: TRANSMIT Sa SELECT REGISTER
168
TABLE 72: TRANSMIT Sa4 REGISTER
174
TABLE 73: TRANSMIT Sa5 REGISTER
174
TABLE 74: TRANSMIT Sa6 REGISTER
174
Table 75:: Transmit Sa7 Register
175
Table 76:: Transmit Sa8 Register
175
Table 77:: Receive Sa4 Register
175
Table 78:: Receive Sa5 Register
176
Table 79:: Receive Sa6 Register
176
Table 80:: Receive Sa7 Register
176
Table 87: Transmit Data Link Byte Count Register
183
Table 88:: Receive Data Link Byte Count Register
184
Table 89: Device ID Register
184
Table 90:: Revision ID Register
185
Table 95: Transmit Signaling Control Register X - T1 Mode
195
Table 96: Receive Channel Control Register X (Rccr 0-31) - E1 Mode
198
Table 97: Receive Channel Control Register X (Rccr 0-23) - T1 Mode
202
Table 99:: Receive Signaling Control Register X (RSCR) (0-31)
205
Table 100:: Receive Substitution Signaling Register (RSSR) E1 Mode
207
Table 101:: Receive Substitution Signaling Register (RSSR) T1 Mode
208
Table 103: Lapd Buffer 0 Control Register
210
Table 104: Lapd Buffer 1 Control Register
210
Table 107:: PMON T1/E1 Receive Framing Alignment Bit Error Counter
211
Table 108:: PMON T1/E1 Receive Framing Alignment Bit Error Counter
212
Table 109:: PMON T1/E1 Receive Severely Errored Frame Counter
212
Table 110:: PMON T1/E1 Receive CRC-4 Block Error Counter - MSB
213
Table 111:: PMON T1/E1 Receive CRC-4 Block Error Counter - LSB
213
Table 113:: PMON E1 Receive Far End Block Error Counter
214
Table 115:: PMON T1/E1 Receive Loss of Frame Counter
215
Table 116:: PMON T1/E1 Receive Change of Frame Alignment Counter
215
Table 118:: T1/E1 PRBS Bit Error Counter MSB
216
Table 119:: T1/E1 PRBS Bit Error Counter LSB
216
Table 120:: T1/E1 Transmit Slip Counter
217
Table 121:: T1/E1 Excessive Zero Violation Counter MSB
217
Table 125: Block Interrupt Status Register
219
Table 126: Block Interrupt Enable Register
221
Table 129: Framer Interrupt Status Register E1 Mode
231
Table 130: Framer Interrupt Status Register T1 Mode
236
Table 131: Framer Interrupt Enable Register E1 Mode
238
Table 132: Framer Interrupt Enable Register T1 Mode
240
Table 134:: Data Link Interrupt Enable Register 1
245
Table 135: Slip Buffer Interrupt Status Register (Sbisr) - T1/E1 Mode
245
Table 136: Slip Buffer Interrupt Enable Register (Sbier) - T1/E1 Mode
250
Table 137: Receive Loopback Code Interrupt and Status Register (Rlcisr)
251
Table 138:: Receive Loopback Code Interrupt Enable Register (RLCIER)
254
Table 139: Receive Sa Interrupt Register (Rsair) - E1 Mode Only
256
Table 140: Receive Sa Interrupt Enable Register (Rsaier)
260
Table 142: Excessive Zero Enable Register
263
Table 143: Ss7 Status Register for Lapd1
263
Table 144: Ss7 Enable Register for Lapd1
264
Table 153:: Customer Installation Alarm Status Register
273
Table 154: Customer Installation Alarm Status Register
275
Programming the Line Interface Unit (Liu Section)
276
Table 155: Microprocessor Register #555, 571, 587, 603, 619, 635, 651 & 667 Bit Description
277
Table 157: Microprocessor Register #556, 572, 588, 604, 620, 636, 652 & 668 Bit Description
280
Table 158: Microprocessor Register #557, 573, 589, 605, 621, 637, 653 & 669 Bit Description
283
Table 159: Microprocessor Register #558, 574, 590, 606, 622, 638, 654 & 670 Bit Description
286
Table 160: Microprocessor Register #559, 575, 591, 607, 623, 639, 655 & 671 Bit Description
287
Table 161: Microprocessor Register #560, 576, 592, 608, 624, 640, 656 & 672 Bit Description
289
Table 162: Microprocessor Register #561, 577, 593, 609, 625, 641, 657 & 673 Bit Description
292
Table 163: Microprocessor Register #562, 578, 594, 610, 626, 642, 658 & 674 Bit Description
294
Table 164: Microprocessor Register #563, 579, 595, 611, 627, 643, 659 & 675 Bit Description
295
Table 165: Microprocessor Register #564, 580, 596, 612, 628, 644, 660 & 676 Bit Description
296
Table 166: Microprocessor Register #565, 581, 597, 613, 629, 645, 661 & 677 Bit Description
296
Table 167: Microprocessor Register #566, 582, 598, 614, 630, 646, 662 & 678 Bit Description
297
Table 168: Microprocessor Register #567, 583, 599, 615, 631, 647, 663 & 679 Bit Description
299
Table 169: Microprocessor Register #568, 584, 600, 616, 632, 648, 664 & 680 Bit Description
299
Table 170: Microprocessor Register #569, 585, 601, 617, 633, 649, 665 & 681 Bit Description
300
Table 171: Microprocessor Register #570, 586, 602, 618, 634, 650, 666 & 682 Bit Description
301
The Interrupt Structure Within the Framer
311
Configuring the Interrupt System, at the Framer Level
315
General Description and Interface
318
Physical Interface
318
Figure 12.: LIU Transmit Connection Diagram Using Internal Termination
318
Figure 13.: LIU Receive Connection Diagram Using Internal Termination
318
R3 Technology (Relayless / Reconfigurable / Redundancy)
319
Line Card Redundancy
319
Typical Redundancy Schemes
319
1:1 and 1+1 Redundancy Without Relays
319
Transmit Interface with 1:1 and 1+1 Redundancy
319
Figure 14.: Simplified Block Diagram of the Transmit Interface for 1:1 and 1+1 Redundancy
319
Receive Interface with 1:1 and 1+1 Redundancy
320
Figure 15.: Simplified Block Diagram of the Receive Interface for 1:1 and 1+1 Redundancy
320
Power Failure Protection
321
Overvoltage and Overcurrent Protection
321
Non-Intrusive Monitoring
321
Figure 16.: Simplified Block Diagram of a Non-Intrusive Monitoring Application
321
T1/E1 Serial Pcm Interface
322
Figure 17.: Transmit T1/E1 Serial PCM Interface
322
Figure 18.: Receive T1/E1 Serial PCM Interface
322
T1/E1 Fractional Interface
323
Figure 19.: T1 Fractional Interface
323
T1/E1 Time Slot Substitution and Control
324
Figure 20.: T1/E1 Time Slot Substitution and Control
324
Robbed Bit Signaling/Cas Signaling
325
Figure 21.: Robbed Bit Signaling / CAS Signaling
325
Figure 22.: ESF / CAS External Signaling Bus
325
Overhead Interface
326
Figure 23.: SF / SLC-96 or 4-Code Signaling in ESF / CAS External Signaling Bus
326
Figure 24.: T1/E1 Overhead Interface
326
Figure 25.: T1 External Overhead Datalink Bus
327
Figure 26.: E1 Overhead External Datalink Bus
327
Framer Bypass Mode
328
Figure 27.: Simplified Block Diagram of the Framer Bypass Mode
328
High-Speed Non-Multiplexed Interface
329
Figure 28.: T1 High-Speed Non-Multiplexed Interface
329
Figure 29.: E1 High-Speed Non-Multiplexed Interface
329
High-Speed Multiplexed Interface
330
Figure 30.: Transmit High-Speed Bit Multiplexed Block Diagram
330
Figure 31.: Receive High-Speed Bit Multiplexed Block Diagram
330
Loopback Modes of Operation
331
Liu Physical Interface Loopback Diagnostics
331
Local Analog Loopback
331
Remote Loopback
331
Figure 32.: Simplified Block Diagram of Local Analog Loopback
331
Figure 33.: Simplified Block Diagram of Remote Loopback
331
Digital Loopback
332
Dual Loopback
332
Framer Remote Line Loopback
332
Figure 34.: Simplified Block Diagram of Digital Loopback
332
Figure 35.: Simplified Block Diagram of Dual Loopback
332
Framer Local Loopback
333
Figure 36.: Simplified Block Diagram of the Framer Remote Line Loopback
333
Figure 37.: Simplified Block Diagram of the Framer Local Loopback
333
Programming Sequence for Sending Less than 96-Byte Messages
334
Programming Sequence for Sending Large Messages
334
Figure 38.: HDLC Controllers
334
Programming Sequence for Receiving Lapd Messages
335
Ss7 (Signaling System Number 7) for Esf in Ds1 Only
335
Ds1/E1 Datalink Transmission Using the Hdlc Controllers
335
Transmit Bos (Bit Oriented Signaling) Processor
335
Description of Bos
335
Priority Codeword Message
336
Command and Response Information
336
Transmit Mos (Message Oriented Signaling) Processor
336
Discussion of Mos
336
Periodic Performance Report
337
Transmission-Error Event
337
Figure 39.: LAPD Frame Structure
337
Path and Test Signal Identification Message
338
Frame Structure
338
Figure 40.: Block Diagram of the DS1 Transmit Overhead Input Interface of the XRT86VL38
343
Figure 41.: DS1 Transmit Overhead Input Interface Timing in ESF Framing Format Mode
345
Figure 42.: DS1 Transmit Overhead Input Timing in N or SLC®96 Framing Format Mode
346
Figure 43.: DS1 Transmit Overhead Input Interface Module in T1DM Framing Format Mode
346
Figure 44.: Block Diagram of the DS1 Receive Overhead Output Interface of XRT86VL38
347
Figure 45.: DS1 Receive Overhead Output Interface Module in ESF Framing Format Mode
349
Figure 46.: DS1 Receive Overhead Output Interface Timing in N or SLC®96 Framing Format Mode
350
Figure 47.: DS1 Receive Overhead Output Interface Timing in T1DM Framing Format Mode
351
Figure 48.: Block Diagram of the E1 Transmit Overhead Input Interface of XRT86VL38
351
Figure 49.: E1 Transmit Overhead Input Interface Timing
353
Figure 50.: Block Diagram of the E1 Receive Overhead Output Interface of XRT86VL38
354
Figure 51.: E1 Receive Overhead Output Interface Timing
355
Figure 52.: TAOS (Transmit All Ones)
356
Figure 53. Simplified Block Diagram of the Ataos Function
356
Figure 54.: Network Loop up Code Generation
356
Figure 55.: Network Loop down Code Generation
357
Figure 56.: Long Haul Line Build out with -7.5Db Attenuation
357
Figure 57.: Long Haul Line Build out with -15Db Attenuation
358
Figure 58.: Long Haul Line Build out with -22.5Db Attenuation
358
Figure 59.: Arbitrary Pulse Segment Assignment
359
Figure 60.: Typical Connection Diagram Using Internal Termination
361
Figure 61.: Typical Connection Diagram Using Internal Termination
362
Figure 62.: Simplified Block Diagram of the Equalizer and Peak Detector
363
Figure 63.: Simplified Block Diagram of the Cable Loss Indicator
363
Figure 64. Test Configuration for Measuring Receive Sensitivity
364
Figure 65.: Process Block for Automatic Loop Code Detection
365
Figure 66.: Simplified Block Diagram of the Rxmute Function
366
Figure 67.: Interfacing the Transmit Path to Local Terminal Equipment
367
Figure 69.: Waveforms for Connecting the Transmit Payload Data Input Interface Block to Local Terminal Equipment 357 Figure 68.: Interfacing the Receive Path to Local Terminal Equipment
368
Figure 70.: Waveforms for Connecting the Receive Payload Data Input Interface Block to Local Terminal Equipment
369
Figure 71.: Transmit Non-Multiplexed High-Speed Connection to Local Terminal Equipment Using MVIP 2.048Mbit/S, 4.096Mbit/S, or 8.192Mbit/S
370
Figure 72.: Receive Non-Multiplexed High-Speed Connection to Local Terminal Equipment Using MVIP 2.048Mbit/S, 4.096Mbit/S, or 8.192Mbit/S
370
Figure 73.: Waveforms for Connecting the Transmit Non-Multiplexed High-Speed Input Interface at MVIP 2.048Mbit/S, 4.096Mbit/S, and 8.192Mbit/S
371
Figure 74.: Waveforms for Connecting the Receive Non-Multiplexed High-Speed Input Interface at MVIP 2.048Mbit/S, 4.096Mbit/S, and 8.192Mbit/S
371
Figure 75.: Interfacing XRT86VL38 Transmit to Local Terminal Equipment Using 16.384Mbit/S, HMVIP 16.384Mbit/S, and H.100 16.384Mbit/S
375
Figure 76.: Timing Signal When the Framer Is Running at Bit-Multiplexed 16.384Mbit/S Mode
375
Figure 77.: Waveforms for Connecting the Transmit Multiplexed High-Speed Input Interface at HMVIP and
376
Figure 78.: Interfacing XRT86VL38 Receive to Local Terminal Equipment Using 16.384Mbit/S, HMVIP 16.384Mbit/S, and H.100 16.384Mbit/S
377
Figure 79.: Timing Signal When the Receive Framer Is Running at 16.384Mhz Bit-Mulitplexed Mode
377
Figure 80.: Timing Signal Wehn the Receive Framer Is Running at HMVIP and H100 16.384Mhz Mode
377
Figure 81.: Timing Diagram of the Txsig Input
379
Figure 82.: Timing Diagram of the Rxsig Output
379
Figure 83.: Interfacing the Transmit Path to Local Terminal Equipment
380
Figure 85.: Waveforms for Connecting the Transmit Payload Data Input Interface Block to Local Terminal Equipment 370 Figure 84.: Interfacing the Receive Path to Local Terminal Equipment
381
Figure 86.: Waveforms for Connecting the Receive Payload Data Input Interface Block to Local Terminal Equipment
382
Figure 87.: Transmit Non-Multiplexed High-Speed Connection to Local Terminal Equipment Using MVIP 2.048Mbit/S, 4.096Mbit/S, or 8.192Mbit/S
383
Figure 89.: Waveforms for Connecting the Transmit Non-Multiplexed High-Speed Input Interface at MVIP 2.048Mbit/S, 4.096Mbit/S, and 8.192Mbit/S
384
Figure 88.: Receive Non-Multiplexed High-Speed Connection to Local Terminal Equipment Using MVIP 2.048Mbit/S, 4.096Mbit/S, or 8.192Mbit/S
384
Figure 90.: Waveforms for Connecting the Receive Non-Multiplexed High-Speed Input Interface at MVIP 2.048Mbit/S, 4.096Mbit/S, and 8.192Mbit/S
385
Figure 91.: Interfacing XRT86VL38 Transmit to Local Terminal Equipment Using 16.384Mbit/S, HMVIP 16.384Mbit/S, and H.100 16.384Mbit/S
387
Figure 92.: Timing Signals When the Transmit Framer Is Running at 12.352 Bit-Multiplexed Mode
387
Figure 93.: Timing Signals When the Transmit Framer Is Running at 16.384 Bit-Multiplexed Mode
389
Figure 94.: Timing Signals When the Transmit Framer Is Running at HMVIP / H.100 16.384Mhz Mode
391
Figure 95.: Interfacing XRT86VL38 Receive to Local Terminal Equipment Using 16.384Mbit/S, HMVIP 16.384Mbit/S, and H.100 16.384Mbit/S
392
Figure 96.: Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at 12.352Mbit/S Mode
392
Figure 97.: Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at 16.384Mbit/S Mode
392
Figure 98.: Waveforms for Connecting the Receive Multiplexed High-Speed Input Interface at HMVIP and H.100 16.384Mbit/ S Mode
393
Figure 99.: Timing Diagram of the Txsig_N Input
395
Figure 100.: Simple Diagram of E1 System Model
405
Figure 101.: Generation of Yellow Alarm by the Repeater Upon Detection of Line Failure
406
Figure 102.: Generation of AIS by the Repeater Upon Detection of Line Failure
407
Figure 103.: Generation of Yellow Alarm by the CPE Upon Detection of AIS Originated by the Repeater
408
Figure 104.: Generation of CAS Multi-Frame Yellow Alarm and AIS16 by the Repeater
409
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