1. Manuals
  2. Brands
  3. Exar Manuals
  4. PCI Card
  5. XRT71D00
  6. Manual

Exar XRT71D00 Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
TAN-042
Designing the XRT71D00 and the XRT73L00 Devices to
operate in the Host Mode, and to be accessed via a single Chip
Select pin.
Preliminary
July 19, 2001
Revision 1.03
DESIGNING THE XRT71D00 AND THE XRT73L00
DEVICES TO OPERATE IN THE HOST MODE, AND TO
BE ACCESSED VIA A SINGLE CHIP SELECT PIN
1

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the XRT71D00 and is the answer not in the manual?

Questions and answers

Related Manuals for Exar XRT71D00

Summary of Contents for Exar XRT71D00

  • Page 1 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 DESIGNING THE XRT71D00 AND THE XRT73L00 DEVICES TO OPERATE IN THE HOST MODE, AND TO...

  • Page 2: Table Of Contents

    2.2 BACKGROUND INFORMATION – THE XRT71D00 1-CHANNEL DS3/E3/STS-1 JITTER ATTENUATOR IC ........................... 7 3.0 THE CHANNEL ASSIGNMENT FEATURE OF THE XRT71D00 DEVICE ........9 4.0 HARDWARE DESIGN CONSIDERATIONS ..................12 4.1 DESIGN CONSIDERATIONS WHEN THE JITTER ATTENUATOR IS DESIGNED IN THE RECEIVE PATH ............................

  • Page 3: Introduction

    1.0 INTRODUCTION The purpose of this Applications Note is two-fold. a. To describe a possible approach that one can use to interface the XRT71D00 DS3/E3/STS-1 Jitter Attenuator to the XRT73L00 DS3/E3/STS-1 LIU IC, while operating each device in the “Host” Mode. In particular, this Applications Note...

  • Page 4: Background Information On The Xrt73L00 And Xrt71D00 Devices

    TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 2.0 BACKGROUND INFORMATION ON THE XRT73L00 AND XRT71D00 DEVICES The next couple of sections present a detailed description of both the XRT73L00 and the XRT71D00 devices.
  • Page 5 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 • SDI – Serial Data In • SDO – Serial Data Out •...
  • Page 6 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 Register Bit-Format Address Command Type Register 0x00 RLOL RLOS ALOS...

  • Page 7: Background Information - The Xrt71D00 1-Channel Ds3/E3/Sts-1 Jitter Attenuator Ic

    Mode/Configuration selection is achieved by setting certain input pins either “HIGH” or “LOW”. If the user configures the XRT71D00 device to operate in the “Hardware” Mode, the user can configure the XRT71D00 device into a wide variety of modes, via the following external input pins.
  • Page 8 Preliminary July 19, 2001 Revision 1.03 Therefore, for Host Mode Operation, the XRT71D00 device provides the user with five (5) pins (4 inputs and 1 output) that can be used to control various aspects of the XRT71D00 device. The bit-format of the Command Register set, within the XRT71D00 Jitter Attenuator device is presented below in Figure 2.

  • Page 9: The Channel Assignment Feature Of The Xrt71D00 Device

    • Ch_Addr_0 (Pin 28) • Ch_Addr_1 (Pin 15) A XRT71D00 device (within a given system) can be assigned a “Channel Number” by setting the “Ch_Addr_0” and “Ch_Addr_1” input pins either high or low. The relationship between the states of the “Ch_Addr_0” and the “Ch_Addr_1” input pins, and...
  • Page 10 Channel 2 Not Valid If a given XRT71D00 device is assigned to “Channel 0” then it will only respond to READ/WRITE operations to Address locations 0x06 and 0x07 (within the device). If the Microprocessor attempts to perform write operations to address locations “0x0E” and “0x16”, then the XRT71D00 device will ignore this particular operation.
  • Page 11 Figure 3, The Bit-Format of the “Composite Set” of Command Registers (from the XRT73L00 and the XRT71D00 Device). NOTE: The “shaded” register bits (within Figure 4) actually reside within the XRT71D00 device. Conversely, the “un-shaded” register bits actually reside within the XRT73L00 device.

  • Page 12: Hardware Design Considerations

    Jitter Attenuator and the LIU IC. b. JA_LIU_CS* This signal is tied to the CS* (Chip-Select) input pins of both the XRT71D00 and the XRT73L00 devices. Therefore, pulsing the “JA_LIU_CS*” input signal “low” asserts Chip Select for both of these devices, simultaneously.
  • Page 13 SDO output of the XRT71D00 device. This 475 Ω resistor serves to isolate the data, being output via the SDO output pin, of the XRT71D00 device; from the SDO output pin of the XRT73L00 device.
  • Page 14 July 19, 2001 Revision 1.03 2. The XRT71D00 device has been designed to operate in the Receive Path (Figure Figure 4 presents a schematic design in which the Jitter Attenuator is placed in the “Receive Path” such that the “RPOS”, “RNEG” and “RCLK” output signals (from the XRT73L00 LIU IC) are being routed to the “RPOS”, “RNEG”...

  • Page 15: Design Considerations When The Jitter Attenuator Is Designed In The Receive Path

    4.1 DESIGN CONSIDERATIONS WHEN THE JITTER ATTENUATOR IS DESIGNED IN THE RECEIVE PATH If the user has designed his/her board such that the XRT71D00 device is operating in the “Receive Path” (as illustrated in Figure 4), then it is imperative that the two devices be configured such that the “set-up”...
  • Page 16 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 FIGURE 4, SCHEMATIC DESIGN OF XRT71D00 DEVICE BEING INTERFACED TO THE XRT73L00 DEVICE (IN THE RECEIVE...
  • Page 17 REG_RESET Ch_Addr_0 Ch_Addr_1 SCLK STS-1 0.01uF GNDD MTIP GNDD GNDA XRT71D00 EXCLK MRING NOTE: In this Configuration, the XRT71D00 device should 44.736MHz TCLK TTIP be assigned a "Channel 31.6 Address" of 00. TxPOS TPDATA T3001 TxNEG TNDATA TRING 31.6 TxOFF...
  • Page 18 Registers (from the XRT73L00 and the XRT71D00 Device), when the XRT71D00 device is configured to operate in the “Receive Path”. If the above-mentioned configuration is implemented, then the XRT71D00 device will be provided with the following set-up and hold times, for each of the three (3) data rates.

  • Page 19: Design Considerations When The Jitter Attenuator Is Designed In The Transmit Path

    4.2 DESIGN CONSIDERATIONS WHEN THE JITTER ATTENUATOR IS DESIGNED IN THE TRANSMIT PATH If the user has designed his/her board such that the XRT71D00 device is operating in the “Transmit Path” (as illustrated in Figure 6), then it is imperative that the two devices be configured such that the “set-up”...
  • Page 20 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 FIGURE 6, SCHEMATIC DESIGN OF XRT71D00 DEVICE BEING INTERFACED TO THE XRT73L00 DEVICE (IN THE TRANSMIT...
  • Page 21 RxDGND AGND GNDD DGND TxAGND GNDD GNDA XRT73L00 XRT71D00 NOTE: In this Configuration, the XRT71D00 device should be assigned a "Channel Address" of 00. JA_FIFO_ALARM Title Schematic Design for TAN_042 (2) Size Document Number XRT71D00_IN_TX_PATH Date: Monday, May 07, 2001...
  • Page 22 Registers (from the XRT73L00 and the XRT71D00 Device), when the XRT71D00 device is configured to operate in the “Transmit Path”. If the above-mentioned configuration is implemented, then the XRT71D00 device will be provided with the following set-up and hold times, for each of the three (3) data rates.

  • Page 23: Power Condition Considerations For The Xrt73L00 And The Xrt71D00 Devices

    GND pins, in order to ensure high-quality performance of the XRT73L00 device. The XRT71D00 device is also a mixed signal device. This particular device consists of an Analog and Digital PLL. Each of these PLLs is used to generate high-speed signals that support loop filtering within the Jitter Attenuator IC.
  • Page 24 XRT73L00 and XRT71D00 devices. The XRT73L00 and XRT71D00 “GND” Pins Tie all XRT73L00 and XRT71D00 “GND” pins to the system ground plane. In cases where there are separate analog and digital ground planes, tie all “GND” pins to the analog ground.
  • Page 25 • To an LC filter (consisting of L3 and C4), prior to being routed to the Receive Analog VDD pin of the XRT73L00 LIU IC (pin 10) and the Analog VDD pin of the XRT71D00 Jitter Attenuator IC (pin 7).
  • Page 26 NOTE: Current consumption measurements were made while the XRT73L00 device was operating in the “STS-1” Mode, and transmitting/receiving an “All Ones” pattern. Similarly, the current consumption (via each of the Power Supply pins, of the XRT71D00 device) is presented below in Table 5.
  • Page 27 Total Current Consumption 28.85mA NOTE: Current measurements were made when the XRT71D00 device was operating in the STS-1 Mode, and powered at 3.35V. For inductors L2 and L3, the user should select as large a value as the selected size (0805, 1210 or 1812 etc.) will allow while keeping the DC resistance of each inductor to less...
  • Page 28 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 DECOUPLING CAPACITORS We strongly recommend that the user provide de-coupling capacitors for each VDD pin of the XRT73L00 device (Analog as well as Digital).

  • Page 29: The Bnc Connector Shields

    TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 6.0 THE BNC CONNECTOR SHIELDS As a general rule, we highly recommend that the customer either AC or DC couple the BNC connector shield to Frame or Chassis Ground.

  • Page 30: Appendix A - Register Description For The Xrt73L00 Ds3/E3/Sts-1 Liu Ic

    TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 APPENDIX A – REGISTER DESCRIPTION FOR THE XRT73L00 DS3/E3/STS-1 LIU IC...
  • Page 31 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 The Bit Format of the Command Registers, within the XRT73L00 device is presented below in Figure A1.
  • Page 32 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 TTIP Tx_FAIL T3001 TRING Tx_OFF TXOFF MTIP MRING XRT73L00 Figure A2, Illustration of the Required Connection, between the MTIP/MRING and TTIP/TRING pins, in order to permit “Transmit Drive Monitoring”...
  • Page 33 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 Bit D3 – RLOS (Receive Loss of Signal) This “Read-Only” bit-field indicates whether or not the XRT73L00 device is currently declaring an LOS condition.
  • Page 34 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 Command Register CR1 Bit D0 – TXBIN (Transmitter - Single Rail Enable/Disable) This “Read/Write”...
  • Page 35 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 Bit D2 – TXCLKINV (Transmit Clock Invert) This “Read/Write” bit-field permits the user to configure the Transmit Section of the LIU IC to latch the contents of the “TPDATA/TNDATA”...
  • Page 36 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 Command Register CR2 Bit D0 – REQDIS (Receive Equalizer Enable/Disable) This “Read/Write”...
  • Page 37 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 Setting this bit-field to “0” enables both the B3ZS/HDB3 Encoder and Decoder blocks within the LIU IC.
  • Page 38 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 Bit D2 – RCLK2/LCV (RCLK2 or LCV Output Select) This “Read/Write” bit-field permits the user to configure the “RCLK2/LCV” output pin to function as either the “RCLK2”...
  • Page 39 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 Command Register CR4 Bit D0 – RLB (Loop-back Select) This “Read/Write” bit-field, along with “D1” (LLB) permits the user to configure the XRT73L00 device to operate in either the “Analog-Local”, “Digital-Local”...
  • Page 40 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 Setting this bit-field to “1” configures the XRT73L00 device to operate in the “E3”...

  • Page 41: Appendix B - Register Description For The Xrt71D00 Ds3/E3/Sts-1 Jitter Attenuator Ic

    TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 APPENDIX B – REGISTER DESCRIPTION FOR THE XRT71D00 DS3/E3/STS-1 JITTER ATTENUATOR IC...
  • Page 42 Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 The Command Register Format for the XRT71D00 device is presented below in Figure Register Bit-Format Addr. Command Type Register...
  • Page 43 D1 – CLKES (Clock Edge Select) This “Read/Write” bit-field permits the user to configure the following. a. Which edge of RCLK that the XRT71D00 device will sample the data (applied at the “RPOS” and “RNEG” input pins). b. Which edge of RRCLK that the XRT71D00 device will output the data (via the “RRPOS”...
  • Page 44 XRT71D00 device to operate in either the DS3, E3 or STS-1 Mode. Setting this bit-field to “1” configures the XRT71D00 device to operate in the E3 Mode. Conversely, setting this bit-field to “0” configures the XRT71D00 device to operate in the “DS3”...
  • Page 45 July 19, 2001 Revision 1.03 Setting this bit-field to “0” configures the XRT71D00 device to operate in either the “DS3” or “E3” Modes. In this setting the state of the “D4” (E3/DS3*) bit-field will dictate whether the chip is operating in the DS3 or E3 Mode.

  • Page 46: Appendix C - Description Of Microprocessor Serial Interface Pins

    TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 APPENDIX C – DESCRIPTION OF MICROPROCESSOR SERIAL INTERFACE PINS...

  • Page 47: A Brief Description Of The Microprocessor Serial Interface Pins

    The Microprocessor (or the entity responsible for reading data from and writing data into the Command Registers, within the XRT71D00 or the XRT73L00 devices) must apply a Clock Signal to this input pin. As the Microprocessor Serial Interface receives this clock signal, it will do the following.
  • Page 48 “default” values of these Command Registers. Further, in the case of the XRT71D00 device, the contents of the FIFO (within the chip) will be flushed. Additionally, the FIFO_READ...

  • Page 49: Using The Microprocessor Serial Interface

    TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 C.2 USING THE MICROPROCESSOR SERIAL INTERFACE The following instructions, for using the Microprocessor Serial Interface, are best understood by referring to the diagram in Figure 28.
  • Page 50 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 Bits 6 and 7: The next two bits, A4 and A5 must be set to “0”, as shown in Figure 23.
  • Page 51 TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 SCLK High Z Denotes a “Don’t Care” Value Figure C.1 – Illustration on How to Use the Microprocessor Serial Interface of the...

  • Page 52: Appendix D - Contact Information For Api-Delevan

    TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 APPENDIX D - CONTACT INFORMATION FOR API- DELEVAN: Corporate Office...

  • Page 53: Appendix E - Revision Change History

    TAN-042 Designing the XRT71D00 and the XRT73L00 Devices to operate in the Host Mode, and to be accessed via a single Chip Select pin. Preliminary July 19, 2001 Revision 1.03 APPENDIX E – REVISION CHANGE HISTORY CHANGES FROM REVISION 1.02 TO 1.03 Corrected and added Figure Numbers in the text, where they were previously missing.

This manual is also suitable for:

Xrt73l00

Table of Contents