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7.1.3
SSB Cell Layout
GPI
O
Wifi
1M71
1M59
1F02
Xilinx
DDR2
CY3
C40
uart
PCI/
XIO
I
pci/xio
²
C
DDR2
DDR2
Ethernet
FLASH
Class-D
Figure 7-2 SSB layout cells (top view)
Circuit Descriptions
1M01
VGA
serv
L/R
Y
Pb
1E51
1E50
Pr
Lo
SPO
L
Ro
R
HDMI
RJ45
MUX
Q549.3E LA
7.
1R12
Head
Right
Left
CVBS
Tuner
Y/C
USB
2.0
HD
MI
1.3
1P00
CA
18310_201_090317.eps
090317
EN 41
2009-Aug-07
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