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5. Communication buffer and reset circuit
In the communication buffer circuit, the transmission signal (F-TXD)
and communication permit signal (F-DTR) from the copier are
received by the buffer IC 74HC14 (IC101), while the reception signal
(F-RXD) and communication request signal (F-DSR) transmitted from
the finisher to the copier are outputted from the transistor Q101 and
Q102.
F-TXD
F-RXD
F-DTR
F-DSR
F-RES
from Copier
Signal
name
F-TXD
Signal line from copier to finisher
F-RXD
Signal line from finisher to copier
F-DTR
Status display signal line for the signal showing communication permit
from finisher to copier
F-DSR
Status display signal line for the signal showing communication request
from finisher to copier
F-RES
Hard rest signal from copier
6. Sensor input circuit
The signal from each sensor connected to 10 kohm pull-up resistance
and noise-removing 1000 pF capacitor, and connected through 10
kohm protective resistance to CPU, and expansion I/O Schmitt trigger
input port.
+5V
+5V
R125
4.7K
RT1N141C
+5V
R113
4.7K
RT1N141C
Q102
+5V
R115
1K
0.1U
Description
H.P.sensor
*1
AMP
*1:Rated Voltage Sircuit
Transport system sensor
240
The reset signal from the copier is also received by the IC101 and
inputted to the CPU's reset terminal (active at L). In addition, the
reversion signal is inputted to the expansion I/O reset terminal (active
at H). For each signal, a protective diode is inserted between +5V and
GND.
IC101
R126 4.7K
9
8
74HC14
Q101
10
10K
IC101
10K
R114
6
5
4.7K
74HC14
10K
IC101
10K
1
2
74HC14
C118 0.1U
C117 1000p
IC101
C120 1000p
74HC14
Start bit detection at H
Usual (marking state) at L
Start bit detection at L
Usual (marking state) at L
Communication from finisher to copier is inhibited at H
Communication from finisher to copier is permitted at L
No communication request from finisher to copier at H
Communication request from finisher to copier at L
Reset at H
Reset is released at L
The sensor signal for transport system is input to the schmitt trigger
input port because the sensor input circuit is not provided with rectifier
circuit.
+5V
+5V
10K
10K
1000PF
+5V
+5V
10K
PA or PB
10K
I/O
(IC03)
1000PF
*2 Schumit trigger input port
9 – 6
AR-FN3
14
RXD0/P92
F-TXD
IC101
11
12
TXD0/P90
F-RXD
74HC14
17
P95
F-DTR
16
P94
F-DSR
63
RES
RES/
C131
CPU
0.1U
(IC03)
33
RESET
RES
I/O
(IC11)
Logic (connector level)
P**
CPU
(IC02)
2
8/19/1999
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