Pci-E Slot Breakdown; M.2 And U.2 Slot Breakdown - EVGA Z270 FTW-K Initial Installation

EVGA Z270 FTW – K (132-KS-E277)

PCI-E Slot Breakdown

PCI-E Lane Distribution (All Socket 1151
processors are 16 lanes.)
PE1 – x4 (Gen3, x4 lanes from PCH, shared with U.2)

PE2 – x16 (Gen3, x16 lanes from CPU, x8 shared with PE4)

PE3 – x1 (Gen3, x1 lanes from PCH)

PE4 – x8 (Gen3, x8 lanes from CPU, shares 8 of PE2's 16 lanes)

PE5 – x16 (Gen3, x1 lanes from PCH)


M.2 and U.2 Slot Breakdown

M.2 Lane Distribution
M.2 Key-M (110mm, Top) – x4 (Shares with SATA Port 4/5)

o M.2 Enable/Disable is set within the BIOS
M.2 Key-M (110mm, Bottom) – x4 (Shares with SATA Port 0/1)

o M.2 Enable/Disable is set within the BIOS
M.2 Key-E (32mm) – x1 (Shares with PE3)

o M.2 Enable/Disable is set within the BIOS
U.2 x4 PCI-E Gen 3 lanes (Shares with PE1)

o U.2 Enable/Disable is set within the BIOS

This motherboard does NOT have any lane replication via PLX; all lanes are
native and derived from CPU or PCH.
backwards compatibility for Gen 2 devices.
This also allows for improved
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