Sony Ericsson GR47 Integrator's Manual page 37

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PCM Timing Diagrams
The PCM timing is shown in Figure 5.8below and it is seen that
the CPU has 45 µs to serve an interrupt and setup data
channels. Data is sent on the falling edge of the sync pulse.
The data bits in PCMULD and PCMDLD are aligned so that the
MSB in each word occurs on the same clock edge as shown in
Figure 5.9.
Sync
Data
PCM signal timing is shown in Figure 5.9. The signals
characteristics are described in the tables following Figure 5.9.
LZT 123 7589 R2B
SYSTEM CONNECTOR INTERFACE
lk
Figure 5.8 16-bit word within 24-bit frame
CMCLK
t
PSS
CMSYN
t
PSH
t
CMIN
CMOUT
Figure 5.9 PCM Timing Diagram
Name Description
t PCMSYN (setup) to PCMCLK (fall)
PSS
t PCMSYN pulse length
PSH
t PCMI (setup) to PCMCLK (fall)
DSL
t PCMI (hold) from PCMCLK (fall)
DSH
t PCMO valid from PCMCLK (rise)
PDLP
Name Description
F PCM clock frequency
PCMCLK
125 µs
t
DSH
DSL
MSB
t
PDLP
X MSB D14
45 µs
D14 D13
D13
Typ. Unit
2.5 µs
5 µs
2.5 µs
2.5 µs
2.5 µs
Typ. Unit
200 kHz
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