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10. MICROPROCESSOR AND IC DATA
QY01 : ML9207-01
AD3
1
AD4
2
SEG1
3
SEG2
4
SEG3
5
SEG4
6
SEG5
7
SEG6
8
SEG7
9
SEG8
10
SEG9
11
SEG10
12
SEG11
13
SEG12
14
SEG13
15
SEG14
16
SEG15
17
SEG16
18
SEG17
19
SEG18
20
ML9207-01 Terminal Function
Pin No.
Pin Name
I/O
3~37
SEG1~35
O
FL display anode drive output pin
39~62
COM1~24
O
FL display grid drive output pin
1,2, 79, 80
AD1~4
O
FL display anode drive output pin
72~75
P1~4
O
General port output pin
71
V
DD
V
-GND: Power supply for logic block
DD
38, 78
V
DISP1~2
V
-V
: Power supply for FL display drive
DISP
FL
64
GND
For V
and V
, apply from same power source
DD
DISP
63, 76
V
FL1~2
70
DA
I
Serial data input pin (positive logic)
69
CP
I
Shift clock input pin
68
CS
I
Chip select input pin
67
RESET
I
Reset input pin
65
OSC0
I
Pin for self-oscillation
66
OSC1
O
60
COM22
59
COM21
58
COM20
57
COM19
56
COM18
55
COM17
54
COM16
53
COM15
52
COM14
51
COM13
50
COM12
49
COM11
48
COM10
47
COM9
46
COM8
45
COM7
44
COM6
43
COM5
42
COM4
41
COM3
Function
1-21
QD61 : CS4397
PCM MODE
Reset
RST
See Description
M4(AD0/CS)
See Description
M3(AD1/CDIN)
See Description
M2(SCL/CCLK)
See Description M0(SDA/CDOUT)
Digital Ground
DGND
Digital Power
VD
Digital Power
VD
Digital Ground
DGND
Master Clock
MCLK
Serial Clock
SCLK
Left/Right Clock
LRCK
Serial Data
SDATA
See Description
M1
Reset - RST
Pin 1, Input
Function:
The device enters a low power mode and all internal state
machines registers are reset when low. When
high, the device will be in a normal operation mode .
RST DESCRIPTION
0
Enabled
1
Normal operation mode
Digital Ground - DGND
Pins 6 and 9, Inputs
Function:
Digital ground reference.
Digital Power - VD
Pins 7 and 8, Input
Function:
Digital power supply. Typically 5.0 to 3.0 VDC.
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 256x, 384x, 512x or
768x the input sample rate in Single
Speed Mode; either 128x, 192x 256x or 384x the input sample
rate in Double Speed Mode; or 64x, 96x
128x or 192x the input sample rate in Quad Speed Mode. Tables
4-6 illustrate the standard audio sample
rates and the required master clock frequencies.
Sample
MCLK (MHz)
Rate (kHz)
256x
384x
512x
32
8.1920
12.2880
16.3840
24.5760
44.1
11.2896
16.9344
22.5792
33.8688
48
12.2880
18.4320
24.5760
36.8640
Table 4. Single Speed (16 to 50 kHz sample rates) Common Clock
Frequencies
Serial Clock - SCLK
Pin 11, Input
Function:
Clocks individual bits of serial data into the SDATA pin. The
required relationship between the Left/Right
clock, serial clock and serial data is defi ned by either the Mode
Control Byte in Control Port Mode or the
M0 - M4 pins in Hardware Mode. The options are detailed in
Figures 29-33
1
1
28
VREF
Voltage Reference
FILT+
Reference Filter
2
2
27
3
26
FILT-
Reference Ground
CMOUT
Common ModeS Voltage
4
25
5
5
24
AOUTL-
Differential Output
AOUTL+
Differential Output
6
6
23
VA
Analog Power
7
22
8
21
AGND
Analog Ground
AOUTR+
Differential Output
9
20
10
19
AOUTR-
Differential Output
AGND
Analog Ground
11
18
MUTEC
Mute Control
12
17
C/H
Control port/Hardware select
13
16
MUTE
Soft Mute
14
15
Left/Right Clock - LRCK
Pin 12, Input
Function:
The Left/Right clock determines which channel is currently being
input on the serial audio data input,
SDATA. The frequency of the Left/Right clock must be at the input
sample rate. Audio samples in
Left/Right sample pairs will be simultaneously output from the
digital-to-analog converter whereas
Right/Left pairs will exhibit a one sample period difference. The
required relationship between the
Left/Right clock, serial clock and serial data is defi ned by the
Mode Control Byte and the options are de-
tailed in Figures 29-33
Serial Audio Data - SDATA
Pin 13, Input
Function:
Serial audio data is input on this pin. The selection of the Digital
Interface Format is determined by set-
tings of the Mode select as detailed in Figures 29-33. The data is
clocked into SDATA via the serial clock
and the channel is determined by the Left/Right clock. The
required relationship between the Left/Right
clock, serial clock and serial data is defi ned by the Mode Control
Byte and the options are detailed inin
Figures 29-33
Soft Mute - MUTE
Pin 15, Input
Function:
The analog outputs will ramp to a muted state when enabled. The
ramp requires 1152 left/right clock cy-
cles in Single Speed, 2304 cycles in Double Speed and 4608
768x
cycles in Quad Speed mode. The bias volt-
age on the outputs will be retained and MUTEC will go active at
the completion of the ramp period.
The analog outputs will ramp to a normal state when this function
transitions from the enabled to disabled
state. The ramp requires 1152 left/right clock cycles in Single
Speed, 2304 cycles in Double Speed and
4608 cycles in Quad Speed mode. The MUTEC will release
immediately on setting MUTE = 1.
The converter analog outputs will mute when enabled. The bias
voltage on the outputs will be retained
and MUTEC will go active during the mute period.
Mute
DESCRIPTION
0
Enabled
1
Normal operation mode
1-22
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