PEP CP351 Manual page 28

CP351
2.2.1 Register Description
Table 2-3: CP351 Register Description
Name
WDG
S_BRB
BERR1
EN_WDG
TR_WDG
EN_BERR1
ABRB
LED_G
2.2.2 Watchdog Timer
A 512ms watchdog timer triggers the on-board system reset generator at timeout. Once
enabled via the board control/status register, the watchdog timer cannot be reset by
software. It must be re-triggered via the corresponding bit in the board control/status
register periodically within the timeout period.
2.2.3 On-Board Bus Error Timer
A 128µs timeout monitors the cycle lengths of data transfers to and from locations
beyond the CPU data bus buffer, including the on-board I/O and PROFIBUS interface.
After a timeout occurs, it generates an on-board BERR signal for error termination. This
timer is enabled/disabled via the board control/status register, which also supplies a tim-
eout status bit in order to identify bus errors generated by the on-board bus error timer.
There are two cases of bus error which are described in the following table.
Table 2-4: Bus Error Description
Cause
Reserved Address BERR0
On-Board BERR1
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Value Access
Read/Write
Read
Read/Write
1 Read/Write
1 Read/Write
1 Read/Write
1 Read
Read/Write
Timeout
100 ns
128 us
® PEP Modular Computers GmbH
Functional Description
Description
Set by watchdog timer when timeout has been
reached. Used to differentiate between resets
caused by the watchdog and resets caused by a
reset button (power up resets can be identified
within the 68360)
Boot jumper (S_BOOT) read back
Set by on-board bus error timer when timeout has
been reached. Used to identify BERR caused by
this timer.
Enable the watchdog timer. It can only be set
once, and remains enabled until the next reset.
Triggers the watchdog timer.
Enables the on-board bus error timer. It also mon-
itors all on-board I/O cycles, including the time
from the VME bus request to the VME bus grant.
ABORT read back
General purpose LED driver
Enable/Disable Possible
Permanently enabled
Set in board control register
ID 18983, Rev. 0101