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CP351
2. Functional Description
2.1 CP351 Address Map
The CP351 CPU360 address map shown in the table below is based on the recom-
mended default initialization of 68360 chip select logic.
Table 2-1: CP351 Address Map
Address (Hex)
HEX 00 xx xx xx
HEX 04 xx xx xx
HEX 07 00 0x xx
HEX 0A xx xx xx
HEX 10 00 00 00
HEX 0C xx xx xx
HEX 0D xx xx xB
HEX 40 00 00 00
HEX c0 00 00 00
2.2 Board Control/Status Register
An additional register for CP 351 control and status purposes is implemented in the glue
logic part of the QUICC-QSPAN interface. This register can also be accessed from the
PCI and the local side (QBUS).
Address:
Format:
Access:
Value after reset:
Table 2-2: Board Control/Status Register Bitmap
7
WDG
S_BRB
ID 18983, Rev. 0101
SRAM
SRAM
68360 internal RAM / register
QSPAN configuration / status registers
PROFIBUS Interface
RTC
board control/status register
PCI image 0
PCI image 1
CS7 + HEX B
Byte
Read/Write
HEX 00
6
5
BERR1
EN_WDG
® PEP Modular Computers GmbH
Functional Description
Device
4
3
TR_WDG
EN_BERR1
2
1
ABORT
LED_G
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