Intelligent profibus controller for compactpci systems (36 pages)
Summary of Contents for PEP VSBC-32
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VSBC-32 Combined VMEbus System Controller and Serial Communications Controller Board Manual ID 21168, Rev. Index 04 Jul 00 The product described in this manual is in compliance with all applied CE stan- dards. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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PEP Modular Computers GmbH. Disclaimer: PEP Modular Computers GmbH rejects any liability for the cor- rectnesss and completeness of this manual as well as its suitabil- ity for any particular purpose.
This document contains information proprietary to PEP Modular Computers . It may not be copied or transmitted by any means, disclosed to others or stored in any retrieval system or media, without the prior written consent of PEP Modular Computers GmbH or one of its autho- rized agents.
However, the life expectancy of your product can be drastically reduced by improper treat- ment during unpacking and installation. Therefore, in the interests of your own safety and of the correct operation of your new PEP product, you are requested to conform with the follow- ing guidelines.
Preface General Instructions on Usage • In order to maintain PEP’s product warranty, this product must not be altered or modified in any way. Changes or modifications to the device, which are not explicitly approved by PEP Modular Computers and described in this manual or received from PEP Technical Support as a special handling instruction, will void your warranty.
However, no other warranties that may be HARDWARE WARRANTY granted or implied by anyone on behalf of PEP are valid unless the consumer has the express written consent of PEP Modular Computers . PEP Modular Computers warrants their own products, excluding software, to be free from manufacturing and material defects for a period of 24 consecutive months from the date of purchase.
Trade Association (VITA): http://www.vita.com Many system-relevant features that are specific for VMEbus systems can be found in the ANSI/VITA VME64 Standard and in the VITA/ PEP CXC MPI Specification which, despite its name, applies also to VMEbus MPI carriers. The VME64 Standard includes the following information: •...
1.2.1 Board-Specific Information The VSBC-32(E) is a 3U (Enhanced) CXC combined system and communications con- troller board that can operate in either a VMEbus or a mixed VMEbus+CXC environ- ment. The board is based on the Motorola Quad Integrated Communications Controller “QUICC”...
The below described frontend connectivity and interface expandibility are common to all board variants. 1.2.3 Board Connectivity and Interface Expandibility The VSBC-32(E) mainboard is provided with the following standard connectors: • Non-optoisolated RS232 serial interface (two RJ45 connectors, on frontpanel) •...
If used as a system controller, the board should be always installed in the system slot. If a CXM-SIO3 or a CXM-SCSI module is used in combination with the VSBC-32(E), the module can be “sandwiched” with the controller, Communication between the controller and the I/O module being acchieved via the VSBC-32(E)’s on-board CXC connector.
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To avoid damaging of your Bootstrap Loader and, consequently, leaving your board unusable, please read the separate Bootstrap Loader manual before re-setting the flash contents of your VSBC- 32 board. Operating Systems The VSBC-32(E) can operate under the following operating systems: • OS-9 • VxWorks ®...
Mainboard: 130g Weight Serial interface piggyback: 20..30g Memory piggyback: 1.5 Applied Standards 1.5.1 CE Compliance The PEP Modular Computers’ VMEbus and (e)CXC systems comply with the require- ments of the following CE-relevant standards: • Emission EN50081-1 • Immission EN50082-2 •...
LAN, WAN or fieldbusses (CAN, LON, PROFIBUS). In fact, both the VSBC-32 and the VSBC-32E allow for a wide range of serial interfaces based on the MC68(EN)360 controller which is able to handle up to six serial communi- cations channels.
VMEbus interrupt controller. Arbitration is single-level FAIR (compare VME64 Specification Rule 3.14/Observation 3.17). If the VSBC-32(E) is used as a system controller and consequently placed in the VMEbus backplane’s system slot, a special detection function provided by the board makes any “slot 1” jumper setting superfluous. The VSBC-32(E) also provides a bus monitor for the VMEbus.
Control/status register 2.2.2 Memory Configurations The VSBC-32(E) allows a significant variety of memory configurations. The special DRAM/flash piggybacks (DM60x), for instance, allows the user to take advantage of the on-board programming facility to produce low cost upgrades by simply overwriting exist- ing stored data.
VSBC-32 Functional Description A schematic overview of all possible memory configurations is given in the figure on the next page. Figure 2-1: VSBC-32 Memory Configuration Variants Mainboard VSBC-32 MC68360 SRAM 256kB 25MHz 2kbit EEPROM SRAM 256kB CPU/Serial VSBC-32E SRAM Comm.
RS485 serial I/O interface implemented on a dedicated piggy- back to be connected to the SI Interface of either the VSBC-32(E) or the external serial interface module. RS422 is not commonly available on the VSBC-32(E) but can be sup- plied by PEP Modular Computers on special request.
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(SI) piggybacks (RS232, RS485, Ethernet). The SCC1 channel of the MC68(EN)360 provides the interface to the serial interface (SI) piggyback installed on the VSBC-32(E). All other channels of the controller (SCC2, SCC3 and SCC4) are ported to the CXC interface except for the SI-PB232 piggyback which has on-board additional control provided by the SCC4 channel through the piggyback interface for serial interface piggybacks.
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Depending on whether the piggyback interface for serial interface (SI) piggybacks is configured as an Ethernet port (board versions with Ethernet piggyback) or not, the serial interfaces channels of the VSBC-32(E) can assume the functions described in the following figure.
2.4.1 Serial I/O Interfaces The mainboard RJ12 RS232 frontpanel connec- Figure 2-5: Orientation of tors BU7 and BU8 of the VSBC-32(E) are pro- the VSBC-32(E) Mainboard vided with TxD and RxD signals by the controller’s Serial Interfaces SMC1 and SMC2 channels and supply RS232 interface software handshake (XON/XOFF) capa- bility.
2.4.4 EPROM DIP Sockets The VSBC-32(E) is equipped with two sets of (flash) EPROM DIP sockets (two 32-pin row female sockets). The pinout of these DIP sockets includes all signals for the connec- tion of up to 1MB of SRAM.
VMEbus interrupt controller. Arbitration is single-level FAIR (compare VME64 Specification Rule 3.14/Observation 3.17) on BR3*. If the VSBC-32(E) is used as a system controller, a special detection function provided by the board, which is also readable within the VMEbus control/status register, makes any “slot 1”...
VSBC-32 Functional Description The VSBC-32(E) also provides a bus monitor for the VMEbus. A 128µs bus error timer monitors the cycle lengths of the VMEbus data transfer and generates a VMEbus BERR* signal on timeout. This timer is enabled and disabled via the VMEbus control/status reg- ister which contains alsao a timeout status bit in order to identify the bus errors generated by the bus monitor.
For general CXC information, including generic pinouts and a comparison of the MC68(EN)360 and the MC68302 CPU pinouts on the CXC, please refer to the “CXC” appendix attached to this manual, the PEP Modular Computers CXC Reference Manual or to the CXC Specification.
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1 Reserved Pin: On a standard VSBC-32 board, this signals is used for UART ports at BU7 and BU8. 2 Reserved Pin: On a standard VSBC-32 board, this signal is used for SPI to which the EEPROM is already con- nected.
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1 Reserved Pin: On a standard VSBC-32 board, this signals is used for UART ports at BU7 and BU8. 2 Reserved Pin: On a standard VSBC-32 board, this signal is used for SPI to which the EEPROM is already con- nected.
During VMEbus cycles the on-board bus error timer is reset as soon as the VSBC-32(E) gains VMEbus ownership, i.e. the time gap between a VMEbus request and the starting of the VMEbus cycle is monitored by the on-board bus error timer.
‘Watchdog timer running’ is a status that is displayed by the yellow front panel LED. For the location of the Watchdog LED please refer to the VSBC-32(E) Frontpanel figure in the “Introduction” chapter of this manual.
Gold Cap provides a minimum of 10 hours backup time. Laboratory tests at PEP indicate a typical backup time of 1 week for both 256kB and 1MByte SRAM plus RTC (the typical on-board backup current is below 2µA). The charge and discharge behaviour of Gold Caps is documented in the graphics overleaf.
2.9 Address Decoder 2.9.1 Basic Structure The address decoder of the VSBC-32(E) consists of external logic and the MC68(EN)360 internal memory controller. The MC68(EN)360’s internal chip select logic decodes all the basic address areas following its initialization. The eight chip select out- puts of the processor are connected to the different devices as shown in the following tablle.
3.2 Software Installation There are no special requirements for software installation. However, many components of the VSBC-32(E) are controlled by the MC68(EN)360 processor. Due to this fact, the controller requires a special initialization sequence before any other software can be started.
4. Configuration 4.1 Hardware Configuration The VSBC-32(E) has fifteen jumpers fitted to the board. The list of default jumper set- tings is shown below. A board layout with all jumper locations and pinouts is supplied in the Board Layouts section of the Introduction chapter of this manual.
4.2.1 Address Map Software applications may require to configure data in the VSBC-32(E) registers. For this pur- pose, the configurable memory is described in the following. The address map in the table below is based on the recommended default initialization of the MC68(EN)360 chip select logic.
DRAM and flash memory as indicated in the table below are available for a wide variety of PEP CPU boards. All configurations have 32-bit access and a maximum address range of 64 MB. In addition jumpers are available for providing write protection.
10Base5 (AUI) Ethernet, • 10BaseT (twisted pair) Ethernet, • RS-232 modem compatible, • RS485 optoisolated (PROFIBUS), and are available for a wide variety of PEP CPU boards. Table B-1: SI Piggyback Types and Configurations Configuration Type Standard Connectors 10Base2 RG58...
B.2 SI-10B2 The SI-10B2 is a physical cheapernet (10Base2) interface to the 68EN360 Controller chip. It connects one of the range of PEP CPU boards to a 50 ohm coax cable via an RG58 BNC ‘T’ connector. The SI6-10B2 has two LEDs fitted; a red LED indicates collision detection and a yellow LED for data transmission.
B.4 SI-10BT The SI-10BT is a physical twisted pair (10BaseT) interface to the 68EN360 Controller chip. It connects one of the range of PEP CPU boards to an unshielded 100ohm twisted-pair cable via an RJ45 telephone jack. The SI-10BT has two LEDs fitted: a red LED indicates collision detection and a yellow LED for data.
Serial Interface Piggybacks B.5 SI-PB232 The SI-PB232 provides two RS-232 serial interfaces to the 68EN360 Controller chip. It connects one of the range of PEP CPU boards via two RJ45 telephone jacks. B.5.1 Front Panel View and Pinout Figure B-4: SI-PB232 Serial Interface Piggyback...
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Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
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