MSI MS-6199VA User Manual page 65

CPU to PCI Write Buffer
When this field is Enabled, writes from the CPU to the PCI bus are
buffered, to compensate for the speed differences between the CPU and the
PCI bus. When Disabled, the writes are not buffered and the CPU must wait
until the write is complete before starting another write cycle.
The choice: Enabled, Disabled.
PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer.
Burstable transactions then burst on the PCI bus and nonburstable
transactions don't.
The choice: Enabled, Disabled
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait
states.
The choice: Enabled, Disabled
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
The choice: Enabled, Disabled
PCI #2 Access #1 Retry
When PCI#2 (AGP bus) access to PCI#1 (PCI bus) has an error
occurred, this operation will set to retry.
The choice: Enabled, Disabled
AGP Master 1 WS Write
When Enabled, writes to the AGP(Accelerated Graphics Port) are
executed with one wait state.
The choice: Enabled, Disabled
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