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VGA Palette Snoop
Bit Setting
Disabled
Data read or written by the CPU is only directed to the
PCI VGA device's palette registers.
Enabled
Data read or written by the CPU is directed to both the
PCI VGA device's palette registers and the ISA VGA
device's palette registers, permitting the palette regis-
ters of both VGA devices to be identical.
The setting must be set to Enabled if any ISA bus adapter in the system
requires VGA palette snooping.
PCI Slot1 IRQ, PCI Slot2/5 IRQ, PCI Slot3 IRQ, PCI Slot4 IRQ
This item specifies the IRQ line for each PCI slot. Settings: 3, 4, 5, 7, 9, 10, 11
and Auto. Selecting Auto allows BIOS to automatically determine the IRQ line
for each PCI slot.
DMA Channel 0/1/3/5/6/7
These items specify the bus that the system DMA (Direct Memory Access)
channel is used.
The settings determine if AMIBIOS should remove a DMA from the available
DMAs passed to devices that are configurable by the system BIOS. The
available DMA pool is determined by reading the ESCD NVRAM. If more
DMAs must be removed from the pool, the end user can reserve the DMA by
assigning an ISA/EISA setting to it.
IRQ 3/4/5/7/9/10/11
These items specify the bus where the specified IRQ line is used.
The settings determine if AMIBIOS should remove an IRQ from the pool of
available IRQs passed to devices that are configurable by the system BIOS.
The available IRQ pool is determined by reading the ESCD NVRAM. If more
IRQs must be removed from the IRQ pool, the end user can use these settings
to reserve the IRQ by assigning an ISA/EISA setting to it. Onboard I/O is
configured by AMIBIOS. All IRQs used by onboard I/O are configured as
PCI/PnP. If all IRQs are set to ISA/EISA, and IRQ 14/15 are allocated to the
onboard PCI IDE, IRQ 9 will still be available for PCI and PnP devices. Avail-
able settings: ISA/EISA and PCI/PnP.
Action
3-19
BIOS Setup
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