Panasonic EB-X300 Service Manual page 26

Transceiver - - Receiver
RXIN
RXIP
RXQN
RXQP
VGA
The transceiver uses a direct conversion receiver which eliminates the requirement for Intermediate Frequency (IF) stages.
The transceiver chip includes three LNAs for each band, a quadrature demodulator, baseband amplifier circuit with I/Q outputs
and three stages of DC-offset correction.
The DCOC correction loop ensures DC-offsets, generated in the U1201, do not overload baseband chain.
The receiver can be calibrated to optimise IP2 performance, which ensures limited baseband interfering signal amplitude.
The U1201 also features an integrated, fully programmable, sigma-delta fraction-N synthesiser suitable for GPRS multi-slot
operation.
DCOC
Figure 5.4. Receiver block diagram
– 5-5 –
RX LO
source from chip
RF SAW
FILTER
LNA
Antenna
900
T/R
Switch
&
Diplexer
1800
1900