7088 (Flower)
Base band Description and Troubleshooting
The system clock is stopped during sleep mode by disabling the VREG_TCXO.
The PMIC regulator turns off the TCXO, which is from MSM's TCXO_ON output
signal.
Backend IC and Camera Module Clocks
Figure 10: backend IC and camera module clocks
Backend IC (U11) uses external 13MHz crystal (Y210) and internal PLL to generate
internal clocks. Backend IC provides 24MHz clock to camera module. Camera
module uses the 24MHz clock to generate 12MHz pixel clock.
Flash Programming Error Description
This table describes the errors condition during Flash memory downloading to the
mobile terminal.
Description
Packet Checksum fail
Erase fail
Write fail
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© 2006 Nokia Corporation
Not Working Properly
ERR: CRC invalid
Unable to erase device
Write unsuccessfully
Figure 11: Flash Programming Error Description
Company Confidential
Issue 1 12/2006